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Merge branch 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31 26
dc42c8bd
ZC		 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
53c5ec31
SMK		 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
ebeb53e1 33#include <linux/i2c/twl.h>
e8e2ff46 34#include <linux/usb/otg.h>
e8c4a7ac 35#include <linux/usb/musb.h>
78c289f8 36#include <linux/usb/nop-usb-xceiv.h>
562138a4 37#include <linux/smsc911x.h>
53c5ec31 38
741927f7
ER		 39#include <linux/wl12xx.h>
40#include <linux/regulator/fixed.h>
1a7ec135 41#include <linux/regulator/machine.h>
3a63833e 42#include <linux/mmc/host.h>
dc28094b 43#include <linux/export.h>
51482be9 44#include <linux/usb/phy.h>
1a7ec135 45
53c5ec31
SMK		 46#include <asm/mach-types.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/map.h>
49
2203747c 50#include <linux/platform_data/mtd-nand-omap2.h>
4e65331c 51#include "common.h"
2203747c 52#include <linux/platform_data/spi-omap2-mcspi.h>
a0b38cc4 53#include <video/omapdss.h>
dac8eb5f 54#include <video/omap-panel-tfp410.h>
53c5ec31 55
e4c060db 56#include "soc.h"
ca5742bd 57#include "mux.h"
53c5ec31 58#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 59#include "hsmmc.h"
96974a24 60#include "common-board-devices.h"
2e618261
AM		 61#include "board-flash.h"
62
63#define NAND_CS 0
53c5ec31 64
c31cc1b7 65#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 66#define OMAP3_EVM_EHCI_VBUS 22
67#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 68
69#define OMAP3EVM_ETHR_START 0x2c000000
70#define OMAP3EVM_ETHR_SIZE 1024
db408023 71#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 72#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 73#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 74/*
75 * Eth Reset signal
76 * 64 = Generation 1 (<=RevD)
77 * 7 = Generation 2 (>=RevE)
78 */
79#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
80#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 81
e54adb1e
IG		 82/*
83 * OMAP35x EVM revision
84 * Run time detection of EVM revision is done by reading Ethernet
85 * PHY ID -
86 * GEN_1 = 0x01150000
87 * GEN_2 = 0x92200000
88 */
89enum {
90 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
91 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
92};
93
db408023
AKG		 94static u8 omap3_evm_version;
95
695f0117 96static u8 get_omap3_evm_rev(void)
db408023
AKG		 97{
98 return omap3_evm_version;
99}
db408023
AKG		 100
101static void __init omap3_evm_get_revision(void)
102{
103 void __iomem *ioaddr;
104 unsigned int smsc_id;
105
106 /* Ethernet PHY ID is stored at ID_REV register */
107 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
108 if (!ioaddr)
109 return;
110 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
111 iounmap(ioaddr);
112
113 switch (smsc_id) {
114 /*SMSC9115 chipset*/
115 case 0x01150000:
116 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
117 break;
118 /*SMSC 9220 chipset*/
119 case 0x92200000:
120 default:
121 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
122 }
123}
124
562138a4 125#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
ac839b3c 126#include "gpmc-smsc911x.h"
53c5ec31 127
21b42731
MR		 128static struct omap_smsc911x_platform_data smsc911x_cfg = {
129 .cs = OMAP3EVM_SMSC911X_CS,
130 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
131 .gpio_reset = -EINVAL,
132 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 133};
134
562138a4 135static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 136{
9bc64b89
VH		 137 /* Configure ethernet controller reset gpio */
138 if (cpu_is_omap3430()) {
21b42731
MR		 139 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
140 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
141 else
142 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 143 }
144
21b42731 145 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 146}
147
562138a4
S		 148#else
149static inline void __init omap3evm_init_smsc911x(void) { return; }
150#endif
151
703e3061
VH		 152/*
153 * OMAP3EVM LCD Panel control signals
154 */
155#define OMAP3EVM_LCD_PANEL_LR 2
156#define OMAP3EVM_LCD_PANEL_UD 3
157#define OMAP3EVM_LCD_PANEL_INI 152
158#define OMAP3EVM_LCD_PANEL_ENVDD 153
159#define OMAP3EVM_LCD_PANEL_QVGA 154
160#define OMAP3EVM_LCD_PANEL_RESB 155
161#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
162#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
163
bc593f5d
IG		 164static struct gpio omap3_evm_dss_gpios[] __initdata = {
165 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
166 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
167 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
168 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
169 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
170 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
171};
172
703e3061
VH		 173static int lcd_enabled;
174static int dvi_enabled;
175
176static void __init omap3_evm_display_init(void)
177{
178 int r;
179
bc593f5d
IG		 180 r = gpio_request_array(omap3_evm_dss_gpios,
181 ARRAY_SIZE(omap3_evm_dss_gpios));
182 if (r)
183 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 184}
185
186static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
187{
188 if (dvi_enabled) {
189 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
190 return -EINVAL;
191 }
192 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
193
194 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 195 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 196 else
f186e9b2 197 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 198
199 lcd_enabled = 1;
200 return 0;
201}
202
203static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
204{
205 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
206
207 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 208 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 209 else
f186e9b2 210 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 211
212 lcd_enabled = 0;
213}
214
215static struct omap_dss_device omap3_evm_lcd_device = {
216 .name = "lcd",
217 .driver_name = "sharp_ls_panel",
218 .type = OMAP_DISPLAY_TYPE_DPI,
219 .phy.dpi.data_lines = 18,
220 .platform_enable = omap3_evm_enable_lcd,
221 .platform_disable = omap3_evm_disable_lcd,
222};
223
224static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
225{
226 return 0;
227}
228
229static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
230{
231}
232
233static struct omap_dss_device omap3_evm_tv_device = {
234 .name = "tv",
235 .driver_name = "venc",
236 .type = OMAP_DISPLAY_TYPE_VENC,
237 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
238 .platform_enable = omap3_evm_enable_tv,
239 .platform_disable = omap3_evm_disable_tv,
240};
241
2e6f2ee7 242static struct tfp410_platform_data dvi_panel = {
e813a55e 243 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
ca2e16fa 244 .i2c_bus_num = -1,
89747c91
BW		 245};
246
703e3061
VH		 247static struct omap_dss_device omap3_evm_dvi_device = {
248 .name = "dvi",
703e3061 249 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 250 .driver_name = "tfp410",
89747c91 251 .data = &dvi_panel,
703e3061 252 .phy.dpi.data_lines = 24,
703e3061
VH		 253};
254
255static struct omap_dss_device *omap3_evm_dss_devices[] = {
256 &omap3_evm_lcd_device,
257 &omap3_evm_tv_device,
258 &omap3_evm_dvi_device,
259};
260
261static struct omap_dss_board_info omap3_evm_dss_data = {
262 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
263 .devices = omap3_evm_dss_devices,
264 .default_device = &omap3_evm_lcd_device,
265};
266
786b01a8
OD		 267static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
268 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 269};
270
786b01a8
OD		 271static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
272 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 273};
274
275/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
276static struct regulator_init_data omap3evm_vmmc1 = {
277 .constraints = {
278 .min_uV = 1850000,
279 .max_uV = 3150000,
280 .valid_modes_mask = REGULATOR_MODE_NORMAL
281 | REGULATOR_MODE_STANDBY,
282 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
283 | REGULATOR_CHANGE_MODE
284 | REGULATOR_CHANGE_STATUS,
285 },
786b01a8
OD		 286 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
287 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 288};
289
290/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
291static struct regulator_init_data omap3evm_vsim = {
292 .constraints = {
293 .min_uV = 1800000,
294 .max_uV = 3000000,
295 .valid_modes_mask = REGULATOR_MODE_NORMAL
296 | REGULATOR_MODE_STANDBY,
297 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
298 | REGULATOR_CHANGE_MODE
299 | REGULATOR_CHANGE_STATUS,
300 },
786b01a8
OD		 301 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
302 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 303};
304
68ff0423 305static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 306 {
307 .mmc = 1,
3a63833e 308 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 309 .gpio_cd = -EINVAL,
310 .gpio_wp = 63,
3b972bf0 311 .deferred = true,
53c5ec31 312 },
6cc9efed 313#ifdef CONFIG_WILINK_PLATFORM_DATA
741927f7
ER		 314 {
315 .name = "wl1271",
aca6ad07 316 .mmc = 2,
741927f7
ER		 317 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
318 .gpio_wp = -EINVAL,
319 .gpio_cd = -EINVAL,
320 .nonremovable = true,
321 },
322#endif
53c5ec31
SMK		 323 {} /* Terminator */
324};
325
326static struct gpio_led gpio_leds[] = {
327 {
328 .name = "omap3evm::ledb",
329 /* normally not visible (board underside) */
330 .default_trigger = "default-on",
331 .gpio = -EINVAL, /* gets replaced */
332 .active_low = true,
333 },
334};
335
336static struct gpio_led_platform_data gpio_led_info = {
337 .leds = gpio_leds,
338 .num_leds = ARRAY_SIZE(gpio_leds),
339};
340
341static struct platform_device leds_gpio = {
342 .name = "leds-gpio",
343 .id = -1,
344 .dev = {
345 .platform_data = &gpio_led_info,
346 },
347};
348
349
350static int omap3evm_twl_gpio_setup(struct device *dev,
351 unsigned gpio, unsigned ngpio)
352{
bc593f5d 353 int r, lcd_bl_en;
42fc8cab 354
53c5ec31 355 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 356 mmc[0].gpio_cd = gpio + 0;
3b972bf0 357 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 358
359 /*
360 * Most GPIOs are for USB OTG. Some are mostly sent to
361 * the P2 connector; notably LEDA for the LCD backlight.
362 */
363
703e3061 364 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 365 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
366 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
367 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 368 if (r)
369 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 370
371 /* gpio + 7 == DVI Enable */
bc593f5d 372 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 373
53c5ec31 374 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 375 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 376
377 platform_device_register(&leds_gpio);
378
cb8ca589
ZC		 379 /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
380 * for starting USB tranceiver
381 */
b103a2e2 382#ifdef CONFIG_TWL4030_CORE
cb8ca589
ZC		 383 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
384 u8 val;
385
386 twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
387 val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
388 twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
389 }
b103a2e2 390#endif
cb8ca589 391
53c5ec31
SMK		 392 return 0;
393}
394
395static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
53c5ec31
SMK		 396 .use_leds = true,
397 .setup = omap3evm_twl_gpio_setup,
398};
399
bead4375 400static uint32_t board_keymap[] = {
53c5ec31 401 KEY(0, 0, KEY_LEFT),
0621d756
SP		 402 KEY(0, 1, KEY_DOWN),
403 KEY(0, 2, KEY_ENTER),
404 KEY(0, 3, KEY_M),
405
406 KEY(1, 0, KEY_RIGHT),
53c5ec31 407 KEY(1, 1, KEY_UP),
0621d756
SP		 408 KEY(1, 2, KEY_I),
409 KEY(1, 3, KEY_N),
410
411 KEY(2, 0, KEY_A),
412 KEY(2, 1, KEY_E),
53c5ec31 413 KEY(2, 2, KEY_J),
0621d756
SP		 414 KEY(2, 3, KEY_O),
415
416 KEY(3, 0, KEY_B),
417 KEY(3, 1, KEY_F),
418 KEY(3, 2, KEY_K),
53c5ec31
SMK		 419 KEY(3, 3, KEY_P)
420};
421
4f543332
TL		 422static struct matrix_keymap_data board_map_data = {
423 .keymap = board_keymap,
424 .keymap_size = ARRAY_SIZE(board_keymap),
425};
426
53c5ec31 427static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 428 .keymap_data = &board_map_data,
53c5ec31
SMK		 429 .rows = 4,
430 .cols = 4,
53c5ec31
SMK		 431 .rep = 1,
432};
433
410491d4 434/* ads7846 on SPI */
786b01a8
OD		 435static struct regulator_consumer_supply omap3evm_vio_supply[] = {
436 REGULATOR_SUPPLY("vcc", "spi1.0"),
437};
410491d4
VH		 438
439/* VIO for ads7846 */
440static struct regulator_init_data omap3evm_vio = {
441 .constraints = {
442 .min_uV = 1800000,
443 .max_uV = 1800000,
444 .apply_uV = true,
445 .valid_modes_mask = REGULATOR_MODE_NORMAL
446 | REGULATOR_MODE_STANDBY,
447 .valid_ops_mask = REGULATOR_CHANGE_MODE
448 | REGULATOR_CHANGE_STATUS,
449 },
786b01a8
OD		 450 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
451 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 452};
453
6cc9efed 454#ifdef CONFIG_WILINK_PLATFORM_DATA
741927f7
ER		 455
456#define OMAP3EVM_WLAN_PMENA_GPIO (150)
457#define OMAP3EVM_WLAN_IRQ_GPIO (149)
458
786b01a8 459static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 460 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 461};
741927f7
ER		 462
463/* VMMC2 for driving the WL12xx module */
464static struct regulator_init_data omap3evm_vmmc2 = {
465 .constraints = {
466 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
467 },
d19f579a 468 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 469 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 470};
471
472static struct fixed_voltage_config omap3evm_vwlan = {
473 .supply_name = "vwl1271",
474 .microvolts = 1800000, /* 1.80V */
475 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
476 .startup_delay = 70000, /* 70ms */
477 .enable_high = 1,
478 .enabled_at_boot = 0,
479 .init_data = &omap3evm_vmmc2,
480};
481
aca6ad07 482static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 483 .name = "reg-fixed-voltage",
484 .id = 1,
485 .dev = {
486 .platform_data = &omap3evm_vwlan,
487 },
488};
489
490struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 491 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 492};
493#endif
494
497af1f3
ZC		 495/* VAUX2 for USB */
496static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
497 REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
498 REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
499 REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
500 REGULATOR_SUPPLY("vaux2", NULL),
501};
502
503static struct regulator_init_data omap3evm_vaux2 = {
504 .constraints = {
505 .min_uV = 2800000,
506 .max_uV = 2800000,
507 .apply_uV = true,
508 .valid_modes_mask = REGULATOR_MODE_NORMAL
509 | REGULATOR_MODE_STANDBY,
510 .valid_ops_mask = REGULATOR_CHANGE_MODE
511 | REGULATOR_CHANGE_STATUS,
512 },
513 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies),
514 .consumer_supplies = omap3evm_vaux2_supplies,
515};
516
53c5ec31 517static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 518 /* platform_data for children goes here */
519 .keypad = &omap3evm_kp_data,
53c5ec31 520 .gpio = &omap3evm_gpio_data,
410491d4 521 .vio = &omap3evm_vio,
fbd8071c
MR		 522 .vmmc1 = &omap3evm_vmmc1,
523 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 524};
525
526static int __init omap3_evm_i2c_init(void)
527{
827ed9ae 528 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 529 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
530 TWL_COMMON_PDATA_AUDIO,
531 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
532
533 omap3evm_twldata.vdac->constraints.apply_uV = true;
534 omap3evm_twldata.vpll2->constraints.apply_uV = true;
535
fbd8071c 536 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 537 omap_register_i2c_bus(2, 400, NULL, 0);
538 omap_register_i2c_bus(3, 400, NULL, 0);
539 return 0;
540}
541
42973159 542static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
58a5491c 543
181b250c
KM		 544 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
545 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
546 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 547
548 .phy_reset = true,
e8e51d29 549 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 550 .reset_gpio_port[0] = -EINVAL,
e8e51d29 551 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 552 .reset_gpio_port[2] = -EINVAL
553};
554
ca5742bd 555#ifdef CONFIG_OMAP_MUX
904c545c 556static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 557 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 558 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 559 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 560 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 561 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
562 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 563 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
564 OMAP_PIN_OFF_NONE),
565 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
566 OMAP_PIN_OFF_NONE),
6cc9efed 567#ifdef CONFIG_WILINK_PLATFORM_DATA
741927f7 568 /* WLAN IRQ - GPIO 149 */
aca6ad07 569 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 570
571 /* WLAN POWER ENABLE - GPIO 150 */
572 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
573
574 /* MMC2 SDIO pin muxes for WL12xx */
575 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
576 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
577 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
578 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
579 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
580 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
581#endif
ca5742bd
TL		 582 { .reg_offset = OMAP_MUX_TERMINATOR },
583};
904c545c
VH		 584
585static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 586 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 587 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 588 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 589 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 590 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
591 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 592 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
593 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
594 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
595 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
596 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
597 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
598 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
599 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
600 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
601 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
602 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
603 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
604 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
6cc9efed 605#ifdef CONFIG_WILINK_PLATFORM_DATA
aca6ad07
ER		 606 /* WLAN IRQ - GPIO 149 */
607 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
608
609 /* WLAN POWER ENABLE - GPIO 150 */
610 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
611
612 /* MMC2 SDIO pin muxes for WL12xx */
613 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
614 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
615 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
616 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
617 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
618 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
619#endif
904c545c 620
ca5742bd
TL		 621 { .reg_offset = OMAP_MUX_TERMINATOR },
622};
904c545c
VH		 623#else
624#define omap35x_board_mux NULL
625#define omap36x_board_mux NULL
ca5742bd
TL		 626#endif
627
884b8369
MM		 628static struct omap_musb_board_data musb_board_data = {
629 .interface_type = MUSB_INTERFACE_ULPI,
630 .mode = MUSB_OTG,
631 .power = 100,
632};
633
bc593f5d
IG		 634static struct gpio omap3_evm_ehci_gpios[] __initdata = {
635 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
636 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
637};
638
70d669de
RK		 639static void __init omap3_evm_wl12xx_init(void)
640{
6cc9efed 641#ifdef CONFIG_WILINK_PLATFORM_DATA
70d669de
RK		 642 int ret;
643
644 /* WL12xx WLAN Init */
46a0a540 645 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 646 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
647 if (ret)
648 pr_err("error setting wl12xx data: %d\n", ret);
649 ret = platform_device_register(&omap3evm_wlan_regulator);
650 if (ret)
651 pr_err("error registering wl12xx device: %d\n", ret);
652#endif
653}
654
5b3689f4
RD		 655static struct regulator_consumer_supply dummy_supplies[] = {
656 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
657 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
658};
659
dc42c8bd
ZC		 660static struct mtd_partition omap3evm_nand_partitions[] = {
661 /* All the partition sizes are listed in terms of NAND block size */
662 {
663 .name = "X-Loader",
664 .offset = 0,
665 .size = 4*(SZ_128K),
666 .mask_flags = MTD_WRITEABLE
667 },
668 {
669 .name = "U-Boot",
670 .offset = MTDPART_OFS_APPEND,
671 .size = 14*(SZ_128K),
672 .mask_flags = MTD_WRITEABLE
673 },
674 {
675 .name = "U-Boot Env",
676 .offset = MTDPART_OFS_APPEND,
677 .size = 2*(SZ_128K)
678 },
679 {
680 .name = "Kernel",
681 .offset = MTDPART_OFS_APPEND,
682 .size = 40*(SZ_128K)
683 },
684 {
685 .name = "File system",
686 .size = MTDPART_SIZ_FULL,
687 .offset = MTDPART_OFS_APPEND,
688 },
689};
690
53c5ec31
SMK		 691static void __init omap3_evm_init(void)
692{
eeb3711b
PW		 693 struct omap_board_mux *obm;
694
db408023 695 omap3_evm_get_revision();
5b3689f4 696 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c 697
eeb3711b
PW		 698 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
699 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
db408023 700
d1589f09 701 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 702 omap_hsmmc_init(mmc);
d1589f09 703
497af1f3
ZC		 704 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
705 omap3evm_twldata.vaux2 = &omap3evm_vaux2;
706
53c5ec31
SMK		 707 omap3_evm_i2c_init();
708
d5e13227 709 omap_display_init(&omap3_evm_dss_data);
53c5ec31 710
53c5ec31 711 omap_serial_init();
a4ca9dbe 712 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 713
e8e2ff46
GAK		 714 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
715 usb_nop_xceiv_register();
1a4f4637 716
e8e51d29
AKG		 717 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
718 /* enable EHCI VBUS using GPIO22 */
bc593f5d 719 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 720 /* Select EHCI port on main board */
bc593f5d
IG		 721 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
722 OMAP_PIN_INPUT_PULLUP);
723 gpio_request_array(omap3_evm_ehci_gpios,
724 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 725
726 /* setup EHCI phy reset config */
4896e394 727 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 728 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 729
58815fa3
AKG		 730 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
731 musb_board_data.power = 500;
732 musb_board_data.extvbus = 1;
e8e51d29
AKG		 733 } else {
734 /* setup EHCI phy reset on MDC */
4896e394 735 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 736 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 737 }
51482be9 738 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
884b8369 739 usb_musb_init(&musb_board_data);
9e64bb1e 740 usbhs_init(&usbhs_bdata);
2e618261
AM		 741 board_nand_init(omap3evm_nand_partitions,
742 ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
743 NAND_BUSWIDTH_16, NULL);
dc42c8bd 744
96974a24 745 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 746 omap3evm_init_smsc911x();
703e3061 747 omap3_evm_display_init();
70d669de 748 omap3_evm_wl12xx_init();
40234bf7 749 omap_twl4030_audio_init("omap3evm", NULL);
53c5ec31
SMK		 750}
751
53c5ec31
SMK		 752MACHINE_START(OMAP3EVM, "OMAP3 EVM")
753 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 754 .atag_offset = 0x100,
71ee7dad 755 .reserve = omap_reserve,
3dc3bad6 756 .map_io = omap3_map_io,
8f5b5a41 757 .init_early = omap35xx_init_early,
741e3a89 758 .init_irq = omap3_init_irq,
6b2f55d7 759 .handle_irq = omap3_intc_handle_irq,
53c5ec31 760 .init_machine = omap3_evm_init,
bbd707ac 761 .init_late = omap35xx_init_late,
6bb27d73 762 .init_time = omap3_sync32k_timer_init,
187e3e06 763 .restart = omap3xxx_restart,
53c5ec31 764MACHINE_END
Linux kernel - Deliverables
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