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Linux 3.6-rc1
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31 26
dc42c8bd
ZC		 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
53c5ec31
SMK		 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
ebeb53e1 33#include <linux/i2c/twl.h>
e8e2ff46 34#include <linux/usb/otg.h>
562138a4 35#include <linux/smsc911x.h>
53c5ec31 36
741927f7
ER		 37#include <linux/wl12xx.h>
38#include <linux/regulator/fixed.h>
1a7ec135 39#include <linux/regulator/machine.h>
3a63833e 40#include <linux/mmc/host.h>
dc28094b 41#include <linux/export.h>
1a7ec135 42
53c5ec31
SMK		 43#include <mach/hardware.h>
44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47
ce491cf8 48#include <plat/board.h>
ce491cf8 49#include <plat/usb.h>
dc42c8bd 50#include <plat/nand.h>
4e65331c 51#include "common.h"
ce491cf8 52#include <plat/mcspi.h>
a0b38cc4 53#include <video/omapdss.h>
dac8eb5f 54#include <video/omap-panel-tfp410.h>
53c5ec31 55
ca5742bd 56#include "mux.h"
53c5ec31 57#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 58#include "hsmmc.h"
96974a24 59#include "common-board-devices.h"
53c5ec31 60
e8e51d29
AKG		 61#define OMAP3_EVM_EHCI_VBUS 22
62#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 63
64#define OMAP3EVM_ETHR_START 0x2c000000
65#define OMAP3EVM_ETHR_SIZE 1024
db408023 66#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 67#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 68#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 69/*
70 * Eth Reset signal
71 * 64 = Generation 1 (<=RevD)
72 * 7 = Generation 2 (>=RevE)
73 */
74#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
75#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 76
db408023
AKG		 77static u8 omap3_evm_version;
78
79u8 get_omap3_evm_rev(void)
80{
81 return omap3_evm_version;
82}
83EXPORT_SYMBOL(get_omap3_evm_rev);
84
85static void __init omap3_evm_get_revision(void)
86{
87 void __iomem *ioaddr;
88 unsigned int smsc_id;
89
90 /* Ethernet PHY ID is stored at ID_REV register */
91 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
92 if (!ioaddr)
93 return;
94 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
95 iounmap(ioaddr);
96
97 switch (smsc_id) {
98 /*SMSC9115 chipset*/
99 case 0x01150000:
100 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
101 break;
102 /*SMSC 9220 chipset*/
103 case 0x92200000:
104 default:
105 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
106 }
107}
108
562138a4 109#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
21b42731 110#include <plat/gpmc-smsc911x.h>
53c5ec31 111
21b42731
MR		 112static struct omap_smsc911x_platform_data smsc911x_cfg = {
113 .cs = OMAP3EVM_SMSC911X_CS,
114 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
115 .gpio_reset = -EINVAL,
116 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 117};
118
562138a4 119static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 120{
9bc64b89
VH		 121 /* Configure ethernet controller reset gpio */
122 if (cpu_is_omap3430()) {
21b42731
MR		 123 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
124 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
125 else
126 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 127 }
128
21b42731 129 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 130}
131
562138a4
S		 132#else
133static inline void __init omap3evm_init_smsc911x(void) { return; }
134#endif
135
703e3061
VH		 136/*
137 * OMAP3EVM LCD Panel control signals
138 */
139#define OMAP3EVM_LCD_PANEL_LR 2
140#define OMAP3EVM_LCD_PANEL_UD 3
141#define OMAP3EVM_LCD_PANEL_INI 152
142#define OMAP3EVM_LCD_PANEL_ENVDD 153
143#define OMAP3EVM_LCD_PANEL_QVGA 154
144#define OMAP3EVM_LCD_PANEL_RESB 155
145#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
146#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
147
bc593f5d
IG		 148static struct gpio omap3_evm_dss_gpios[] __initdata = {
149 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
150 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
151 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
152 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
153 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
154 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
155};
156
703e3061
VH		 157static int lcd_enabled;
158static int dvi_enabled;
159
160static void __init omap3_evm_display_init(void)
161{
162 int r;
163
bc593f5d
IG		 164 r = gpio_request_array(omap3_evm_dss_gpios,
165 ARRAY_SIZE(omap3_evm_dss_gpios));
166 if (r)
167 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 168}
169
170static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
171{
172 if (dvi_enabled) {
173 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
174 return -EINVAL;
175 }
176 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
177
178 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 179 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 180 else
f186e9b2 181 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 182
183 lcd_enabled = 1;
184 return 0;
185}
186
187static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
188{
189 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
190
191 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 192 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 193 else
f186e9b2 194 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 195
196 lcd_enabled = 0;
197}
198
199static struct omap_dss_device omap3_evm_lcd_device = {
200 .name = "lcd",
201 .driver_name = "sharp_ls_panel",
202 .type = OMAP_DISPLAY_TYPE_DPI,
203 .phy.dpi.data_lines = 18,
204 .platform_enable = omap3_evm_enable_lcd,
205 .platform_disable = omap3_evm_disable_lcd,
206};
207
208static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
209{
210 return 0;
211}
212
213static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
214{
215}
216
217static struct omap_dss_device omap3_evm_tv_device = {
218 .name = "tv",
219 .driver_name = "venc",
220 .type = OMAP_DISPLAY_TYPE_VENC,
221 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
222 .platform_enable = omap3_evm_enable_tv,
223 .platform_disable = omap3_evm_disable_tv,
224};
225
2e6f2ee7 226static struct tfp410_platform_data dvi_panel = {
e813a55e 227 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
89747c91
BW		 228};
229
703e3061
VH		 230static struct omap_dss_device omap3_evm_dvi_device = {
231 .name = "dvi",
703e3061 232 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 233 .driver_name = "tfp410",
89747c91 234 .data = &dvi_panel,
703e3061 235 .phy.dpi.data_lines = 24,
703e3061
VH		 236};
237
238static struct omap_dss_device *omap3_evm_dss_devices[] = {
239 &omap3_evm_lcd_device,
240 &omap3_evm_tv_device,
241 &omap3_evm_dvi_device,
242};
243
244static struct omap_dss_board_info omap3_evm_dss_data = {
245 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
246 .devices = omap3_evm_dss_devices,
247 .default_device = &omap3_evm_lcd_device,
248};
249
786b01a8
OD		 250static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
251 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 252};
253
786b01a8
OD		 254static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
255 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 256};
257
258/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
259static struct regulator_init_data omap3evm_vmmc1 = {
260 .constraints = {
261 .min_uV = 1850000,
262 .max_uV = 3150000,
263 .valid_modes_mask = REGULATOR_MODE_NORMAL
264 | REGULATOR_MODE_STANDBY,
265 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
266 | REGULATOR_CHANGE_MODE
267 | REGULATOR_CHANGE_STATUS,
268 },
786b01a8
OD		 269 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
270 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 271};
272
273/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
274static struct regulator_init_data omap3evm_vsim = {
275 .constraints = {
276 .min_uV = 1800000,
277 .max_uV = 3000000,
278 .valid_modes_mask = REGULATOR_MODE_NORMAL
279 | REGULATOR_MODE_STANDBY,
280 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
281 | REGULATOR_CHANGE_MODE
282 | REGULATOR_CHANGE_STATUS,
283 },
786b01a8
OD		 284 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
285 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 286};
287
68ff0423 288static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 289 {
290 .mmc = 1,
3a63833e 291 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 292 .gpio_cd = -EINVAL,
293 .gpio_wp = 63,
3b972bf0 294 .deferred = true,
53c5ec31 295 },
741927f7
ER		 296#ifdef CONFIG_WL12XX_PLATFORM_DATA
297 {
298 .name = "wl1271",
aca6ad07 299 .mmc = 2,
741927f7
ER		 300 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
301 .gpio_wp = -EINVAL,
302 .gpio_cd = -EINVAL,
303 .nonremovable = true,
304 },
305#endif
53c5ec31
SMK		 306 {} /* Terminator */
307};
308
309static struct gpio_led gpio_leds[] = {
310 {
311 .name = "omap3evm::ledb",
312 /* normally not visible (board underside) */
313 .default_trigger = "default-on",
314 .gpio = -EINVAL, /* gets replaced */
315 .active_low = true,
316 },
317};
318
319static struct gpio_led_platform_data gpio_led_info = {
320 .leds = gpio_leds,
321 .num_leds = ARRAY_SIZE(gpio_leds),
322};
323
324static struct platform_device leds_gpio = {
325 .name = "leds-gpio",
326 .id = -1,
327 .dev = {
328 .platform_data = &gpio_led_info,
329 },
330};
331
332
333static int omap3evm_twl_gpio_setup(struct device *dev,
334 unsigned gpio, unsigned ngpio)
335{
bc593f5d 336 int r, lcd_bl_en;
42fc8cab 337
53c5ec31 338 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 339 mmc[0].gpio_cd = gpio + 0;
3b972bf0 340 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 341
342 /*
343 * Most GPIOs are for USB OTG. Some are mostly sent to
344 * the P2 connector; notably LEDA for the LCD backlight.
345 */
346
703e3061 347 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 348 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
349 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
350 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 351 if (r)
352 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 353
354 /* gpio + 7 == DVI Enable */
bc593f5d 355 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 356
53c5ec31 357 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 358 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 359
360 platform_device_register(&leds_gpio);
361
cb8ca589
ZC		 362 /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
363 * for starting USB tranceiver
364 */
b103a2e2 365#ifdef CONFIG_TWL4030_CORE
cb8ca589
ZC		 366 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
367 u8 val;
368
369 twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
370 val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
371 twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
372 }
b103a2e2 373#endif
cb8ca589 374
53c5ec31
SMK		 375 return 0;
376}
377
378static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
379 .gpio_base = OMAP_MAX_GPIO_LINES,
380 .irq_base = TWL4030_GPIO_IRQ_BASE,
381 .irq_end = TWL4030_GPIO_IRQ_END,
382 .use_leds = true,
383 .setup = omap3evm_twl_gpio_setup,
384};
385
bead4375 386static uint32_t board_keymap[] = {
53c5ec31 387 KEY(0, 0, KEY_LEFT),
0621d756
SP		 388 KEY(0, 1, KEY_DOWN),
389 KEY(0, 2, KEY_ENTER),
390 KEY(0, 3, KEY_M),
391
392 KEY(1, 0, KEY_RIGHT),
53c5ec31 393 KEY(1, 1, KEY_UP),
0621d756
SP		 394 KEY(1, 2, KEY_I),
395 KEY(1, 3, KEY_N),
396
397 KEY(2, 0, KEY_A),
398 KEY(2, 1, KEY_E),
53c5ec31 399 KEY(2, 2, KEY_J),
0621d756
SP		 400 KEY(2, 3, KEY_O),
401
402 KEY(3, 0, KEY_B),
403 KEY(3, 1, KEY_F),
404 KEY(3, 2, KEY_K),
53c5ec31
SMK		 405 KEY(3, 3, KEY_P)
406};
407
4f543332
TL		 408static struct matrix_keymap_data board_map_data = {
409 .keymap = board_keymap,
410 .keymap_size = ARRAY_SIZE(board_keymap),
411};
412
53c5ec31 413static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 414 .keymap_data = &board_map_data,
53c5ec31
SMK		 415 .rows = 4,
416 .cols = 4,
53c5ec31
SMK		 417 .rep = 1,
418};
419
410491d4 420/* ads7846 on SPI */
786b01a8
OD		 421static struct regulator_consumer_supply omap3evm_vio_supply[] = {
422 REGULATOR_SUPPLY("vcc", "spi1.0"),
423};
410491d4
VH		 424
425/* VIO for ads7846 */
426static struct regulator_init_data omap3evm_vio = {
427 .constraints = {
428 .min_uV = 1800000,
429 .max_uV = 1800000,
430 .apply_uV = true,
431 .valid_modes_mask = REGULATOR_MODE_NORMAL
432 | REGULATOR_MODE_STANDBY,
433 .valid_ops_mask = REGULATOR_CHANGE_MODE
434 | REGULATOR_CHANGE_STATUS,
435 },
786b01a8
OD		 436 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
437 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 438};
439
741927f7
ER		 440#ifdef CONFIG_WL12XX_PLATFORM_DATA
441
442#define OMAP3EVM_WLAN_PMENA_GPIO (150)
443#define OMAP3EVM_WLAN_IRQ_GPIO (149)
444
786b01a8 445static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 446 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 447};
741927f7
ER		 448
449/* VMMC2 for driving the WL12xx module */
450static struct regulator_init_data omap3evm_vmmc2 = {
451 .constraints = {
452 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
453 },
d19f579a 454 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 455 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 456};
457
458static struct fixed_voltage_config omap3evm_vwlan = {
459 .supply_name = "vwl1271",
460 .microvolts = 1800000, /* 1.80V */
461 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
462 .startup_delay = 70000, /* 70ms */
463 .enable_high = 1,
464 .enabled_at_boot = 0,
465 .init_data = &omap3evm_vmmc2,
466};
467
aca6ad07 468static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 469 .name = "reg-fixed-voltage",
470 .id = 1,
471 .dev = {
472 .platform_data = &omap3evm_vwlan,
473 },
474};
475
476struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 477 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 478};
479#endif
480
497af1f3
ZC		 481/* VAUX2 for USB */
482static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
483 REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
484 REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
485 REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
486 REGULATOR_SUPPLY("vaux2", NULL),
487};
488
489static struct regulator_init_data omap3evm_vaux2 = {
490 .constraints = {
491 .min_uV = 2800000,
492 .max_uV = 2800000,
493 .apply_uV = true,
494 .valid_modes_mask = REGULATOR_MODE_NORMAL
495 | REGULATOR_MODE_STANDBY,
496 .valid_ops_mask = REGULATOR_CHANGE_MODE
497 | REGULATOR_CHANGE_STATUS,
498 },
499 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies),
500 .consumer_supplies = omap3evm_vaux2_supplies,
501};
502
53c5ec31 503static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 504 /* platform_data for children goes here */
505 .keypad = &omap3evm_kp_data,
53c5ec31 506 .gpio = &omap3evm_gpio_data,
410491d4 507 .vio = &omap3evm_vio,
fbd8071c
MR		 508 .vmmc1 = &omap3evm_vmmc1,
509 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 510};
511
512static int __init omap3_evm_i2c_init(void)
513{
827ed9ae 514 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 515 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
516 TWL_COMMON_PDATA_AUDIO,
517 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
518
519 omap3evm_twldata.vdac->constraints.apply_uV = true;
520 omap3evm_twldata.vpll2->constraints.apply_uV = true;
521
fbd8071c 522 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 523 omap_register_i2c_bus(2, 400, NULL, 0);
524 omap_register_i2c_bus(3, 400, NULL, 0);
525 return 0;
526}
527
b3c6df3a 528static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
b3c6df3a
PW		 529};
530
181b250c 531static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 532
181b250c
KM		 533 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
534 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
535 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 536
537 .phy_reset = true,
e8e51d29 538 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 539 .reset_gpio_port[0] = -EINVAL,
e8e51d29 540 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 541 .reset_gpio_port[2] = -EINVAL
542};
543
ca5742bd 544#ifdef CONFIG_OMAP_MUX
904c545c 545static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 546 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 547 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 548 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 549 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 550 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
551 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 552 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
553 OMAP_PIN_OFF_NONE),
554 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
555 OMAP_PIN_OFF_NONE),
741927f7
ER		 556#ifdef CONFIG_WL12XX_PLATFORM_DATA
557 /* WLAN IRQ - GPIO 149 */
aca6ad07 558 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 559
560 /* WLAN POWER ENABLE - GPIO 150 */
561 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
562
563 /* MMC2 SDIO pin muxes for WL12xx */
564 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
565 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
566 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
567 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
568 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
569 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
570#endif
ca5742bd
TL		 571 { .reg_offset = OMAP_MUX_TERMINATOR },
572};
904c545c
VH		 573
574static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 575 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 576 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 577 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 578 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 579 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
580 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 581 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
582 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
583 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
584 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
585 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
586 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
587 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
588 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
589 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
590 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
591 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
592 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
593 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 594#ifdef CONFIG_WL12XX_PLATFORM_DATA
595 /* WLAN IRQ - GPIO 149 */
596 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
597
598 /* WLAN POWER ENABLE - GPIO 150 */
599 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
600
601 /* MMC2 SDIO pin muxes for WL12xx */
602 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
603 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
604 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
605 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
606 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
607 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
608#endif
904c545c 609
ca5742bd
TL		 610 { .reg_offset = OMAP_MUX_TERMINATOR },
611};
904c545c
VH		 612#else
613#define omap35x_board_mux NULL
614#define omap36x_board_mux NULL
ca5742bd
TL		 615#endif
616
884b8369
MM		 617static struct omap_musb_board_data musb_board_data = {
618 .interface_type = MUSB_INTERFACE_ULPI,
619 .mode = MUSB_OTG,
620 .power = 100,
621};
622
bc593f5d
IG		 623static struct gpio omap3_evm_ehci_gpios[] __initdata = {
624 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
625 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
626};
627
70d669de
RK		 628static void __init omap3_evm_wl12xx_init(void)
629{
630#ifdef CONFIG_WL12XX_PLATFORM_DATA
631 int ret;
632
633 /* WL12xx WLAN Init */
46a0a540 634 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 635 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
636 if (ret)
637 pr_err("error setting wl12xx data: %d\n", ret);
638 ret = platform_device_register(&omap3evm_wlan_regulator);
639 if (ret)
640 pr_err("error registering wl12xx device: %d\n", ret);
641#endif
642}
643
5b3689f4
RD		 644static struct regulator_consumer_supply dummy_supplies[] = {
645 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
646 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
647};
648
dc42c8bd
ZC		 649static struct mtd_partition omap3evm_nand_partitions[] = {
650 /* All the partition sizes are listed in terms of NAND block size */
651 {
652 .name = "X-Loader",
653 .offset = 0,
654 .size = 4*(SZ_128K),
655 .mask_flags = MTD_WRITEABLE
656 },
657 {
658 .name = "U-Boot",
659 .offset = MTDPART_OFS_APPEND,
660 .size = 14*(SZ_128K),
661 .mask_flags = MTD_WRITEABLE
662 },
663 {
664 .name = "U-Boot Env",
665 .offset = MTDPART_OFS_APPEND,
666 .size = 2*(SZ_128K)
667 },
668 {
669 .name = "Kernel",
670 .offset = MTDPART_OFS_APPEND,
671 .size = 40*(SZ_128K)
672 },
673 {
674 .name = "File system",
675 .size = MTDPART_SIZ_FULL,
676 .offset = MTDPART_OFS_APPEND,
677 },
678};
679
53c5ec31
SMK		 680static void __init omap3_evm_init(void)
681{
eeb3711b
PW		 682 struct omap_board_mux *obm;
683
db408023 684 omap3_evm_get_revision();
5b3689f4 685 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c 686
eeb3711b
PW		 687 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
688 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
db408023 689
e41cccfe
TL		 690 omap_board_config = omap3_evm_config;
691 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
db408023 692
d1589f09 693 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 694 omap_hsmmc_init(mmc);
d1589f09 695
497af1f3
ZC		 696 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
697 omap3evm_twldata.vaux2 = &omap3evm_vaux2;
698
53c5ec31
SMK		 699 omap3_evm_i2c_init();
700
d5e13227 701 omap_display_init(&omap3_evm_dss_data);
53c5ec31 702
53c5ec31 703 omap_serial_init();
a4ca9dbe 704 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 705
e8e2ff46
GAK		 706 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
707 usb_nop_xceiv_register();
1a4f4637 708
e8e51d29
AKG		 709 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
710 /* enable EHCI VBUS using GPIO22 */
bc593f5d 711 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 712 /* Select EHCI port on main board */
bc593f5d
IG		 713 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
714 OMAP_PIN_INPUT_PULLUP);
715 gpio_request_array(omap3_evm_ehci_gpios,
716 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 717
718 /* setup EHCI phy reset config */
4896e394 719 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 720 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 721
58815fa3
AKG		 722 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
723 musb_board_data.power = 500;
724 musb_board_data.extvbus = 1;
e8e51d29
AKG		 725 } else {
726 /* setup EHCI phy reset on MDC */
4896e394 727 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 728 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 729 }
884b8369 730 usb_musb_init(&musb_board_data);
9e64bb1e 731 usbhs_init(&usbhs_bdata);
dc42c8bd
ZC		 732 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
733 ARRAY_SIZE(omap3evm_nand_partitions));
734
96974a24 735 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 736 omap3evm_init_smsc911x();
703e3061 737 omap3_evm_display_init();
70d669de 738 omap3_evm_wl12xx_init();
53c5ec31
SMK		 739}
740
53c5ec31
SMK		 741MACHINE_START(OMAP3EVM, "OMAP3 EVM")
742 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 743 .atag_offset = 0x100,
71ee7dad 744 .reserve = omap_reserve,
3dc3bad6 745 .map_io = omap3_map_io,
8f5b5a41 746 .init_early = omap35xx_init_early,
741e3a89 747 .init_irq = omap3_init_irq,
6b2f55d7 748 .handle_irq = omap3_intc_handle_irq,
53c5ec31 749 .init_machine = omap3_evm_init,
bbd707ac 750 .init_late = omap35xx_init_late,
e74984e4 751 .timer = &omap3_timer,
baa95883 752 .restart = omap_prcm_restart,
53c5ec31 753MACHINE_END
Linux kernel - Deliverables
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