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ARM: OMAP1: board files: deduplicate and clean some NAND-related code
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31
SMK		 26
27#include <linux/spi/spi.h>
28#include <linux/spi/ads7846.h>
ebeb53e1 29#include <linux/i2c/twl.h>
e8e2ff46 30#include <linux/usb/otg.h>
562138a4 31#include <linux/smsc911x.h>
53c5ec31 32
741927f7
ER		 33#include <linux/wl12xx.h>
34#include <linux/regulator/fixed.h>
1a7ec135 35#include <linux/regulator/machine.h>
3a63833e 36#include <linux/mmc/host.h>
dc28094b 37#include <linux/export.h>
1a7ec135 38
53c5ec31
SMK		 39#include <mach/hardware.h>
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43
ce491cf8 44#include <plat/board.h>
ce491cf8 45#include <plat/usb.h>
4e65331c 46#include "common.h"
ce491cf8 47#include <plat/mcspi.h>
a0b38cc4 48#include <video/omapdss.h>
1d7a8654 49#include <video/omap-panel-dvi.h>
53c5ec31 50
ca5742bd 51#include "mux.h"
53c5ec31 52#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 53#include "hsmmc.h"
96974a24 54#include "common-board-devices.h"
53c5ec31
SMK		 55
56#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 57#define OMAP3_EVM_EHCI_VBUS 22
58#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 59
60#define OMAP3EVM_ETHR_START 0x2c000000
61#define OMAP3EVM_ETHR_SIZE 1024
db408023 62#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 63#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 64#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 65/*
66 * Eth Reset signal
67 * 64 = Generation 1 (<=RevD)
68 * 7 = Generation 2 (>=RevE)
69 */
70#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
71#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 72
db408023
AKG		 73static u8 omap3_evm_version;
74
75u8 get_omap3_evm_rev(void)
76{
77 return omap3_evm_version;
78}
79EXPORT_SYMBOL(get_omap3_evm_rev);
80
81static void __init omap3_evm_get_revision(void)
82{
83 void __iomem *ioaddr;
84 unsigned int smsc_id;
85
86 /* Ethernet PHY ID is stored at ID_REV register */
87 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
88 if (!ioaddr)
89 return;
90 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
91 iounmap(ioaddr);
92
93 switch (smsc_id) {
94 /*SMSC9115 chipset*/
95 case 0x01150000:
96 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
97 break;
98 /*SMSC 9220 chipset*/
99 case 0x92200000:
100 default:
101 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
102 }
103}
104
562138a4 105#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
21b42731 106#include <plat/gpmc-smsc911x.h>
53c5ec31 107
21b42731
MR		 108static struct omap_smsc911x_platform_data smsc911x_cfg = {
109 .cs = OMAP3EVM_SMSC911X_CS,
110 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
111 .gpio_reset = -EINVAL,
112 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 113};
114
562138a4 115static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 116{
9bc64b89
VH		 117 /* Configure ethernet controller reset gpio */
118 if (cpu_is_omap3430()) {
21b42731
MR		 119 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
120 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
121 else
122 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 123 }
124
21b42731 125 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 126}
127
562138a4
S		 128#else
129static inline void __init omap3evm_init_smsc911x(void) { return; }
130#endif
131
703e3061
VH		 132/*
133 * OMAP3EVM LCD Panel control signals
134 */
135#define OMAP3EVM_LCD_PANEL_LR 2
136#define OMAP3EVM_LCD_PANEL_UD 3
137#define OMAP3EVM_LCD_PANEL_INI 152
138#define OMAP3EVM_LCD_PANEL_ENVDD 153
139#define OMAP3EVM_LCD_PANEL_QVGA 154
140#define OMAP3EVM_LCD_PANEL_RESB 155
141#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
142#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
143
bc593f5d
IG		 144static struct gpio omap3_evm_dss_gpios[] __initdata = {
145 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
146 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
147 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
148 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
149 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
150 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
151};
152
703e3061
VH		 153static int lcd_enabled;
154static int dvi_enabled;
155
156static void __init omap3_evm_display_init(void)
157{
158 int r;
159
bc593f5d
IG		 160 r = gpio_request_array(omap3_evm_dss_gpios,
161 ARRAY_SIZE(omap3_evm_dss_gpios));
162 if (r)
163 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 164}
165
166static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
167{
168 if (dvi_enabled) {
169 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
170 return -EINVAL;
171 }
172 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
173
174 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 175 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 176 else
f186e9b2 177 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 178
179 lcd_enabled = 1;
180 return 0;
181}
182
183static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
184{
185 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
186
187 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 188 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 189 else
f186e9b2 190 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 191
192 lcd_enabled = 0;
193}
194
195static struct omap_dss_device omap3_evm_lcd_device = {
196 .name = "lcd",
197 .driver_name = "sharp_ls_panel",
198 .type = OMAP_DISPLAY_TYPE_DPI,
199 .phy.dpi.data_lines = 18,
200 .platform_enable = omap3_evm_enable_lcd,
201 .platform_disable = omap3_evm_disable_lcd,
202};
203
204static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
205{
206 return 0;
207}
208
209static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
210{
211}
212
213static struct omap_dss_device omap3_evm_tv_device = {
214 .name = "tv",
215 .driver_name = "venc",
216 .type = OMAP_DISPLAY_TYPE_VENC,
217 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
218 .platform_enable = omap3_evm_enable_tv,
219 .platform_disable = omap3_evm_disable_tv,
220};
221
222static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
223{
224 if (lcd_enabled) {
225 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
226 return -EINVAL;
227 }
228
f186e9b2 229 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
703e3061
VH		 230
231 dvi_enabled = 1;
232 return 0;
233}
234
235static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
236{
f186e9b2 237 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
703e3061
VH		 238
239 dvi_enabled = 0;
240}
241
1d7a8654 242static struct panel_dvi_platform_data dvi_panel = {
89747c91
BW		 243 .platform_enable = omap3_evm_enable_dvi,
244 .platform_disable = omap3_evm_disable_dvi,
245};
246
703e3061
VH		 247static struct omap_dss_device omap3_evm_dvi_device = {
248 .name = "dvi",
703e3061 249 .type = OMAP_DISPLAY_TYPE_DPI,
1d7a8654 250 .driver_name = "dvi",
89747c91 251 .data = &dvi_panel,
703e3061 252 .phy.dpi.data_lines = 24,
703e3061
VH		 253};
254
255static struct omap_dss_device *omap3_evm_dss_devices[] = {
256 &omap3_evm_lcd_device,
257 &omap3_evm_tv_device,
258 &omap3_evm_dvi_device,
259};
260
261static struct omap_dss_board_info omap3_evm_dss_data = {
262 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
263 .devices = omap3_evm_dss_devices,
264 .default_device = &omap3_evm_lcd_device,
265};
266
786b01a8
OD		 267static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
268 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 269};
270
786b01a8
OD		 271static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
272 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 273};
274
275/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
276static struct regulator_init_data omap3evm_vmmc1 = {
277 .constraints = {
278 .min_uV = 1850000,
279 .max_uV = 3150000,
280 .valid_modes_mask = REGULATOR_MODE_NORMAL
281 | REGULATOR_MODE_STANDBY,
282 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
283 | REGULATOR_CHANGE_MODE
284 | REGULATOR_CHANGE_STATUS,
285 },
786b01a8
OD		 286 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
287 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 288};
289
290/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
291static struct regulator_init_data omap3evm_vsim = {
292 .constraints = {
293 .min_uV = 1800000,
294 .max_uV = 3000000,
295 .valid_modes_mask = REGULATOR_MODE_NORMAL
296 | REGULATOR_MODE_STANDBY,
297 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
298 | REGULATOR_CHANGE_MODE
299 | REGULATOR_CHANGE_STATUS,
300 },
786b01a8
OD		 301 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
302 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 303};
304
68ff0423 305static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 306 {
307 .mmc = 1,
3a63833e 308 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 309 .gpio_cd = -EINVAL,
310 .gpio_wp = 63,
3b972bf0 311 .deferred = true,
53c5ec31 312 },
741927f7
ER		 313#ifdef CONFIG_WL12XX_PLATFORM_DATA
314 {
315 .name = "wl1271",
aca6ad07 316 .mmc = 2,
741927f7
ER		 317 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
318 .gpio_wp = -EINVAL,
319 .gpio_cd = -EINVAL,
320 .nonremovable = true,
321 },
322#endif
53c5ec31
SMK		 323 {} /* Terminator */
324};
325
326static struct gpio_led gpio_leds[] = {
327 {
328 .name = "omap3evm::ledb",
329 /* normally not visible (board underside) */
330 .default_trigger = "default-on",
331 .gpio = -EINVAL, /* gets replaced */
332 .active_low = true,
333 },
334};
335
336static struct gpio_led_platform_data gpio_led_info = {
337 .leds = gpio_leds,
338 .num_leds = ARRAY_SIZE(gpio_leds),
339};
340
341static struct platform_device leds_gpio = {
342 .name = "leds-gpio",
343 .id = -1,
344 .dev = {
345 .platform_data = &gpio_led_info,
346 },
347};
348
349
350static int omap3evm_twl_gpio_setup(struct device *dev,
351 unsigned gpio, unsigned ngpio)
352{
bc593f5d 353 int r, lcd_bl_en;
42fc8cab 354
53c5ec31 355 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 356 mmc[0].gpio_cd = gpio + 0;
3b972bf0 357 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 358
359 /*
360 * Most GPIOs are for USB OTG. Some are mostly sent to
361 * the P2 connector; notably LEDA for the LCD backlight.
362 */
363
703e3061 364 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 365 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
366 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
367 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 368 if (r)
369 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 370
371 /* gpio + 7 == DVI Enable */
bc593f5d 372 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 373
53c5ec31 374 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 375 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 376
377 platform_device_register(&leds_gpio);
378
379 return 0;
380}
381
382static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
383 .gpio_base = OMAP_MAX_GPIO_LINES,
384 .irq_base = TWL4030_GPIO_IRQ_BASE,
385 .irq_end = TWL4030_GPIO_IRQ_END,
386 .use_leds = true,
387 .setup = omap3evm_twl_gpio_setup,
388};
389
bead4375 390static uint32_t board_keymap[] = {
53c5ec31 391 KEY(0, 0, KEY_LEFT),
0621d756
SP		 392 KEY(0, 1, KEY_DOWN),
393 KEY(0, 2, KEY_ENTER),
394 KEY(0, 3, KEY_M),
395
396 KEY(1, 0, KEY_RIGHT),
53c5ec31 397 KEY(1, 1, KEY_UP),
0621d756
SP		 398 KEY(1, 2, KEY_I),
399 KEY(1, 3, KEY_N),
400
401 KEY(2, 0, KEY_A),
402 KEY(2, 1, KEY_E),
53c5ec31 403 KEY(2, 2, KEY_J),
0621d756
SP		 404 KEY(2, 3, KEY_O),
405
406 KEY(3, 0, KEY_B),
407 KEY(3, 1, KEY_F),
408 KEY(3, 2, KEY_K),
53c5ec31
SMK		 409 KEY(3, 3, KEY_P)
410};
411
4f543332
TL		 412static struct matrix_keymap_data board_map_data = {
413 .keymap = board_keymap,
414 .keymap_size = ARRAY_SIZE(board_keymap),
415};
416
53c5ec31 417static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 418 .keymap_data = &board_map_data,
53c5ec31
SMK		 419 .rows = 4,
420 .cols = 4,
53c5ec31
SMK		 421 .rep = 1,
422};
423
410491d4 424/* ads7846 on SPI */
786b01a8
OD		 425static struct regulator_consumer_supply omap3evm_vio_supply[] = {
426 REGULATOR_SUPPLY("vcc", "spi1.0"),
427};
410491d4
VH		 428
429/* VIO for ads7846 */
430static struct regulator_init_data omap3evm_vio = {
431 .constraints = {
432 .min_uV = 1800000,
433 .max_uV = 1800000,
434 .apply_uV = true,
435 .valid_modes_mask = REGULATOR_MODE_NORMAL
436 | REGULATOR_MODE_STANDBY,
437 .valid_ops_mask = REGULATOR_CHANGE_MODE
438 | REGULATOR_CHANGE_STATUS,
439 },
786b01a8
OD		 440 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
441 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 442};
443
741927f7
ER		 444#ifdef CONFIG_WL12XX_PLATFORM_DATA
445
446#define OMAP3EVM_WLAN_PMENA_GPIO (150)
447#define OMAP3EVM_WLAN_IRQ_GPIO (149)
448
786b01a8 449static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 450 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 451};
741927f7
ER		 452
453/* VMMC2 for driving the WL12xx module */
454static struct regulator_init_data omap3evm_vmmc2 = {
455 .constraints = {
456 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
457 },
d19f579a 458 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 459 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 460};
461
462static struct fixed_voltage_config omap3evm_vwlan = {
463 .supply_name = "vwl1271",
464 .microvolts = 1800000, /* 1.80V */
465 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
466 .startup_delay = 70000, /* 70ms */
467 .enable_high = 1,
468 .enabled_at_boot = 0,
469 .init_data = &omap3evm_vmmc2,
470};
471
aca6ad07 472static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 473 .name = "reg-fixed-voltage",
474 .id = 1,
475 .dev = {
476 .platform_data = &omap3evm_vwlan,
477 },
478};
479
480struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 481 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 482};
483#endif
484
53c5ec31 485static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 486 /* platform_data for children goes here */
487 .keypad = &omap3evm_kp_data,
53c5ec31 488 .gpio = &omap3evm_gpio_data,
410491d4 489 .vio = &omap3evm_vio,
fbd8071c
MR		 490 .vmmc1 = &omap3evm_vmmc1,
491 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 492};
493
494static int __init omap3_evm_i2c_init(void)
495{
827ed9ae 496 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 497 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
498 TWL_COMMON_PDATA_AUDIO,
499 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
500
501 omap3evm_twldata.vdac->constraints.apply_uV = true;
502 omap3evm_twldata.vpll2->constraints.apply_uV = true;
503
fbd8071c 504 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 505 omap_register_i2c_bus(2, 400, NULL, 0);
506 omap_register_i2c_bus(3, 400, NULL, 0);
507 return 0;
508}
509
b3c6df3a 510static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
b3c6df3a
PW		 511};
512
181b250c 513static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 514
181b250c
KM		 515 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
516 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
517 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 518
519 .phy_reset = true,
e8e51d29 520 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 521 .reset_gpio_port[0] = -EINVAL,
e8e51d29 522 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 523 .reset_gpio_port[2] = -EINVAL
524};
525
ca5742bd 526#ifdef CONFIG_OMAP_MUX
904c545c 527static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 528 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 529 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 530 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 531 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 532 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
533 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 534 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
535 OMAP_PIN_OFF_NONE),
536 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
537 OMAP_PIN_OFF_NONE),
741927f7
ER		 538#ifdef CONFIG_WL12XX_PLATFORM_DATA
539 /* WLAN IRQ - GPIO 149 */
aca6ad07 540 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 541
542 /* WLAN POWER ENABLE - GPIO 150 */
543 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
544
545 /* MMC2 SDIO pin muxes for WL12xx */
546 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
547 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
548 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
549 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
550 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
551 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
552#endif
ca5742bd
TL		 553 { .reg_offset = OMAP_MUX_TERMINATOR },
554};
904c545c
VH		 555
556static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 557 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 558 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 559 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 560 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 561 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
562 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 563 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
564 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
565 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
566 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
567 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
568 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
569 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
570 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
571 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
572 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
573 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
574 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
575 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 576#ifdef CONFIG_WL12XX_PLATFORM_DATA
577 /* WLAN IRQ - GPIO 149 */
578 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
579
580 /* WLAN POWER ENABLE - GPIO 150 */
581 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
582
583 /* MMC2 SDIO pin muxes for WL12xx */
584 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
585 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
586 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
587 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
588 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
589 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
590#endif
904c545c 591
ca5742bd
TL		 592 { .reg_offset = OMAP_MUX_TERMINATOR },
593};
904c545c
VH		 594#else
595#define omap35x_board_mux NULL
596#define omap36x_board_mux NULL
ca5742bd
TL		 597#endif
598
884b8369
MM		 599static struct omap_musb_board_data musb_board_data = {
600 .interface_type = MUSB_INTERFACE_ULPI,
601 .mode = MUSB_OTG,
602 .power = 100,
603};
604
bc593f5d
IG		 605static struct gpio omap3_evm_ehci_gpios[] __initdata = {
606 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
607 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
608};
609
70d669de
RK		 610static void __init omap3_evm_wl12xx_init(void)
611{
612#ifdef CONFIG_WL12XX_PLATFORM_DATA
613 int ret;
614
615 /* WL12xx WLAN Init */
46a0a540 616 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 617 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
618 if (ret)
619 pr_err("error setting wl12xx data: %d\n", ret);
620 ret = platform_device_register(&omap3evm_wlan_regulator);
621 if (ret)
622 pr_err("error registering wl12xx device: %d\n", ret);
623#endif
624}
625
5b3689f4
RD		 626static struct regulator_consumer_supply dummy_supplies[] = {
627 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
628 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
629};
630
53c5ec31
SMK		 631static void __init omap3_evm_init(void)
632{
db408023 633 omap3_evm_get_revision();
5b3689f4 634 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c
VH		 635
636 if (cpu_is_omap3630())
637 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
638 else
639 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
db408023 640
e41cccfe
TL		 641 omap_board_config = omap3_evm_config;
642 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
db408023 643
d1589f09 644 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 645 omap_hsmmc_init(mmc);
d1589f09 646
53c5ec31
SMK		 647 omap3_evm_i2c_init();
648
d5e13227 649 omap_display_init(&omap3_evm_dss_data);
53c5ec31 650
53c5ec31 651 omap_serial_init();
a4ca9dbe 652 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 653
e8e2ff46
GAK		 654 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
655 usb_nop_xceiv_register();
1a4f4637 656
e8e51d29
AKG		 657 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
658 /* enable EHCI VBUS using GPIO22 */
bc593f5d 659 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 660 /* Select EHCI port on main board */
bc593f5d
IG		 661 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
662 OMAP_PIN_INPUT_PULLUP);
663 gpio_request_array(omap3_evm_ehci_gpios,
664 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 665
666 /* setup EHCI phy reset config */
4896e394 667 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 668 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 669
58815fa3
AKG		 670 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
671 musb_board_data.power = 500;
672 musb_board_data.extvbus = 1;
e8e51d29
AKG		 673 } else {
674 /* setup EHCI phy reset on MDC */
4896e394 675 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 676 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 677 }
884b8369 678 usb_musb_init(&musb_board_data);
9e64bb1e 679 usbhs_init(&usbhs_bdata);
96974a24 680 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 681 omap3evm_init_smsc911x();
703e3061 682 omap3_evm_display_init();
70d669de 683 omap3_evm_wl12xx_init();
53c5ec31
SMK		 684}
685
53c5ec31
SMK		 686MACHINE_START(OMAP3EVM, "OMAP3 EVM")
687 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 688 .atag_offset = 0x100,
71ee7dad 689 .reserve = omap_reserve,
3dc3bad6 690 .map_io = omap3_map_io,
8f5b5a41 691 .init_early = omap35xx_init_early,
741e3a89 692 .init_irq = omap3_init_irq,
6b2f55d7 693 .handle_irq = omap3_intc_handle_irq,
53c5ec31 694 .init_machine = omap3_evm_init,
e74984e4 695 .timer = &omap3_timer,
baa95883 696 .restart = omap_prcm_restart,
53c5ec31 697MACHINE_END
Linux kernel - Deliverables
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