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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jesse/openvswitch
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31 26
dc42c8bd
ZC		 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
53c5ec31
SMK		 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
ebeb53e1 33#include <linux/i2c/twl.h>
e8e2ff46 34#include <linux/usb/otg.h>
562138a4 35#include <linux/smsc911x.h>
53c5ec31 36
741927f7
ER		 37#include <linux/wl12xx.h>
38#include <linux/regulator/fixed.h>
1a7ec135 39#include <linux/regulator/machine.h>
3a63833e 40#include <linux/mmc/host.h>
dc28094b 41#include <linux/export.h>
1a7ec135 42
53c5ec31
SMK		 43#include <mach/hardware.h>
44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47
ce491cf8 48#include <plat/board.h>
ce491cf8 49#include <plat/usb.h>
dc42c8bd 50#include <plat/nand.h>
4e65331c 51#include "common.h"
ce491cf8 52#include <plat/mcspi.h>
a0b38cc4 53#include <video/omapdss.h>
dac8eb5f 54#include <video/omap-panel-tfp410.h>
53c5ec31 55
ca5742bd 56#include "mux.h"
53c5ec31 57#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 58#include "hsmmc.h"
96974a24 59#include "common-board-devices.h"
53c5ec31 60
c31cc1b7 61#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 62#define OMAP3_EVM_EHCI_VBUS 22
63#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 64
65#define OMAP3EVM_ETHR_START 0x2c000000
66#define OMAP3EVM_ETHR_SIZE 1024
db408023 67#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 68#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 69#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 70/*
71 * Eth Reset signal
72 * 64 = Generation 1 (<=RevD)
73 * 7 = Generation 2 (>=RevE)
74 */
75#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
76#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 77
db408023
AKG		 78static u8 omap3_evm_version;
79
80u8 get_omap3_evm_rev(void)
81{
82 return omap3_evm_version;
83}
84EXPORT_SYMBOL(get_omap3_evm_rev);
85
86static void __init omap3_evm_get_revision(void)
87{
88 void __iomem *ioaddr;
89 unsigned int smsc_id;
90
91 /* Ethernet PHY ID is stored at ID_REV register */
92 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
93 if (!ioaddr)
94 return;
95 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
96 iounmap(ioaddr);
97
98 switch (smsc_id) {
99 /*SMSC9115 chipset*/
100 case 0x01150000:
101 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
102 break;
103 /*SMSC 9220 chipset*/
104 case 0x92200000:
105 default:
106 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
107 }
108}
109
562138a4 110#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
21b42731 111#include <plat/gpmc-smsc911x.h>
53c5ec31 112
21b42731
MR		 113static struct omap_smsc911x_platform_data smsc911x_cfg = {
114 .cs = OMAP3EVM_SMSC911X_CS,
115 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
116 .gpio_reset = -EINVAL,
117 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 118};
119
562138a4 120static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 121{
9bc64b89
VH		 122 /* Configure ethernet controller reset gpio */
123 if (cpu_is_omap3430()) {
21b42731
MR		 124 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
125 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
126 else
127 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 128 }
129
21b42731 130 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 131}
132
562138a4
S		 133#else
134static inline void __init omap3evm_init_smsc911x(void) { return; }
135#endif
136
703e3061
VH		 137/*
138 * OMAP3EVM LCD Panel control signals
139 */
140#define OMAP3EVM_LCD_PANEL_LR 2
141#define OMAP3EVM_LCD_PANEL_UD 3
142#define OMAP3EVM_LCD_PANEL_INI 152
143#define OMAP3EVM_LCD_PANEL_ENVDD 153
144#define OMAP3EVM_LCD_PANEL_QVGA 154
145#define OMAP3EVM_LCD_PANEL_RESB 155
146#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
147#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
148
bc593f5d
IG		 149static struct gpio omap3_evm_dss_gpios[] __initdata = {
150 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
151 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
152 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
153 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
154 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
155 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
156};
157
703e3061
VH		 158static int lcd_enabled;
159static int dvi_enabled;
160
161static void __init omap3_evm_display_init(void)
162{
163 int r;
164
bc593f5d
IG		 165 r = gpio_request_array(omap3_evm_dss_gpios,
166 ARRAY_SIZE(omap3_evm_dss_gpios));
167 if (r)
168 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 169}
170
171static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
172{
173 if (dvi_enabled) {
174 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
175 return -EINVAL;
176 }
177 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
178
179 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 180 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 181 else
f186e9b2 182 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 183
184 lcd_enabled = 1;
185 return 0;
186}
187
188static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
189{
190 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
191
192 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 193 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 194 else
f186e9b2 195 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 196
197 lcd_enabled = 0;
198}
199
200static struct omap_dss_device omap3_evm_lcd_device = {
201 .name = "lcd",
202 .driver_name = "sharp_ls_panel",
203 .type = OMAP_DISPLAY_TYPE_DPI,
204 .phy.dpi.data_lines = 18,
205 .platform_enable = omap3_evm_enable_lcd,
206 .platform_disable = omap3_evm_disable_lcd,
207};
208
209static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
210{
211 return 0;
212}
213
214static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
215{
216}
217
218static struct omap_dss_device omap3_evm_tv_device = {
219 .name = "tv",
220 .driver_name = "venc",
221 .type = OMAP_DISPLAY_TYPE_VENC,
222 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
223 .platform_enable = omap3_evm_enable_tv,
224 .platform_disable = omap3_evm_disable_tv,
225};
226
2e6f2ee7 227static struct tfp410_platform_data dvi_panel = {
e813a55e 228 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
89747c91
BW		 229};
230
703e3061
VH		 231static struct omap_dss_device omap3_evm_dvi_device = {
232 .name = "dvi",
703e3061 233 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 234 .driver_name = "tfp410",
89747c91 235 .data = &dvi_panel,
703e3061 236 .phy.dpi.data_lines = 24,
703e3061
VH		 237};
238
239static struct omap_dss_device *omap3_evm_dss_devices[] = {
240 &omap3_evm_lcd_device,
241 &omap3_evm_tv_device,
242 &omap3_evm_dvi_device,
243};
244
245static struct omap_dss_board_info omap3_evm_dss_data = {
246 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
247 .devices = omap3_evm_dss_devices,
248 .default_device = &omap3_evm_lcd_device,
249};
250
786b01a8
OD		 251static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
252 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 253};
254
786b01a8
OD		 255static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
256 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 257};
258
259/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
260static struct regulator_init_data omap3evm_vmmc1 = {
261 .constraints = {
262 .min_uV = 1850000,
263 .max_uV = 3150000,
264 .valid_modes_mask = REGULATOR_MODE_NORMAL
265 | REGULATOR_MODE_STANDBY,
266 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
267 | REGULATOR_CHANGE_MODE
268 | REGULATOR_CHANGE_STATUS,
269 },
786b01a8
OD		 270 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
271 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 272};
273
274/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
275static struct regulator_init_data omap3evm_vsim = {
276 .constraints = {
277 .min_uV = 1800000,
278 .max_uV = 3000000,
279 .valid_modes_mask = REGULATOR_MODE_NORMAL
280 | REGULATOR_MODE_STANDBY,
281 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
282 | REGULATOR_CHANGE_MODE
283 | REGULATOR_CHANGE_STATUS,
284 },
786b01a8
OD		 285 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
286 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 287};
288
68ff0423 289static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 290 {
291 .mmc = 1,
3a63833e 292 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 293 .gpio_cd = -EINVAL,
294 .gpio_wp = 63,
3b972bf0 295 .deferred = true,
53c5ec31 296 },
741927f7
ER		 297#ifdef CONFIG_WL12XX_PLATFORM_DATA
298 {
299 .name = "wl1271",
aca6ad07 300 .mmc = 2,
741927f7
ER		 301 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
302 .gpio_wp = -EINVAL,
303 .gpio_cd = -EINVAL,
304 .nonremovable = true,
305 },
306#endif
53c5ec31
SMK		 307 {} /* Terminator */
308};
309
310static struct gpio_led gpio_leds[] = {
311 {
312 .name = "omap3evm::ledb",
313 /* normally not visible (board underside) */
314 .default_trigger = "default-on",
315 .gpio = -EINVAL, /* gets replaced */
316 .active_low = true,
317 },
318};
319
320static struct gpio_led_platform_data gpio_led_info = {
321 .leds = gpio_leds,
322 .num_leds = ARRAY_SIZE(gpio_leds),
323};
324
325static struct platform_device leds_gpio = {
326 .name = "leds-gpio",
327 .id = -1,
328 .dev = {
329 .platform_data = &gpio_led_info,
330 },
331};
332
333
334static int omap3evm_twl_gpio_setup(struct device *dev,
335 unsigned gpio, unsigned ngpio)
336{
bc593f5d 337 int r, lcd_bl_en;
42fc8cab 338
53c5ec31 339 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 340 mmc[0].gpio_cd = gpio + 0;
3b972bf0 341 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 342
343 /*
344 * Most GPIOs are for USB OTG. Some are mostly sent to
345 * the P2 connector; notably LEDA for the LCD backlight.
346 */
347
703e3061 348 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 349 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
350 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
351 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 352 if (r)
353 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 354
355 /* gpio + 7 == DVI Enable */
bc593f5d 356 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 357
53c5ec31 358 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 359 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 360
361 platform_device_register(&leds_gpio);
362
cb8ca589
ZC		 363 /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
364 * for starting USB tranceiver
365 */
b103a2e2 366#ifdef CONFIG_TWL4030_CORE
cb8ca589
ZC		 367 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
368 u8 val;
369
370 twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
371 val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
372 twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
373 }
b103a2e2 374#endif
cb8ca589 375
53c5ec31
SMK		 376 return 0;
377}
378
379static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
380 .gpio_base = OMAP_MAX_GPIO_LINES,
381 .irq_base = TWL4030_GPIO_IRQ_BASE,
382 .irq_end = TWL4030_GPIO_IRQ_END,
383 .use_leds = true,
384 .setup = omap3evm_twl_gpio_setup,
385};
386
bead4375 387static uint32_t board_keymap[] = {
53c5ec31 388 KEY(0, 0, KEY_LEFT),
0621d756
SP		 389 KEY(0, 1, KEY_DOWN),
390 KEY(0, 2, KEY_ENTER),
391 KEY(0, 3, KEY_M),
392
393 KEY(1, 0, KEY_RIGHT),
53c5ec31 394 KEY(1, 1, KEY_UP),
0621d756
SP		 395 KEY(1, 2, KEY_I),
396 KEY(1, 3, KEY_N),
397
398 KEY(2, 0, KEY_A),
399 KEY(2, 1, KEY_E),
53c5ec31 400 KEY(2, 2, KEY_J),
0621d756
SP		 401 KEY(2, 3, KEY_O),
402
403 KEY(3, 0, KEY_B),
404 KEY(3, 1, KEY_F),
405 KEY(3, 2, KEY_K),
53c5ec31
SMK		 406 KEY(3, 3, KEY_P)
407};
408
4f543332
TL		 409static struct matrix_keymap_data board_map_data = {
410 .keymap = board_keymap,
411 .keymap_size = ARRAY_SIZE(board_keymap),
412};
413
53c5ec31 414static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 415 .keymap_data = &board_map_data,
53c5ec31
SMK		 416 .rows = 4,
417 .cols = 4,
53c5ec31
SMK		 418 .rep = 1,
419};
420
410491d4 421/* ads7846 on SPI */
786b01a8
OD		 422static struct regulator_consumer_supply omap3evm_vio_supply[] = {
423 REGULATOR_SUPPLY("vcc", "spi1.0"),
424};
410491d4
VH		 425
426/* VIO for ads7846 */
427static struct regulator_init_data omap3evm_vio = {
428 .constraints = {
429 .min_uV = 1800000,
430 .max_uV = 1800000,
431 .apply_uV = true,
432 .valid_modes_mask = REGULATOR_MODE_NORMAL
433 | REGULATOR_MODE_STANDBY,
434 .valid_ops_mask = REGULATOR_CHANGE_MODE
435 | REGULATOR_CHANGE_STATUS,
436 },
786b01a8
OD		 437 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
438 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 439};
440
741927f7
ER		 441#ifdef CONFIG_WL12XX_PLATFORM_DATA
442
443#define OMAP3EVM_WLAN_PMENA_GPIO (150)
444#define OMAP3EVM_WLAN_IRQ_GPIO (149)
445
786b01a8 446static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 447 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 448};
741927f7
ER		 449
450/* VMMC2 for driving the WL12xx module */
451static struct regulator_init_data omap3evm_vmmc2 = {
452 .constraints = {
453 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
454 },
d19f579a 455 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 456 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 457};
458
459static struct fixed_voltage_config omap3evm_vwlan = {
460 .supply_name = "vwl1271",
461 .microvolts = 1800000, /* 1.80V */
462 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
463 .startup_delay = 70000, /* 70ms */
464 .enable_high = 1,
465 .enabled_at_boot = 0,
466 .init_data = &omap3evm_vmmc2,
467};
468
aca6ad07 469static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 470 .name = "reg-fixed-voltage",
471 .id = 1,
472 .dev = {
473 .platform_data = &omap3evm_vwlan,
474 },
475};
476
477struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 478 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 479};
480#endif
481
497af1f3
ZC		 482/* VAUX2 for USB */
483static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
484 REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
485 REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
486 REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
487 REGULATOR_SUPPLY("vaux2", NULL),
488};
489
490static struct regulator_init_data omap3evm_vaux2 = {
491 .constraints = {
492 .min_uV = 2800000,
493 .max_uV = 2800000,
494 .apply_uV = true,
495 .valid_modes_mask = REGULATOR_MODE_NORMAL
496 | REGULATOR_MODE_STANDBY,
497 .valid_ops_mask = REGULATOR_CHANGE_MODE
498 | REGULATOR_CHANGE_STATUS,
499 },
500 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies),
501 .consumer_supplies = omap3evm_vaux2_supplies,
502};
503
53c5ec31 504static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 505 /* platform_data for children goes here */
506 .keypad = &omap3evm_kp_data,
53c5ec31 507 .gpio = &omap3evm_gpio_data,
410491d4 508 .vio = &omap3evm_vio,
fbd8071c
MR		 509 .vmmc1 = &omap3evm_vmmc1,
510 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 511};
512
513static int __init omap3_evm_i2c_init(void)
514{
827ed9ae 515 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 516 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
517 TWL_COMMON_PDATA_AUDIO,
518 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
519
520 omap3evm_twldata.vdac->constraints.apply_uV = true;
521 omap3evm_twldata.vpll2->constraints.apply_uV = true;
522
fbd8071c 523 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 524 omap_register_i2c_bus(2, 400, NULL, 0);
525 omap_register_i2c_bus(3, 400, NULL, 0);
526 return 0;
527}
528
b3c6df3a 529static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
b3c6df3a
PW		 530};
531
181b250c 532static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 533
181b250c
KM		 534 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
535 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
536 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 537
538 .phy_reset = true,
e8e51d29 539 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 540 .reset_gpio_port[0] = -EINVAL,
e8e51d29 541 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 542 .reset_gpio_port[2] = -EINVAL
543};
544
ca5742bd 545#ifdef CONFIG_OMAP_MUX
904c545c 546static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 547 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 548 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 549 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 550 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 551 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
552 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 553 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
554 OMAP_PIN_OFF_NONE),
555 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
556 OMAP_PIN_OFF_NONE),
741927f7
ER		 557#ifdef CONFIG_WL12XX_PLATFORM_DATA
558 /* WLAN IRQ - GPIO 149 */
aca6ad07 559 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 560
561 /* WLAN POWER ENABLE - GPIO 150 */
562 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
563
564 /* MMC2 SDIO pin muxes for WL12xx */
565 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
566 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
567 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
568 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
569 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
570 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
571#endif
ca5742bd
TL		 572 { .reg_offset = OMAP_MUX_TERMINATOR },
573};
904c545c
VH		 574
575static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 576 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 577 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 578 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 579 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 580 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
581 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 582 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
583 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
584 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
585 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
586 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
587 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
588 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
589 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
590 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
591 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
592 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
593 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
594 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 595#ifdef CONFIG_WL12XX_PLATFORM_DATA
596 /* WLAN IRQ - GPIO 149 */
597 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
598
599 /* WLAN POWER ENABLE - GPIO 150 */
600 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
601
602 /* MMC2 SDIO pin muxes for WL12xx */
603 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
604 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
605 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
606 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
607 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
608 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
609#endif
904c545c 610
ca5742bd
TL		 611 { .reg_offset = OMAP_MUX_TERMINATOR },
612};
904c545c
VH		 613#else
614#define omap35x_board_mux NULL
615#define omap36x_board_mux NULL
ca5742bd
TL		 616#endif
617
884b8369
MM		 618static struct omap_musb_board_data musb_board_data = {
619 .interface_type = MUSB_INTERFACE_ULPI,
620 .mode = MUSB_OTG,
621 .power = 100,
622};
623
bc593f5d
IG		 624static struct gpio omap3_evm_ehci_gpios[] __initdata = {
625 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
626 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
627};
628
70d669de
RK		 629static void __init omap3_evm_wl12xx_init(void)
630{
631#ifdef CONFIG_WL12XX_PLATFORM_DATA
632 int ret;
633
634 /* WL12xx WLAN Init */
46a0a540 635 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 636 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
637 if (ret)
638 pr_err("error setting wl12xx data: %d\n", ret);
639 ret = platform_device_register(&omap3evm_wlan_regulator);
640 if (ret)
641 pr_err("error registering wl12xx device: %d\n", ret);
642#endif
643}
644
5b3689f4
RD		 645static struct regulator_consumer_supply dummy_supplies[] = {
646 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
647 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
648};
649
dc42c8bd
ZC		 650static struct mtd_partition omap3evm_nand_partitions[] = {
651 /* All the partition sizes are listed in terms of NAND block size */
652 {
653 .name = "X-Loader",
654 .offset = 0,
655 .size = 4*(SZ_128K),
656 .mask_flags = MTD_WRITEABLE
657 },
658 {
659 .name = "U-Boot",
660 .offset = MTDPART_OFS_APPEND,
661 .size = 14*(SZ_128K),
662 .mask_flags = MTD_WRITEABLE
663 },
664 {
665 .name = "U-Boot Env",
666 .offset = MTDPART_OFS_APPEND,
667 .size = 2*(SZ_128K)
668 },
669 {
670 .name = "Kernel",
671 .offset = MTDPART_OFS_APPEND,
672 .size = 40*(SZ_128K)
673 },
674 {
675 .name = "File system",
676 .size = MTDPART_SIZ_FULL,
677 .offset = MTDPART_OFS_APPEND,
678 },
679};
680
53c5ec31
SMK		 681static void __init omap3_evm_init(void)
682{
eeb3711b
PW		 683 struct omap_board_mux *obm;
684
db408023 685 omap3_evm_get_revision();
5b3689f4 686 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c 687
eeb3711b
PW		 688 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
689 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
db408023 690
e41cccfe
TL		 691 omap_board_config = omap3_evm_config;
692 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
db408023 693
d1589f09 694 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 695 omap_hsmmc_init(mmc);
d1589f09 696
497af1f3
ZC		 697 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
698 omap3evm_twldata.vaux2 = &omap3evm_vaux2;
699
53c5ec31
SMK		 700 omap3_evm_i2c_init();
701
d5e13227 702 omap_display_init(&omap3_evm_dss_data);
53c5ec31 703
53c5ec31 704 omap_serial_init();
a4ca9dbe 705 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 706
e8e2ff46
GAK		 707 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
708 usb_nop_xceiv_register();
1a4f4637 709
e8e51d29
AKG		 710 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
711 /* enable EHCI VBUS using GPIO22 */
bc593f5d 712 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 713 /* Select EHCI port on main board */
bc593f5d
IG		 714 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
715 OMAP_PIN_INPUT_PULLUP);
716 gpio_request_array(omap3_evm_ehci_gpios,
717 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 718
719 /* setup EHCI phy reset config */
4896e394 720 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 721 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 722
58815fa3
AKG		 723 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
724 musb_board_data.power = 500;
725 musb_board_data.extvbus = 1;
e8e51d29
AKG		 726 } else {
727 /* setup EHCI phy reset on MDC */
4896e394 728 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 729 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 730 }
884b8369 731 usb_musb_init(&musb_board_data);
9e64bb1e 732 usbhs_init(&usbhs_bdata);
dc42c8bd
ZC		 733 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
734 ARRAY_SIZE(omap3evm_nand_partitions));
735
96974a24 736 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 737 omap3evm_init_smsc911x();
703e3061 738 omap3_evm_display_init();
70d669de 739 omap3_evm_wl12xx_init();
53c5ec31
SMK		 740}
741
53c5ec31
SMK		 742MACHINE_START(OMAP3EVM, "OMAP3 EVM")
743 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 744 .atag_offset = 0x100,
71ee7dad 745 .reserve = omap_reserve,
3dc3bad6 746 .map_io = omap3_map_io,
8f5b5a41 747 .init_early = omap35xx_init_early,
741e3a89 748 .init_irq = omap3_init_irq,
6b2f55d7 749 .handle_irq = omap3_intc_handle_irq,
53c5ec31 750 .init_machine = omap3_evm_init,
bbd707ac 751 .init_late = omap35xx_init_late,
e74984e4 752 .timer = &omap3_timer,
baa95883 753 .restart = omap_prcm_restart,
53c5ec31 754MACHINE_END
Linux kernel - Deliverables
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