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omap: musb: introduce default board config
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31
SMK		 26
27#include <linux/spi/spi.h>
28#include <linux/spi/ads7846.h>
ebeb53e1 29#include <linux/i2c/twl.h>
e8e2ff46 30#include <linux/usb/otg.h>
562138a4 31#include <linux/smsc911x.h>
53c5ec31 32
741927f7
ER		 33#include <linux/wl12xx.h>
34#include <linux/regulator/fixed.h>
1a7ec135 35#include <linux/regulator/machine.h>
3a63833e 36#include <linux/mmc/host.h>
1a7ec135 37
53c5ec31
SMK		 38#include <mach/hardware.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42
ce491cf8 43#include <plat/board.h>
ce491cf8
TL		 44#include <plat/usb.h>
45#include <plat/common.h>
46#include <plat/mcspi.h>
703e3061 47#include <plat/display.h>
89747c91 48#include <plat/panel-generic-dpi.h>
53c5ec31 49
ca5742bd 50#include "mux.h"
53c5ec31 51#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 52#include "hsmmc.h"
96974a24 53#include "common-board-devices.h"
53c5ec31
SMK		 54
55#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 56#define OMAP3_EVM_EHCI_VBUS 22
57#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 58
59#define OMAP3EVM_ETHR_START 0x2c000000
60#define OMAP3EVM_ETHR_SIZE 1024
db408023 61#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 62#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 63#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 64/*
65 * Eth Reset signal
66 * 64 = Generation 1 (<=RevD)
67 * 7 = Generation 2 (>=RevE)
68 */
69#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
70#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 71
db408023
AKG		 72static u8 omap3_evm_version;
73
74u8 get_omap3_evm_rev(void)
75{
76 return omap3_evm_version;
77}
78EXPORT_SYMBOL(get_omap3_evm_rev);
79
80static void __init omap3_evm_get_revision(void)
81{
82 void __iomem *ioaddr;
83 unsigned int smsc_id;
84
85 /* Ethernet PHY ID is stored at ID_REV register */
86 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
87 if (!ioaddr)
88 return;
89 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
90 iounmap(ioaddr);
91
92 switch (smsc_id) {
93 /*SMSC9115 chipset*/
94 case 0x01150000:
95 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
96 break;
97 /*SMSC 9220 chipset*/
98 case 0x92200000:
99 default:
100 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
101 }
102}
103
562138a4 104#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
21b42731 105#include <plat/gpmc-smsc911x.h>
562138a4 106
21b42731
MR		 107static struct omap_smsc911x_platform_data smsc911x_cfg = {
108 .cs = OMAP3EVM_SMSC911X_CS,
109 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
110 .gpio_reset = -EINVAL,
111 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 112};
113
562138a4 114static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 115{
53c5ec31
SMK		 116 struct clk *l3ck;
117 unsigned int rate;
118
53c5ec31
SMK		 119 l3ck = clk_get(NULL, "l3_ck");
120 if (IS_ERR(l3ck))
121 rate = 100000000;
122 else
123 rate = clk_get_rate(l3ck);
124
9bc64b89
VH		 125 /* Configure ethernet controller reset gpio */
126 if (cpu_is_omap3430()) {
21b42731
MR		 127 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
128 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
129 else
130 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 131 }
132
21b42731 133 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 134}
135
562138a4
S		 136#else
137static inline void __init omap3evm_init_smsc911x(void) { return; }
138#endif
139
703e3061
VH		 140/*
141 * OMAP3EVM LCD Panel control signals
142 */
143#define OMAP3EVM_LCD_PANEL_LR 2
144#define OMAP3EVM_LCD_PANEL_UD 3
145#define OMAP3EVM_LCD_PANEL_INI 152
146#define OMAP3EVM_LCD_PANEL_ENVDD 153
147#define OMAP3EVM_LCD_PANEL_QVGA 154
148#define OMAP3EVM_LCD_PANEL_RESB 155
149#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
150#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
151
152static int lcd_enabled;
153static int dvi_enabled;
154
155static void __init omap3_evm_display_init(void)
156{
157 int r;
158
159 r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb");
160 if (r) {
161 printk(KERN_ERR "failed to get lcd_panel_resb\n");
162 return;
163 }
164 gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1);
165
166 r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini");
167 if (r) {
168 printk(KERN_ERR "failed to get lcd_panel_ini\n");
169 goto err_1;
170 }
171 gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1);
172
173 r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga");
174 if (r) {
175 printk(KERN_ERR "failed to get lcd_panel_qvga\n");
176 goto err_2;
177 }
178 gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0);
179
180 r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr");
181 if (r) {
182 printk(KERN_ERR "failed to get lcd_panel_lr\n");
183 goto err_3;
184 }
185 gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1);
186
187 r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud");
188 if (r) {
189 printk(KERN_ERR "failed to get lcd_panel_ud\n");
190 goto err_4;
191 }
192 gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1);
193
194 r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd");
195 if (r) {
196 printk(KERN_ERR "failed to get lcd_panel_envdd\n");
197 goto err_5;
198 }
199 gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0);
200
201 return;
202
203err_5:
204 gpio_free(OMAP3EVM_LCD_PANEL_UD);
205err_4:
206 gpio_free(OMAP3EVM_LCD_PANEL_LR);
207err_3:
208 gpio_free(OMAP3EVM_LCD_PANEL_QVGA);
209err_2:
210 gpio_free(OMAP3EVM_LCD_PANEL_INI);
211err_1:
212 gpio_free(OMAP3EVM_LCD_PANEL_RESB);
213
214}
215
216static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
217{
218 if (dvi_enabled) {
219 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
220 return -EINVAL;
221 }
222 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
223
224 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 225 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 226 else
f186e9b2 227 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 228
229 lcd_enabled = 1;
230 return 0;
231}
232
233static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
234{
235 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
236
237 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 238 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 239 else
f186e9b2 240 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 241
242 lcd_enabled = 0;
243}
244
245static struct omap_dss_device omap3_evm_lcd_device = {
246 .name = "lcd",
247 .driver_name = "sharp_ls_panel",
248 .type = OMAP_DISPLAY_TYPE_DPI,
249 .phy.dpi.data_lines = 18,
250 .platform_enable = omap3_evm_enable_lcd,
251 .platform_disable = omap3_evm_disable_lcd,
252};
253
254static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
255{
256 return 0;
257}
258
259static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
260{
261}
262
263static struct omap_dss_device omap3_evm_tv_device = {
264 .name = "tv",
265 .driver_name = "venc",
266 .type = OMAP_DISPLAY_TYPE_VENC,
267 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
268 .platform_enable = omap3_evm_enable_tv,
269 .platform_disable = omap3_evm_disable_tv,
270};
271
272static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
273{
274 if (lcd_enabled) {
275 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
276 return -EINVAL;
277 }
278
f186e9b2 279 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
703e3061
VH		 280
281 dvi_enabled = 1;
282 return 0;
283}
284
285static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
286{
f186e9b2 287 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
703e3061
VH		 288
289 dvi_enabled = 0;
290}
291
89747c91
BW		 292static struct panel_generic_dpi_data dvi_panel = {
293 .name = "generic",
294 .platform_enable = omap3_evm_enable_dvi,
295 .platform_disable = omap3_evm_disable_dvi,
296};
297
703e3061
VH		 298static struct omap_dss_device omap3_evm_dvi_device = {
299 .name = "dvi",
703e3061 300 .type = OMAP_DISPLAY_TYPE_DPI,
89747c91
BW		 301 .driver_name = "generic_dpi_panel",
302 .data = &dvi_panel,
703e3061 303 .phy.dpi.data_lines = 24,
703e3061
VH		 304};
305
306static struct omap_dss_device *omap3_evm_dss_devices[] = {
307 &omap3_evm_lcd_device,
308 &omap3_evm_tv_device,
309 &omap3_evm_dvi_device,
310};
311
312static struct omap_dss_board_info omap3_evm_dss_data = {
313 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
314 .devices = omap3_evm_dss_devices,
315 .default_device = &omap3_evm_lcd_device,
316};
317
1a7ec135
MR		 318static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
319 .supply = "vmmc",
320};
321
322static struct regulator_consumer_supply omap3evm_vsim_supply = {
323 .supply = "vmmc_aux",
324};
325
326/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
327static struct regulator_init_data omap3evm_vmmc1 = {
328 .constraints = {
329 .min_uV = 1850000,
330 .max_uV = 3150000,
331 .valid_modes_mask = REGULATOR_MODE_NORMAL
332 | REGULATOR_MODE_STANDBY,
333 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
334 | REGULATOR_CHANGE_MODE
335 | REGULATOR_CHANGE_STATUS,
336 },
337 .num_consumer_supplies = 1,
338 .consumer_supplies = &omap3evm_vmmc1_supply,
339};
340
341/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
342static struct regulator_init_data omap3evm_vsim = {
343 .constraints = {
344 .min_uV = 1800000,
345 .max_uV = 3000000,
346 .valid_modes_mask = REGULATOR_MODE_NORMAL
347 | REGULATOR_MODE_STANDBY,
348 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
349 | REGULATOR_CHANGE_MODE
350 | REGULATOR_CHANGE_STATUS,
351 },
352 .num_consumer_supplies = 1,
353 .consumer_supplies = &omap3evm_vsim_supply,
354};
355
68ff0423 356static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 357 {
358 .mmc = 1,
3a63833e 359 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 360 .gpio_cd = -EINVAL,
361 .gpio_wp = 63,
362 },
741927f7
ER		 363#ifdef CONFIG_WL12XX_PLATFORM_DATA
364 {
365 .name = "wl1271",
aca6ad07 366 .mmc = 2,
741927f7
ER		 367 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
368 .gpio_wp = -EINVAL,
369 .gpio_cd = -EINVAL,
370 .nonremovable = true,
371 },
372#endif
53c5ec31
SMK		 373 {} /* Terminator */
374};
375
376static struct gpio_led gpio_leds[] = {
377 {
378 .name = "omap3evm::ledb",
379 /* normally not visible (board underside) */
380 .default_trigger = "default-on",
381 .gpio = -EINVAL, /* gets replaced */
382 .active_low = true,
383 },
384};
385
386static struct gpio_led_platform_data gpio_led_info = {
387 .leds = gpio_leds,
388 .num_leds = ARRAY_SIZE(gpio_leds),
389};
390
391static struct platform_device leds_gpio = {
392 .name = "leds-gpio",
393 .id = -1,
394 .dev = {
395 .platform_data = &gpio_led_info,
396 },
397};
398
399
400static int omap3evm_twl_gpio_setup(struct device *dev,
401 unsigned gpio, unsigned ngpio)
402{
42fc8cab
VH		 403 int r;
404
53c5ec31 405 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
4896e394 406 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
53c5ec31 407 mmc[0].gpio_cd = gpio + 0;
68ff0423 408 omap2_hsmmc_init(mmc);
53c5ec31 409
1a7ec135
MR		 410 /* link regulators to MMC adapters */
411 omap3evm_vmmc1_supply.dev = mmc[0].dev;
412 omap3evm_vsim_supply.dev = mmc[0].dev;
413
53c5ec31
SMK		 414 /*
415 * Most GPIOs are for USB OTG. Some are mostly sent to
416 * the P2 connector; notably LEDA for the LCD backlight.
417 */
418
703e3061 419 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
42fc8cab
VH		 420 r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
421 if (!r)
422 r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
423 (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
424 if (r)
425 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 426
427 /* gpio + 7 == DVI Enable */
428 gpio_request(gpio + 7, "EN_DVI");
429 gpio_direction_output(gpio + 7, 0);
430
53c5ec31
SMK		 431 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
432 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
433
434 platform_device_register(&leds_gpio);
435
436 return 0;
437}
438
439static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
440 .gpio_base = OMAP_MAX_GPIO_LINES,
441 .irq_base = TWL4030_GPIO_IRQ_BASE,
442 .irq_end = TWL4030_GPIO_IRQ_END,
443 .use_leds = true,
444 .setup = omap3evm_twl_gpio_setup,
445};
446
447static struct twl4030_usb_data omap3evm_usb_data = {
448 .usb_mode = T2_USB_MODE_ULPI,
449};
450
bead4375 451static uint32_t board_keymap[] = {
53c5ec31 452 KEY(0, 0, KEY_LEFT),
0621d756
SP		 453 KEY(0, 1, KEY_DOWN),
454 KEY(0, 2, KEY_ENTER),
455 KEY(0, 3, KEY_M),
456
457 KEY(1, 0, KEY_RIGHT),
53c5ec31 458 KEY(1, 1, KEY_UP),
0621d756
SP		 459 KEY(1, 2, KEY_I),
460 KEY(1, 3, KEY_N),
461
462 KEY(2, 0, KEY_A),
463 KEY(2, 1, KEY_E),
53c5ec31 464 KEY(2, 2, KEY_J),
0621d756
SP		 465 KEY(2, 3, KEY_O),
466
467 KEY(3, 0, KEY_B),
468 KEY(3, 1, KEY_F),
469 KEY(3, 2, KEY_K),
53c5ec31
SMK		 470 KEY(3, 3, KEY_P)
471};
472
4f543332
TL		 473static struct matrix_keymap_data board_map_data = {
474 .keymap = board_keymap,
475 .keymap_size = ARRAY_SIZE(board_keymap),
476};
477
53c5ec31 478static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 479 .keymap_data = &board_map_data,
53c5ec31
SMK		 480 .rows = 4,
481 .cols = 4,
53c5ec31
SMK		 482 .rep = 1,
483};
484
485static struct twl4030_madc_platform_data omap3evm_madc_data = {
486 .irq_line = 1,
487};
488
6a58baf8 489static struct twl4030_codec_audio_data omap3evm_audio_data;
e86fa0b4
PU		 490
491static struct twl4030_codec_data omap3evm_codec_data = {
6df74efb 492 .audio_mclk = 26000000,
e86fa0b4
PU		 493 .audio = &omap3evm_audio_data,
494};
495
1dde9732 496static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
30ea50c9 497 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
703e3061
VH		 498
499/* VDAC for DSS driving S-Video */
500static struct regulator_init_data omap3_evm_vdac = {
501 .constraints = {
502 .min_uV = 1800000,
503 .max_uV = 1800000,
504 .apply_uV = true,
505 .valid_modes_mask = REGULATOR_MODE_NORMAL
506 | REGULATOR_MODE_STANDBY,
507 .valid_ops_mask = REGULATOR_CHANGE_MODE
508 | REGULATOR_CHANGE_STATUS,
509 },
510 .num_consumer_supplies = 1,
511 .consumer_supplies = &omap3_evm_vdda_dac_supply,
512};
513
514/* VPLL2 for digital video outputs */
c8aac01b
SG		 515static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
516 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
517 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
518};
703e3061
VH		 519
520static struct regulator_init_data omap3_evm_vpll2 = {
521 .constraints = {
703e3061
VH		 522 .min_uV = 1800000,
523 .max_uV = 1800000,
524 .apply_uV = true,
525 .valid_modes_mask = REGULATOR_MODE_NORMAL
526 | REGULATOR_MODE_STANDBY,
527 .valid_ops_mask = REGULATOR_CHANGE_MODE
528 | REGULATOR_CHANGE_STATUS,
529 },
c8aac01b
SG		 530 .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
531 .consumer_supplies = omap3_evm_vpll2_supplies,
703e3061
VH		 532};
533
410491d4
VH		 534/* ads7846 on SPI */
535static struct regulator_consumer_supply omap3evm_vio_supply =
536 REGULATOR_SUPPLY("vcc", "spi1.0");
537
538/* VIO for ads7846 */
539static struct regulator_init_data omap3evm_vio = {
540 .constraints = {
541 .min_uV = 1800000,
542 .max_uV = 1800000,
543 .apply_uV = true,
544 .valid_modes_mask = REGULATOR_MODE_NORMAL
545 | REGULATOR_MODE_STANDBY,
546 .valid_ops_mask = REGULATOR_CHANGE_MODE
547 | REGULATOR_CHANGE_STATUS,
548 },
549 .num_consumer_supplies = 1,
550 .consumer_supplies = &omap3evm_vio_supply,
551};
552
741927f7
ER		 553#ifdef CONFIG_WL12XX_PLATFORM_DATA
554
555#define OMAP3EVM_WLAN_PMENA_GPIO (150)
556#define OMAP3EVM_WLAN_IRQ_GPIO (149)
557
aca6ad07 558static struct regulator_consumer_supply omap3evm_vmmc2_supply =
0005ae73 559 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
741927f7
ER		 560
561/* VMMC2 for driving the WL12xx module */
562static struct regulator_init_data omap3evm_vmmc2 = {
563 .constraints = {
564 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
565 },
566 .num_consumer_supplies = 1,
567 .consumer_supplies = &omap3evm_vmmc2_supply,
568};
569
570static struct fixed_voltage_config omap3evm_vwlan = {
571 .supply_name = "vwl1271",
572 .microvolts = 1800000, /* 1.80V */
573 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
574 .startup_delay = 70000, /* 70ms */
575 .enable_high = 1,
576 .enabled_at_boot = 0,
577 .init_data = &omap3evm_vmmc2,
578};
579
aca6ad07 580static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 581 .name = "reg-fixed-voltage",
582 .id = 1,
583 .dev = {
584 .platform_data = &omap3evm_vwlan,
585 },
586};
587
588struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
589 .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
aca6ad07 590 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 591};
592#endif
593
53c5ec31
SMK		 594static struct twl4030_platform_data omap3evm_twldata = {
595 .irq_base = TWL4030_IRQ_BASE,
596 .irq_end = TWL4030_IRQ_END,
597
598 /* platform_data for children goes here */
599 .keypad = &omap3evm_kp_data,
600 .madc = &omap3evm_madc_data,
601 .usb = &omap3evm_usb_data,
602 .gpio = &omap3evm_gpio_data,
e86fa0b4 603 .codec = &omap3evm_codec_data,
703e3061
VH		 604 .vdac = &omap3_evm_vdac,
605 .vpll2 = &omap3_evm_vpll2,
410491d4 606 .vio = &omap3evm_vio,
fbd8071c
MR		 607 .vmmc1 = &omap3evm_vmmc1,
608 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 609};
610
611static int __init omap3_evm_i2c_init(void)
612{
fbd8071c 613 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 614 omap_register_i2c_bus(2, 400, NULL, 0);
615 omap_register_i2c_bus(3, 400, NULL, 0);
616 return 0;
617}
618
b3c6df3a 619static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
b3c6df3a
PW		 620};
621
3dc3bad6 622static void __init omap3_evm_init_early(void)
53c5ec31 623{
4805734b
PW		 624 omap2_init_common_infrastructure();
625 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
53c5ec31
SMK		 626}
627
181b250c 628static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 629
181b250c
KM		 630 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
631 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
632 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 633
634 .phy_reset = true,
e8e51d29 635 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 636 .reset_gpio_port[0] = -EINVAL,
e8e51d29 637 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 638 .reset_gpio_port[2] = -EINVAL
639};
640
ca5742bd 641#ifdef CONFIG_OMAP_MUX
904c545c 642static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 643 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 644 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 645 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 646 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 647 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
648 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 649 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
650 OMAP_PIN_OFF_NONE),
651 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
652 OMAP_PIN_OFF_NONE),
741927f7
ER		 653#ifdef CONFIG_WL12XX_PLATFORM_DATA
654 /* WLAN IRQ - GPIO 149 */
aca6ad07 655 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 656
657 /* WLAN POWER ENABLE - GPIO 150 */
658 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
659
660 /* MMC2 SDIO pin muxes for WL12xx */
661 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
662 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
663 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
664 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
665 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
666 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
667#endif
ca5742bd
TL		 668 { .reg_offset = OMAP_MUX_TERMINATOR },
669};
904c545c
VH		 670
671static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 672 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 673 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 674 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 675 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 676 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
677 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 678 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
679 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
680 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
681 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
682 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
683 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
684 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
685 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
686 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
687 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
688 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
689 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
690 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 691#ifdef CONFIG_WL12XX_PLATFORM_DATA
692 /* WLAN IRQ - GPIO 149 */
693 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
694
695 /* WLAN POWER ENABLE - GPIO 150 */
696 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
697
698 /* MMC2 SDIO pin muxes for WL12xx */
699 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
700 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
701 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
702 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
703 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
704 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
705#endif
904c545c 706
ca5742bd
TL		 707 { .reg_offset = OMAP_MUX_TERMINATOR },
708};
904c545c
VH		 709#else
710#define omap35x_board_mux NULL
711#define omap36x_board_mux NULL
ca5742bd
TL		 712#endif
713
884b8369
MM		 714static struct omap_musb_board_data musb_board_data = {
715 .interface_type = MUSB_INTERFACE_ULPI,
716 .mode = MUSB_OTG,
717 .power = 100,
718};
719
53c5ec31
SMK		 720static void __init omap3_evm_init(void)
721{
db408023 722 omap3_evm_get_revision();
904c545c
VH		 723
724 if (cpu_is_omap3630())
725 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
726 else
727 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
db408023 728
e41cccfe
TL		 729 omap_board_config = omap3_evm_config;
730 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
db408023 731
53c5ec31
SMK		 732 omap3_evm_i2c_init();
733
d5e13227 734 omap_display_init(&omap3_evm_dss_data);
53c5ec31 735
53c5ec31 736 omap_serial_init();
1a4f4637 737
e8e2ff46
GAK		 738 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
739 usb_nop_xceiv_register();
1a4f4637 740
e8e51d29
AKG		 741 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
742 /* enable EHCI VBUS using GPIO22 */
4896e394 743 omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
e8e51d29
AKG		 744 gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
745 gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
746 gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
747
748 /* Select EHCI port on main board */
4896e394 749 omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
e8e51d29
AKG		 750 gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
751 gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
752 gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
753
754 /* setup EHCI phy reset config */
4896e394 755 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 756 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 757
58815fa3
AKG		 758 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
759 musb_board_data.power = 500;
760 musb_board_data.extvbus = 1;
e8e51d29
AKG		 761 } else {
762 /* setup EHCI phy reset on MDC */
4896e394 763 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 764 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 765 }
884b8369 766 usb_musb_init(&musb_board_data);
9e64bb1e 767 usbhs_init(&usbhs_bdata);
96974a24 768 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 769 omap3evm_init_smsc911x();
703e3061 770 omap3_evm_display_init();
741927f7
ER		 771
772#ifdef CONFIG_WL12XX_PLATFORM_DATA
773 /* WL12xx WLAN Init */
774 if (wl12xx_set_platform_data(&omap3evm_wlan_data))
775 pr_err("error setting wl12xx data\n");
aca6ad07 776 platform_device_register(&omap3evm_wlan_regulator);
741927f7 777#endif
53c5ec31
SMK		 778}
779
53c5ec31
SMK		 780MACHINE_START(OMAP3EVM, "OMAP3 EVM")
781 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
53c5ec31 782 .boot_params = 0x80000100,
71ee7dad 783 .reserve = omap_reserve,
3dc3bad6
RKAL		 784 .map_io = omap3_map_io,
785 .init_early = omap3_evm_init_early,
786 .init_irq = omap_init_irq,
53c5ec31
SMK		 787 .init_machine = omap3_evm_init,
788 .timer = &omap_timer,
789MACHINE_END
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