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ARM: OMAP3EVM: Add NAND flash definition
[deliverable/linux.git] / arch / arm / mach-omap2 / board-omap3evm.c
CommitLineData
53c5ec31
SMK		 1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
6135434a 23#include <linux/input/matrix_keypad.h>
53c5ec31 24#include <linux/leds.h>
562138a4 25#include <linux/interrupt.h>
53c5ec31 26
dc42c8bd
ZC		 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
53c5ec31
SMK		 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
ebeb53e1 33#include <linux/i2c/twl.h>
e8e2ff46 34#include <linux/usb/otg.h>
562138a4 35#include <linux/smsc911x.h>
53c5ec31 36
741927f7
ER		 37#include <linux/wl12xx.h>
38#include <linux/regulator/fixed.h>
1a7ec135 39#include <linux/regulator/machine.h>
3a63833e 40#include <linux/mmc/host.h>
dc28094b 41#include <linux/export.h>
1a7ec135 42
53c5ec31
SMK		 43#include <mach/hardware.h>
44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47
ce491cf8 48#include <plat/board.h>
ce491cf8 49#include <plat/usb.h>
dc42c8bd 50#include <plat/nand.h>
4e65331c 51#include "common.h"
ce491cf8 52#include <plat/mcspi.h>
a0b38cc4 53#include <video/omapdss.h>
dac8eb5f 54#include <video/omap-panel-tfp410.h>
53c5ec31 55
ca5742bd 56#include "mux.h"
53c5ec31 57#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 58#include "hsmmc.h"
96974a24 59#include "common-board-devices.h"
53c5ec31
SMK		 60
61#define OMAP3_EVM_TS_GPIO 175
e8e51d29
AKG		 62#define OMAP3_EVM_EHCI_VBUS 22
63#define OMAP3_EVM_EHCI_SELECT 61
53c5ec31
SMK		 64
65#define OMAP3EVM_ETHR_START 0x2c000000
66#define OMAP3EVM_ETHR_SIZE 1024
db408023 67#define OMAP3EVM_ETHR_ID_REV 0x50
53c5ec31 68#define OMAP3EVM_ETHR_GPIO_IRQ 176
562138a4 69#define OMAP3EVM_SMSC911X_CS 5
9bc64b89
VH		 70/*
71 * Eth Reset signal
72 * 64 = Generation 1 (<=RevD)
73 * 7 = Generation 2 (>=RevE)
74 */
75#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
76#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
53c5ec31 77
db408023
AKG		 78static u8 omap3_evm_version;
79
80u8 get_omap3_evm_rev(void)
81{
82 return omap3_evm_version;
83}
84EXPORT_SYMBOL(get_omap3_evm_rev);
85
86static void __init omap3_evm_get_revision(void)
87{
88 void __iomem *ioaddr;
89 unsigned int smsc_id;
90
91 /* Ethernet PHY ID is stored at ID_REV register */
92 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
93 if (!ioaddr)
94 return;
95 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
96 iounmap(ioaddr);
97
98 switch (smsc_id) {
99 /*SMSC9115 chipset*/
100 case 0x01150000:
101 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
102 break;
103 /*SMSC 9220 chipset*/
104 case 0x92200000:
105 default:
106 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
107 }
108}
109
562138a4 110#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
21b42731 111#include <plat/gpmc-smsc911x.h>
53c5ec31 112
21b42731
MR		 113static struct omap_smsc911x_platform_data smsc911x_cfg = {
114 .cs = OMAP3EVM_SMSC911X_CS,
115 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
116 .gpio_reset = -EINVAL,
117 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
53c5ec31
SMK		 118};
119
562138a4 120static inline void __init omap3evm_init_smsc911x(void)
53c5ec31 121{
9bc64b89
VH		 122 /* Configure ethernet controller reset gpio */
123 if (cpu_is_omap3430()) {
21b42731
MR		 124 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
125 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
126 else
127 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
53c5ec31
SMK		 128 }
129
21b42731 130 gpmc_smsc911x_init(&smsc911x_cfg);
53c5ec31
SMK		 131}
132
562138a4
S		 133#else
134static inline void __init omap3evm_init_smsc911x(void) { return; }
135#endif
136
703e3061
VH		 137/*
138 * OMAP3EVM LCD Panel control signals
139 */
140#define OMAP3EVM_LCD_PANEL_LR 2
141#define OMAP3EVM_LCD_PANEL_UD 3
142#define OMAP3EVM_LCD_PANEL_INI 152
143#define OMAP3EVM_LCD_PANEL_ENVDD 153
144#define OMAP3EVM_LCD_PANEL_QVGA 154
145#define OMAP3EVM_LCD_PANEL_RESB 155
146#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
147#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
148
bc593f5d
IG		 149static struct gpio omap3_evm_dss_gpios[] __initdata = {
150 { OMAP3EVM_LCD_PANEL_RESB, GPIOF_OUT_INIT_HIGH, "lcd_panel_resb" },
151 { OMAP3EVM_LCD_PANEL_INI, GPIOF_OUT_INIT_HIGH, "lcd_panel_ini" },
152 { OMAP3EVM_LCD_PANEL_QVGA, GPIOF_OUT_INIT_LOW, "lcd_panel_qvga" },
153 { OMAP3EVM_LCD_PANEL_LR, GPIOF_OUT_INIT_HIGH, "lcd_panel_lr" },
154 { OMAP3EVM_LCD_PANEL_UD, GPIOF_OUT_INIT_HIGH, "lcd_panel_ud" },
155 { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, "lcd_panel_envdd" },
156};
157
703e3061
VH		 158static int lcd_enabled;
159static int dvi_enabled;
160
161static void __init omap3_evm_display_init(void)
162{
163 int r;
164
bc593f5d
IG		 165 r = gpio_request_array(omap3_evm_dss_gpios,
166 ARRAY_SIZE(omap3_evm_dss_gpios));
167 if (r)
168 printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
703e3061
VH		 169}
170
171static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
172{
173 if (dvi_enabled) {
174 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
175 return -EINVAL;
176 }
177 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
178
179 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 180 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061 181 else
f186e9b2 182 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061
VH		 183
184 lcd_enabled = 1;
185 return 0;
186}
187
188static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
189{
190 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
191
192 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
f186e9b2 193 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
703e3061 194 else
f186e9b2 195 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
703e3061
VH		 196
197 lcd_enabled = 0;
198}
199
200static struct omap_dss_device omap3_evm_lcd_device = {
201 .name = "lcd",
202 .driver_name = "sharp_ls_panel",
203 .type = OMAP_DISPLAY_TYPE_DPI,
204 .phy.dpi.data_lines = 18,
205 .platform_enable = omap3_evm_enable_lcd,
206 .platform_disable = omap3_evm_disable_lcd,
207};
208
209static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
210{
211 return 0;
212}
213
214static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
215{
216}
217
218static struct omap_dss_device omap3_evm_tv_device = {
219 .name = "tv",
220 .driver_name = "venc",
221 .type = OMAP_DISPLAY_TYPE_VENC,
222 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
223 .platform_enable = omap3_evm_enable_tv,
224 .platform_disable = omap3_evm_disable_tv,
225};
226
2e6f2ee7 227static struct tfp410_platform_data dvi_panel = {
e813a55e 228 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
89747c91
BW		 229};
230
703e3061
VH		 231static struct omap_dss_device omap3_evm_dvi_device = {
232 .name = "dvi",
703e3061 233 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 234 .driver_name = "tfp410",
89747c91 235 .data = &dvi_panel,
703e3061 236 .phy.dpi.data_lines = 24,
703e3061
VH		 237};
238
239static struct omap_dss_device *omap3_evm_dss_devices[] = {
240 &omap3_evm_lcd_device,
241 &omap3_evm_tv_device,
242 &omap3_evm_dvi_device,
243};
244
245static struct omap_dss_board_info omap3_evm_dss_data = {
246 .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
247 .devices = omap3_evm_dss_devices,
248 .default_device = &omap3_evm_lcd_device,
249};
250
786b01a8
OD		 251static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
252 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
1a7ec135
MR		 253};
254
786b01a8
OD		 255static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
256 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
1a7ec135
MR		 257};
258
259/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
260static struct regulator_init_data omap3evm_vmmc1 = {
261 .constraints = {
262 .min_uV = 1850000,
263 .max_uV = 3150000,
264 .valid_modes_mask = REGULATOR_MODE_NORMAL
265 | REGULATOR_MODE_STANDBY,
266 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
267 | REGULATOR_CHANGE_MODE
268 | REGULATOR_CHANGE_STATUS,
269 },
786b01a8
OD		 270 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
271 .consumer_supplies = omap3evm_vmmc1_supply,
1a7ec135
MR		 272};
273
274/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
275static struct regulator_init_data omap3evm_vsim = {
276 .constraints = {
277 .min_uV = 1800000,
278 .max_uV = 3000000,
279 .valid_modes_mask = REGULATOR_MODE_NORMAL
280 | REGULATOR_MODE_STANDBY,
281 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
282 | REGULATOR_CHANGE_MODE
283 | REGULATOR_CHANGE_STATUS,
284 },
786b01a8
OD		 285 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
286 .consumer_supplies = omap3evm_vsim_supply,
1a7ec135
MR		 287};
288
68ff0423 289static struct omap2_hsmmc_info mmc[] = {
53c5ec31
SMK		 290 {
291 .mmc = 1,
3a63833e 292 .caps = MMC_CAP_4_BIT_DATA,
53c5ec31
SMK		 293 .gpio_cd = -EINVAL,
294 .gpio_wp = 63,
3b972bf0 295 .deferred = true,
53c5ec31 296 },
741927f7
ER		 297#ifdef CONFIG_WL12XX_PLATFORM_DATA
298 {
299 .name = "wl1271",
aca6ad07 300 .mmc = 2,
741927f7
ER		 301 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
302 .gpio_wp = -EINVAL,
303 .gpio_cd = -EINVAL,
304 .nonremovable = true,
305 },
306#endif
53c5ec31
SMK		 307 {} /* Terminator */
308};
309
310static struct gpio_led gpio_leds[] = {
311 {
312 .name = "omap3evm::ledb",
313 /* normally not visible (board underside) */
314 .default_trigger = "default-on",
315 .gpio = -EINVAL, /* gets replaced */
316 .active_low = true,
317 },
318};
319
320static struct gpio_led_platform_data gpio_led_info = {
321 .leds = gpio_leds,
322 .num_leds = ARRAY_SIZE(gpio_leds),
323};
324
325static struct platform_device leds_gpio = {
326 .name = "leds-gpio",
327 .id = -1,
328 .dev = {
329 .platform_data = &gpio_led_info,
330 },
331};
332
333
334static int omap3evm_twl_gpio_setup(struct device *dev,
335 unsigned gpio, unsigned ngpio)
336{
bc593f5d 337 int r, lcd_bl_en;
42fc8cab 338
53c5ec31 339 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
53c5ec31 340 mmc[0].gpio_cd = gpio + 0;
3b972bf0 341 omap_hsmmc_late_init(mmc);
53c5ec31
SMK		 342
343 /*
344 * Most GPIOs are for USB OTG. Some are mostly sent to
345 * the P2 connector; notably LEDA for the LCD backlight.
346 */
347
703e3061 348 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
bc593f5d
IG		 349 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
350 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
351 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
42fc8cab
VH		 352 if (r)
353 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
703e3061
VH		 354
355 /* gpio + 7 == DVI Enable */
bc593f5d 356 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
703e3061 357
53c5ec31 358 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
ebe8f7e5 359 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
53c5ec31
SMK		 360
361 platform_device_register(&leds_gpio);
362
363 return 0;
364}
365
366static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
367 .gpio_base = OMAP_MAX_GPIO_LINES,
368 .irq_base = TWL4030_GPIO_IRQ_BASE,
369 .irq_end = TWL4030_GPIO_IRQ_END,
370 .use_leds = true,
371 .setup = omap3evm_twl_gpio_setup,
372};
373
bead4375 374static uint32_t board_keymap[] = {
53c5ec31 375 KEY(0, 0, KEY_LEFT),
0621d756
SP		 376 KEY(0, 1, KEY_DOWN),
377 KEY(0, 2, KEY_ENTER),
378 KEY(0, 3, KEY_M),
379
380 KEY(1, 0, KEY_RIGHT),
53c5ec31 381 KEY(1, 1, KEY_UP),
0621d756
SP		 382 KEY(1, 2, KEY_I),
383 KEY(1, 3, KEY_N),
384
385 KEY(2, 0, KEY_A),
386 KEY(2, 1, KEY_E),
53c5ec31 387 KEY(2, 2, KEY_J),
0621d756
SP		 388 KEY(2, 3, KEY_O),
389
390 KEY(3, 0, KEY_B),
391 KEY(3, 1, KEY_F),
392 KEY(3, 2, KEY_K),
53c5ec31
SMK		 393 KEY(3, 3, KEY_P)
394};
395
4f543332
TL		 396static struct matrix_keymap_data board_map_data = {
397 .keymap = board_keymap,
398 .keymap_size = ARRAY_SIZE(board_keymap),
399};
400
53c5ec31 401static struct twl4030_keypad_data omap3evm_kp_data = {
4f543332 402 .keymap_data = &board_map_data,
53c5ec31
SMK		 403 .rows = 4,
404 .cols = 4,
53c5ec31
SMK		 405 .rep = 1,
406};
407
410491d4 408/* ads7846 on SPI */
786b01a8
OD		 409static struct regulator_consumer_supply omap3evm_vio_supply[] = {
410 REGULATOR_SUPPLY("vcc", "spi1.0"),
411};
410491d4
VH		 412
413/* VIO for ads7846 */
414static struct regulator_init_data omap3evm_vio = {
415 .constraints = {
416 .min_uV = 1800000,
417 .max_uV = 1800000,
418 .apply_uV = true,
419 .valid_modes_mask = REGULATOR_MODE_NORMAL
420 | REGULATOR_MODE_STANDBY,
421 .valid_ops_mask = REGULATOR_CHANGE_MODE
422 | REGULATOR_CHANGE_STATUS,
423 },
786b01a8
OD		 424 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
425 .consumer_supplies = omap3evm_vio_supply,
410491d4
VH		 426};
427
741927f7
ER		 428#ifdef CONFIG_WL12XX_PLATFORM_DATA
429
430#define OMAP3EVM_WLAN_PMENA_GPIO (150)
431#define OMAP3EVM_WLAN_IRQ_GPIO (149)
432
786b01a8 433static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
d19f579a 434 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
786b01a8 435};
741927f7
ER		 436
437/* VMMC2 for driving the WL12xx module */
438static struct regulator_init_data omap3evm_vmmc2 = {
439 .constraints = {
440 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
441 },
d19f579a 442 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
786b01a8 443 .consumer_supplies = omap3evm_vmmc2_supply,
741927f7
ER		 444};
445
446static struct fixed_voltage_config omap3evm_vwlan = {
447 .supply_name = "vwl1271",
448 .microvolts = 1800000, /* 1.80V */
449 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
450 .startup_delay = 70000, /* 70ms */
451 .enable_high = 1,
452 .enabled_at_boot = 0,
453 .init_data = &omap3evm_vmmc2,
454};
455
aca6ad07 456static struct platform_device omap3evm_wlan_regulator = {
741927f7
ER		 457 .name = "reg-fixed-voltage",
458 .id = 1,
459 .dev = {
460 .platform_data = &omap3evm_vwlan,
461 },
462};
463
464struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
aca6ad07 465 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
741927f7
ER		 466};
467#endif
468
53c5ec31 469static struct twl4030_platform_data omap3evm_twldata = {
53c5ec31
SMK		 470 /* platform_data for children goes here */
471 .keypad = &omap3evm_kp_data,
53c5ec31 472 .gpio = &omap3evm_gpio_data,
410491d4 473 .vio = &omap3evm_vio,
fbd8071c
MR		 474 .vmmc1 = &omap3evm_vmmc1,
475 .vsim = &omap3evm_vsim,
53c5ec31
SMK		 476};
477
478static int __init omap3_evm_i2c_init(void)
479{
827ed9ae 480 omap3_pmic_get_config(&omap3evm_twldata,
b252b0ef
PU		 481 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
482 TWL_COMMON_PDATA_AUDIO,
483 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
484
485 omap3evm_twldata.vdac->constraints.apply_uV = true;
486 omap3evm_twldata.vpll2->constraints.apply_uV = true;
487
fbd8071c 488 omap3_pmic_init("twl4030", &omap3evm_twldata);
53c5ec31
SMK		 489 omap_register_i2c_bus(2, 400, NULL, 0);
490 omap_register_i2c_bus(3, 400, NULL, 0);
491 return 0;
492}
493
b3c6df3a 494static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
b3c6df3a
PW		 495};
496
181b250c 497static struct usbhs_omap_board_data usbhs_bdata __initdata = {
58a5491c 498
181b250c
KM		 499 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
500 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
501 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
58a5491c
FB		 502
503 .phy_reset = true,
e8e51d29 504 /* PHY reset GPIO will be runtime programmed based on EVM version */
58a5491c 505 .reset_gpio_port[0] = -EINVAL,
e8e51d29 506 .reset_gpio_port[1] = -EINVAL,
58a5491c
FB		 507 .reset_gpio_port[2] = -EINVAL
508};
509
ca5742bd 510#ifdef CONFIG_OMAP_MUX
904c545c 511static struct omap_board_mux omap35x_board_mux[] __initdata = {
aa6912d8 512 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 513 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 514 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 515 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 516 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
517 OMAP_PIN_OFF_WAKEUPENABLE),
9bc64b89
VH		 518 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
519 OMAP_PIN_OFF_NONE),
520 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
521 OMAP_PIN_OFF_NONE),
741927f7
ER		 522#ifdef CONFIG_WL12XX_PLATFORM_DATA
523 /* WLAN IRQ - GPIO 149 */
aca6ad07 524 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
741927f7
ER		 525
526 /* WLAN POWER ENABLE - GPIO 150 */
527 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
528
529 /* MMC2 SDIO pin muxes for WL12xx */
530 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
531 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
532 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
533 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
534 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
535 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
536#endif
ca5742bd
TL		 537 { .reg_offset = OMAP_MUX_TERMINATOR },
538};
904c545c
VH		 539
540static struct omap_board_mux omap36x_board_mux[] __initdata = {
aa6912d8 541 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
f3a8cde6 542 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
aa6912d8 543 OMAP_PIN_OFF_WAKEUPENABLE),
87520aae 544 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
854c122f
VH		 545 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
546 OMAP_PIN_OFF_WAKEUPENABLE),
904c545c
VH		 547 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
548 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
549 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
550 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
551 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
552 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
553 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
554 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
555 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
556 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
557 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
558 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
559 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
aca6ad07
ER		 560#ifdef CONFIG_WL12XX_PLATFORM_DATA
561 /* WLAN IRQ - GPIO 149 */
562 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
563
564 /* WLAN POWER ENABLE - GPIO 150 */
565 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
566
567 /* MMC2 SDIO pin muxes for WL12xx */
568 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
569 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
570 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
571 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
572 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
573 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
574#endif
904c545c 575
ca5742bd
TL		 576 { .reg_offset = OMAP_MUX_TERMINATOR },
577};
904c545c
VH		 578#else
579#define omap35x_board_mux NULL
580#define omap36x_board_mux NULL
ca5742bd
TL		 581#endif
582
884b8369
MM		 583static struct omap_musb_board_data musb_board_data = {
584 .interface_type = MUSB_INTERFACE_ULPI,
585 .mode = MUSB_OTG,
586 .power = 100,
587};
588
bc593f5d
IG		 589static struct gpio omap3_evm_ehci_gpios[] __initdata = {
590 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
591 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
592};
593
70d669de
RK		 594static void __init omap3_evm_wl12xx_init(void)
595{
596#ifdef CONFIG_WL12XX_PLATFORM_DATA
597 int ret;
598
599 /* WL12xx WLAN Init */
46a0a540 600 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
70d669de
RK		 601 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
602 if (ret)
603 pr_err("error setting wl12xx data: %d\n", ret);
604 ret = platform_device_register(&omap3evm_wlan_regulator);
605 if (ret)
606 pr_err("error registering wl12xx device: %d\n", ret);
607#endif
608}
609
5b3689f4
RD		 610static struct regulator_consumer_supply dummy_supplies[] = {
611 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
612 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
613};
614
dc42c8bd
ZC		 615static struct mtd_partition omap3evm_nand_partitions[] = {
616 /* All the partition sizes are listed in terms of NAND block size */
617 {
618 .name = "X-Loader",
619 .offset = 0,
620 .size = 4*(SZ_128K),
621 .mask_flags = MTD_WRITEABLE
622 },
623 {
624 .name = "U-Boot",
625 .offset = MTDPART_OFS_APPEND,
626 .size = 14*(SZ_128K),
627 .mask_flags = MTD_WRITEABLE
628 },
629 {
630 .name = "U-Boot Env",
631 .offset = MTDPART_OFS_APPEND,
632 .size = 2*(SZ_128K)
633 },
634 {
635 .name = "Kernel",
636 .offset = MTDPART_OFS_APPEND,
637 .size = 40*(SZ_128K)
638 },
639 {
640 .name = "File system",
641 .size = MTDPART_SIZ_FULL,
642 .offset = MTDPART_OFS_APPEND,
643 },
644};
645
53c5ec31
SMK		 646static void __init omap3_evm_init(void)
647{
eeb3711b
PW		 648 struct omap_board_mux *obm;
649
db408023 650 omap3_evm_get_revision();
5b3689f4 651 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
904c545c 652
eeb3711b
PW		 653 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
654 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
db408023 655
e41cccfe
TL		 656 omap_board_config = omap3_evm_config;
657 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
db408023 658
d1589f09 659 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
3b972bf0 660 omap_hsmmc_init(mmc);
d1589f09 661
53c5ec31
SMK		 662 omap3_evm_i2c_init();
663
d5e13227 664 omap_display_init(&omap3_evm_dss_data);
53c5ec31 665
53c5ec31 666 omap_serial_init();
a4ca9dbe 667 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
1a4f4637 668
e8e2ff46
GAK		 669 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
670 usb_nop_xceiv_register();
1a4f4637 671
e8e51d29
AKG		 672 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
673 /* enable EHCI VBUS using GPIO22 */
bc593f5d 674 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
e8e51d29 675 /* Select EHCI port on main board */
bc593f5d
IG		 676 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
677 OMAP_PIN_INPUT_PULLUP);
678 gpio_request_array(omap3_evm_ehci_gpios,
679 ARRAY_SIZE(omap3_evm_ehci_gpios));
e8e51d29
AKG		 680
681 /* setup EHCI phy reset config */
4896e394 682 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
181b250c 683 usbhs_bdata.reset_gpio_port[1] = 21;
e8e51d29 684
58815fa3
AKG		 685 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
686 musb_board_data.power = 500;
687 musb_board_data.extvbus = 1;
e8e51d29
AKG		 688 } else {
689 /* setup EHCI phy reset on MDC */
4896e394 690 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
181b250c 691 usbhs_bdata.reset_gpio_port[1] = 135;
e8e51d29 692 }
884b8369 693 usb_musb_init(&musb_board_data);
9e64bb1e 694 usbhs_init(&usbhs_bdata);
dc42c8bd
ZC		 695 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
696 ARRAY_SIZE(omap3evm_nand_partitions));
697
96974a24 698 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
562138a4 699 omap3evm_init_smsc911x();
703e3061 700 omap3_evm_display_init();
70d669de 701 omap3_evm_wl12xx_init();
53c5ec31
SMK		 702}
703
53c5ec31
SMK		 704MACHINE_START(OMAP3EVM, "OMAP3 EVM")
705 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
5e52b435 706 .atag_offset = 0x100,
71ee7dad 707 .reserve = omap_reserve,
3dc3bad6 708 .map_io = omap3_map_io,
8f5b5a41 709 .init_early = omap35xx_init_early,
741e3a89 710 .init_irq = omap3_init_irq,
6b2f55d7 711 .handle_irq = omap3_intc_handle_irq,
53c5ec31 712 .init_machine = omap3_evm_init,
bbd707ac 713 .init_late = omap35xx_init_late,
e74984e4 714 .timer = &omap3_timer,
baa95883 715 .restart = omap_prcm_restart,
53c5ec31 716MACHINE_END
Linux kernel - Deliverables
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