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6ab9f69e RN |
1 | /* |
2 | * OMAP2430 clock data | |
3 | * | |
4 | * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. | |
5 | * Copyright (C) 2004-2011 Nokia Corporation | |
6 | * | |
7 | * Contacts: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/clk-private.h> | |
19 | #include <linux/list.h> | |
20 | ||
21 | #include "soc.h" | |
22 | #include "iomap.h" | |
23 | #include "clock.h" | |
24 | #include "clock2xxx.h" | |
25 | #include "opp2xxx.h" | |
26 | #include "cm2xxx.h" | |
27 | #include "prm2xxx.h" | |
28 | #include "prm-regbits-24xx.h" | |
29 | #include "cm-regbits-24xx.h" | |
30 | #include "sdrc.h" | |
31 | #include "control.h" | |
32 | ||
33 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR | |
34 | ||
35 | /* | |
36 | * 2430 clock tree. | |
37 | * | |
38 | * NOTE:In many cases here we are assigning a 'default' parent. In | |
39 | * many cases the parent is selectable. The set parent calls will | |
40 | * also switch sources. | |
41 | * | |
42 | * Several sources are given initial rates which may be wrong, this will | |
43 | * be fixed up in the init func. | |
44 | * | |
45 | * Things are broadly separated below by clock domains. It is | |
46 | * noteworthy that most peripherals have dependencies on multiple clock | |
47 | * domains. Many get their interface clocks from the L4 domain, but get | |
48 | * functional clocks from fixed sources or other core domain derived | |
49 | * clocks. | |
50 | */ | |
51 | ||
52 | DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); | |
53 | ||
54 | DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |
55 | ||
56 | DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); | |
57 | ||
58 | static struct clk osc_ck; | |
59 | ||
60 | static const struct clk_ops osc_ck_ops = { | |
61 | .enable = &omap2_enable_osc_ck, | |
62 | .disable = omap2_disable_osc_ck, | |
63 | .recalc_rate = &omap2_osc_clk_recalc, | |
64 | }; | |
65 | ||
66 | static struct clk_hw_omap osc_ck_hw = { | |
67 | .hw = { | |
68 | .clk = &osc_ck, | |
69 | }, | |
70 | }; | |
71 | ||
72 | static struct clk osc_ck = { | |
73 | .name = "osc_ck", | |
74 | .ops = &osc_ck_ops, | |
75 | .hw = &osc_ck_hw.hw, | |
76 | .flags = CLK_IS_ROOT, | |
77 | }; | |
78 | ||
79 | DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |
80 | ||
81 | static struct clk sys_ck; | |
82 | ||
83 | static const char *sys_ck_parent_names[] = { | |
84 | "osc_ck", | |
85 | }; | |
86 | ||
87 | static const struct clk_ops sys_ck_ops = { | |
88 | .init = &omap2_init_clk_clkdm, | |
89 | .recalc_rate = &omap2xxx_sys_clk_recalc, | |
90 | }; | |
91 | ||
92 | DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); | |
93 | DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); | |
94 | ||
95 | static struct dpll_data dpll_dd = { | |
96 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
97 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
98 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
99 | .clk_bypass = &sys_ck, | |
100 | .clk_ref = &sys_ck, | |
101 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
102 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
103 | .max_multiplier = 1023, | |
104 | .min_divider = 1, | |
105 | .max_divider = 16, | |
106 | }; | |
107 | ||
108 | static struct clk dpll_ck; | |
109 | ||
110 | static const char *dpll_ck_parent_names[] = { | |
111 | "sys_ck", | |
112 | }; | |
113 | ||
114 | static const struct clk_ops dpll_ck_ops = { | |
115 | .init = &omap2_init_clk_clkdm, | |
116 | .get_parent = &omap2_init_dpll_parent, | |
117 | .recalc_rate = &omap2_dpllcore_recalc, | |
118 | .round_rate = &omap2_dpll_round_rate, | |
119 | .set_rate = &omap2_reprogram_dpllcore, | |
120 | }; | |
121 | ||
122 | static struct clk_hw_omap dpll_ck_hw = { | |
123 | .hw = { | |
124 | .clk = &dpll_ck, | |
125 | }, | |
126 | .ops = &clkhwops_omap2xxx_dpll, | |
127 | .dpll_data = &dpll_dd, | |
128 | .clkdm_name = "wkup_clkdm", | |
129 | }; | |
130 | ||
131 | DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); | |
132 | ||
133 | static struct clk core_ck; | |
134 | ||
135 | static const char *core_ck_parent_names[] = { | |
136 | "dpll_ck", | |
137 | }; | |
138 | ||
139 | static const struct clk_ops core_ck_ops = { | |
140 | .init = &omap2_init_clk_clkdm, | |
141 | }; | |
142 | ||
143 | DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); | |
144 | DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); | |
145 | ||
146 | DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, | |
147 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
148 | OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, | |
149 | CLK_DIVIDER_ONE_BASED, NULL); | |
150 | ||
151 | DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, | |
152 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
153 | OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, | |
154 | CLK_DIVIDER_ONE_BASED, NULL); | |
155 | ||
156 | static struct clk aes_ick; | |
157 | ||
158 | static const char *aes_ick_parent_names[] = { | |
159 | "l4_ck", | |
160 | }; | |
161 | ||
162 | static const struct clk_ops aes_ick_ops = { | |
163 | .init = &omap2_init_clk_clkdm, | |
164 | .enable = &omap2_dflt_clk_enable, | |
165 | .disable = &omap2_dflt_clk_disable, | |
166 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
167 | }; | |
168 | ||
169 | static struct clk_hw_omap aes_ick_hw = { | |
170 | .hw = { | |
171 | .clk = &aes_ick, | |
172 | }, | |
173 | .ops = &clkhwops_iclk_wait, | |
174 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | |
175 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
176 | .clkdm_name = "core_l4_clkdm", | |
177 | }; | |
178 | ||
179 | DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); | |
180 | ||
181 | static struct clk apll54_ck; | |
182 | ||
183 | static const struct clk_ops apll54_ck_ops = { | |
184 | .init = &omap2_init_clk_clkdm, | |
185 | .enable = &omap2_clk_apll54_enable, | |
186 | .disable = &omap2_clk_apll54_disable, | |
187 | .recalc_rate = &omap2_clk_apll54_recalc, | |
188 | }; | |
189 | ||
190 | static struct clk_hw_omap apll54_ck_hw = { | |
191 | .hw = { | |
192 | .clk = &apll54_ck, | |
193 | }, | |
194 | .ops = &clkhwops_apll54, | |
195 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
196 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
197 | .flags = ENABLE_ON_INIT, | |
198 | .clkdm_name = "wkup_clkdm", | |
199 | }; | |
200 | ||
201 | DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); | |
202 | ||
203 | static struct clk apll96_ck; | |
204 | ||
205 | static const struct clk_ops apll96_ck_ops = { | |
206 | .init = &omap2_init_clk_clkdm, | |
207 | .enable = &omap2_clk_apll96_enable, | |
208 | .disable = &omap2_clk_apll96_disable, | |
209 | .recalc_rate = &omap2_clk_apll96_recalc, | |
210 | }; | |
211 | ||
212 | static struct clk_hw_omap apll96_ck_hw = { | |
213 | .hw = { | |
214 | .clk = &apll96_ck, | |
215 | }, | |
216 | .ops = &clkhwops_apll96, | |
217 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
218 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
219 | .flags = ENABLE_ON_INIT, | |
220 | .clkdm_name = "wkup_clkdm", | |
221 | }; | |
222 | ||
223 | DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); | |
224 | ||
225 | static const char *func_96m_ck_parent_names[] = { | |
226 | "apll96_ck", "alt_ck", | |
227 | }; | |
228 | ||
229 | DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, | |
230 | OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, | |
231 | OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); | |
232 | ||
233 | static struct clk cam_fck; | |
234 | ||
235 | static const char *cam_fck_parent_names[] = { | |
236 | "func_96m_ck", | |
237 | }; | |
238 | ||
239 | static struct clk_hw_omap cam_fck_hw = { | |
240 | .hw = { | |
241 | .clk = &cam_fck, | |
242 | }, | |
243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
244 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
245 | .clkdm_name = "core_l3_clkdm", | |
246 | }; | |
247 | ||
248 | DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); | |
249 | ||
250 | static struct clk cam_ick; | |
251 | ||
252 | static struct clk_hw_omap cam_ick_hw = { | |
253 | .hw = { | |
254 | .clk = &cam_ick, | |
255 | }, | |
256 | .ops = &clkhwops_iclk, | |
257 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
258 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
259 | .clkdm_name = "core_l4_clkdm", | |
260 | }; | |
261 | ||
262 | DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); | |
263 | ||
264 | static struct clk des_ick; | |
265 | ||
266 | static struct clk_hw_omap des_ick_hw = { | |
267 | .hw = { | |
268 | .clk = &des_ick, | |
269 | }, | |
270 | .ops = &clkhwops_iclk_wait, | |
271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | |
272 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
273 | .clkdm_name = "core_l4_clkdm", | |
274 | }; | |
275 | ||
276 | DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); | |
277 | ||
278 | static const struct clksel_rate dsp_fck_core_rates[] = { | |
279 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
280 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
281 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
282 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
283 | { .div = 0 } | |
284 | }; | |
285 | ||
286 | static const struct clksel dsp_fck_clksel[] = { | |
287 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
288 | { .parent = NULL }, | |
289 | }; | |
290 | ||
291 | static const char *dsp_fck_parent_names[] = { | |
292 | "core_ck", | |
293 | }; | |
294 | ||
295 | static struct clk dsp_fck; | |
296 | ||
297 | static const struct clk_ops dsp_fck_ops = { | |
298 | .init = &omap2_init_clk_clkdm, | |
299 | .enable = &omap2_dflt_clk_enable, | |
300 | .disable = &omap2_dflt_clk_disable, | |
301 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
302 | .recalc_rate = &omap2_clksel_recalc, | |
303 | .set_rate = &omap2_clksel_set_rate, | |
304 | .round_rate = &omap2_clksel_round_rate, | |
305 | }; | |
306 | ||
307 | DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, | |
308 | OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
309 | OMAP24XX_CLKSEL_DSP_MASK, | |
310 | OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | |
311 | OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, | |
312 | dsp_fck_parent_names, dsp_fck_ops); | |
313 | ||
314 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
315 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
316 | { .div = 0 } | |
317 | }; | |
318 | ||
319 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
320 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
321 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
322 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
323 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
324 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
325 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
326 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
327 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
328 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
329 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, | |
330 | { .div = 0 } | |
331 | }; | |
332 | ||
333 | static const struct clksel dss1_fck_clksel[] = { | |
334 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
335 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
336 | { .parent = NULL }, | |
337 | }; | |
338 | ||
339 | static const char *dss1_fck_parent_names[] = { | |
340 | "sys_ck", "core_ck", | |
341 | }; | |
342 | ||
343 | static const struct clk_ops dss1_fck_ops = { | |
344 | .init = &omap2_init_clk_clkdm, | |
345 | .enable = &omap2_dflt_clk_enable, | |
346 | .disable = &omap2_dflt_clk_disable, | |
347 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
348 | .recalc_rate = &omap2_clksel_recalc, | |
349 | .get_parent = &omap2_clksel_find_parent_index, | |
350 | .set_parent = &omap2_clksel_set_parent, | |
351 | }; | |
352 | ||
353 | DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, | |
354 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
355 | OMAP24XX_CLKSEL_DSS1_MASK, | |
356 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
357 | OMAP24XX_EN_DSS1_SHIFT, NULL, | |
358 | dss1_fck_parent_names, dss1_fck_ops); | |
359 | ||
360 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
361 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
362 | { .div = 0 } | |
363 | }; | |
364 | ||
365 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
366 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
367 | { .div = 0 } | |
368 | }; | |
369 | ||
370 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
371 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, | |
372 | { .div = 0 } | |
373 | }; | |
374 | ||
375 | static const struct clksel_rate func_48m_alt_rates[] = { | |
376 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
377 | { .div = 0 } | |
378 | }; | |
379 | ||
380 | static const struct clksel func_48m_clksel[] = { | |
381 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
382 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
383 | { .parent = NULL }, | |
384 | }; | |
385 | ||
386 | static const char *func_48m_ck_parent_names[] = { | |
387 | "apll96_ck", "alt_ck", | |
388 | }; | |
389 | ||
390 | static struct clk func_48m_ck; | |
391 | ||
392 | static const struct clk_ops func_48m_ck_ops = { | |
393 | .init = &omap2_init_clk_clkdm, | |
394 | .recalc_rate = &omap2_clksel_recalc, | |
395 | .set_rate = &omap2_clksel_set_rate, | |
396 | .round_rate = &omap2_clksel_round_rate, | |
397 | .get_parent = &omap2_clksel_find_parent_index, | |
398 | .set_parent = &omap2_clksel_set_parent, | |
399 | }; | |
400 | ||
401 | static struct clk_hw_omap func_48m_ck_hw = { | |
402 | .hw = { | |
403 | .clk = &func_48m_ck, | |
404 | }, | |
405 | .clksel = func_48m_clksel, | |
406 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
407 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, | |
408 | .clkdm_name = "wkup_clkdm", | |
409 | }; | |
410 | ||
411 | DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); | |
412 | ||
413 | static const struct clksel dss2_fck_clksel[] = { | |
414 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
415 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
416 | { .parent = NULL }, | |
417 | }; | |
418 | ||
419 | static const char *dss2_fck_parent_names[] = { | |
420 | "sys_ck", "func_48m_ck", | |
421 | }; | |
422 | ||
423 | DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, | |
424 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
425 | OMAP24XX_CLKSEL_DSS2_MASK, | |
426 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
427 | OMAP24XX_EN_DSS2_SHIFT, NULL, | |
428 | dss2_fck_parent_names, dss1_fck_ops); | |
429 | ||
430 | static const char *func_54m_ck_parent_names[] = { | |
431 | "apll54_ck", "alt_ck", | |
432 | }; | |
433 | ||
434 | DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, | |
435 | OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
436 | OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); | |
437 | ||
438 | static struct clk dss_54m_fck; | |
439 | ||
440 | static const char *dss_54m_fck_parent_names[] = { | |
441 | "func_54m_ck", | |
442 | }; | |
443 | ||
444 | static struct clk_hw_omap dss_54m_fck_hw = { | |
445 | .hw = { | |
446 | .clk = &dss_54m_fck, | |
447 | }, | |
448 | .ops = &clkhwops_wait, | |
449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
450 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
451 | .clkdm_name = "dss_clkdm", | |
452 | }; | |
453 | ||
454 | DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); | |
455 | ||
456 | static struct clk dss_ick; | |
457 | ||
458 | static struct clk_hw_omap dss_ick_hw = { | |
459 | .hw = { | |
460 | .clk = &dss_ick, | |
461 | }, | |
462 | .ops = &clkhwops_iclk, | |
463 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
464 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
465 | .clkdm_name = "dss_clkdm", | |
466 | }; | |
467 | ||
468 | DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); | |
469 | ||
470 | static struct clk emul_ck; | |
471 | ||
472 | static struct clk_hw_omap emul_ck_hw = { | |
473 | .hw = { | |
474 | .clk = &emul_ck, | |
475 | }, | |
476 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, | |
477 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | |
478 | .clkdm_name = "wkup_clkdm", | |
479 | }; | |
480 | ||
481 | DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); | |
482 | ||
483 | DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); | |
484 | ||
485 | static struct clk fac_fck; | |
486 | ||
487 | static const char *fac_fck_parent_names[] = { | |
488 | "func_12m_ck", | |
489 | }; | |
490 | ||
491 | static struct clk_hw_omap fac_fck_hw = { | |
492 | .hw = { | |
493 | .clk = &fac_fck, | |
494 | }, | |
495 | .ops = &clkhwops_wait, | |
496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
497 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
498 | .clkdm_name = "core_l4_clkdm", | |
499 | }; | |
500 | ||
501 | DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); | |
502 | ||
503 | static struct clk fac_ick; | |
504 | ||
505 | static struct clk_hw_omap fac_ick_hw = { | |
506 | .hw = { | |
507 | .clk = &fac_ick, | |
508 | }, | |
509 | .ops = &clkhwops_iclk_wait, | |
510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
511 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
512 | .clkdm_name = "core_l4_clkdm", | |
513 | }; | |
514 | ||
515 | DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); | |
516 | ||
517 | static const struct clksel gfx_fck_clksel[] = { | |
518 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
519 | { .parent = NULL }, | |
520 | }; | |
521 | ||
522 | static const char *gfx_2d_fck_parent_names[] = { | |
523 | "core_l3_ck", | |
524 | }; | |
525 | ||
526 | DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, | |
527 | OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
528 | OMAP_CLKSEL_GFX_MASK, | |
529 | OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
530 | OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, | |
531 | gfx_2d_fck_parent_names, dsp_fck_ops); | |
532 | ||
533 | DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, | |
534 | OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
535 | OMAP_CLKSEL_GFX_MASK, | |
536 | OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
537 | OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, | |
538 | gfx_2d_fck_parent_names, dsp_fck_ops); | |
539 | ||
540 | static struct clk gfx_ick; | |
541 | ||
542 | static const char *gfx_ick_parent_names[] = { | |
543 | "core_l3_ck", | |
544 | }; | |
545 | ||
546 | static struct clk_hw_omap gfx_ick_hw = { | |
547 | .hw = { | |
548 | .clk = &gfx_ick, | |
549 | }, | |
550 | .ops = &clkhwops_wait, | |
551 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
552 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
553 | .clkdm_name = "gfx_clkdm", | |
554 | }; | |
555 | ||
556 | DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); | |
557 | ||
558 | static struct clk gpio5_fck; | |
559 | ||
560 | static const char *gpio5_fck_parent_names[] = { | |
561 | "func_32k_ck", | |
562 | }; | |
563 | ||
564 | static struct clk_hw_omap gpio5_fck_hw = { | |
565 | .hw = { | |
566 | .clk = &gpio5_fck, | |
567 | }, | |
568 | .ops = &clkhwops_wait, | |
569 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
570 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
571 | .clkdm_name = "core_l4_clkdm", | |
572 | }; | |
573 | ||
574 | DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); | |
575 | ||
576 | static struct clk gpio5_ick; | |
577 | ||
578 | static struct clk_hw_omap gpio5_ick_hw = { | |
579 | .hw = { | |
580 | .clk = &gpio5_ick, | |
581 | }, | |
582 | .ops = &clkhwops_iclk_wait, | |
583 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
584 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
585 | .clkdm_name = "core_l4_clkdm", | |
586 | }; | |
587 | ||
588 | DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); | |
589 | ||
590 | static struct clk gpios_fck; | |
591 | ||
592 | static struct clk_hw_omap gpios_fck_hw = { | |
593 | .hw = { | |
594 | .clk = &gpios_fck, | |
595 | }, | |
596 | .ops = &clkhwops_wait, | |
597 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
598 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
599 | .clkdm_name = "wkup_clkdm", | |
600 | }; | |
601 | ||
602 | DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); | |
603 | ||
6ab9f69e RN |
604 | static struct clk gpios_ick; |
605 | ||
606 | static const char *gpios_ick_parent_names[] = { | |
dd1e4223 | 607 | "sys_ck", |
6ab9f69e RN |
608 | }; |
609 | ||
610 | static struct clk_hw_omap gpios_ick_hw = { | |
611 | .hw = { | |
612 | .clk = &gpios_ick, | |
613 | }, | |
614 | .ops = &clkhwops_iclk_wait, | |
615 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
616 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
617 | .clkdm_name = "wkup_clkdm", | |
618 | }; | |
619 | ||
620 | DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); | |
621 | ||
622 | static struct clk gpmc_fck; | |
623 | ||
624 | static struct clk_hw_omap gpmc_fck_hw = { | |
625 | .hw = { | |
626 | .clk = &gpmc_fck, | |
627 | }, | |
628 | .ops = &clkhwops_iclk, | |
629 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
630 | .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, | |
631 | .flags = ENABLE_ON_INIT, | |
632 | .clkdm_name = "core_l3_clkdm", | |
633 | }; | |
634 | ||
635 | DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); | |
636 | ||
637 | static const struct clksel_rate gpt_alt_rates[] = { | |
638 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, | |
639 | { .div = 0 } | |
640 | }; | |
641 | ||
642 | static const struct clksel omap24xx_gpt_clksel[] = { | |
643 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
644 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
645 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
646 | { .parent = NULL }, | |
647 | }; | |
648 | ||
649 | static const char *gpt10_fck_parent_names[] = { | |
650 | "func_32k_ck", "sys_ck", "alt_ck", | |
651 | }; | |
652 | ||
653 | DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
654 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
655 | OMAP24XX_CLKSEL_GPT10_MASK, | |
656 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
657 | OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, | |
658 | gpt10_fck_parent_names, dss1_fck_ops); | |
659 | ||
660 | static struct clk gpt10_ick; | |
661 | ||
662 | static struct clk_hw_omap gpt10_ick_hw = { | |
663 | .hw = { | |
664 | .clk = &gpt10_ick, | |
665 | }, | |
666 | .ops = &clkhwops_iclk_wait, | |
667 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
668 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
669 | .clkdm_name = "core_l4_clkdm", | |
670 | }; | |
671 | ||
672 | DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); | |
673 | ||
674 | DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
675 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
676 | OMAP24XX_CLKSEL_GPT11_MASK, | |
677 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
678 | OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, | |
679 | gpt10_fck_parent_names, dss1_fck_ops); | |
680 | ||
681 | static struct clk gpt11_ick; | |
682 | ||
683 | static struct clk_hw_omap gpt11_ick_hw = { | |
684 | .hw = { | |
685 | .clk = &gpt11_ick, | |
686 | }, | |
687 | .ops = &clkhwops_iclk_wait, | |
688 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
689 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
690 | .clkdm_name = "core_l4_clkdm", | |
691 | }; | |
692 | ||
693 | DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); | |
694 | ||
695 | DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
696 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
697 | OMAP24XX_CLKSEL_GPT12_MASK, | |
698 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
699 | OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, | |
700 | gpt10_fck_parent_names, dss1_fck_ops); | |
701 | ||
702 | static struct clk gpt12_ick; | |
703 | ||
704 | static struct clk_hw_omap gpt12_ick_hw = { | |
705 | .hw = { | |
706 | .clk = &gpt12_ick, | |
707 | }, | |
708 | .ops = &clkhwops_iclk_wait, | |
709 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
710 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
711 | .clkdm_name = "core_l4_clkdm", | |
712 | }; | |
713 | ||
714 | DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); | |
715 | ||
716 | static const struct clk_ops gpt1_fck_ops = { | |
717 | .init = &omap2_init_clk_clkdm, | |
718 | .enable = &omap2_dflt_clk_enable, | |
719 | .disable = &omap2_dflt_clk_disable, | |
720 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
721 | .recalc_rate = &omap2_clksel_recalc, | |
722 | .set_rate = &omap2_clksel_set_rate, | |
723 | .round_rate = &omap2_clksel_round_rate, | |
724 | .get_parent = &omap2_clksel_find_parent_index, | |
725 | .set_parent = &omap2_clksel_set_parent, | |
726 | }; | |
727 | ||
728 | DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
729 | OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
730 | OMAP24XX_CLKSEL_GPT1_MASK, | |
731 | OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
732 | OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, | |
733 | gpt10_fck_parent_names, gpt1_fck_ops); | |
734 | ||
735 | static struct clk gpt1_ick; | |
736 | ||
737 | static struct clk_hw_omap gpt1_ick_hw = { | |
738 | .hw = { | |
739 | .clk = &gpt1_ick, | |
740 | }, | |
741 | .ops = &clkhwops_iclk_wait, | |
742 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
743 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
744 | .clkdm_name = "wkup_clkdm", | |
745 | }; | |
746 | ||
747 | DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); | |
748 | ||
749 | DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
750 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
751 | OMAP24XX_CLKSEL_GPT2_MASK, | |
752 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
753 | OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, | |
754 | gpt10_fck_parent_names, dss1_fck_ops); | |
755 | ||
756 | static struct clk gpt2_ick; | |
757 | ||
758 | static struct clk_hw_omap gpt2_ick_hw = { | |
759 | .hw = { | |
760 | .clk = &gpt2_ick, | |
761 | }, | |
762 | .ops = &clkhwops_iclk_wait, | |
763 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
764 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
765 | .clkdm_name = "core_l4_clkdm", | |
766 | }; | |
767 | ||
768 | DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); | |
769 | ||
770 | DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
771 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
772 | OMAP24XX_CLKSEL_GPT3_MASK, | |
773 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
774 | OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, | |
775 | gpt10_fck_parent_names, dss1_fck_ops); | |
776 | ||
777 | static struct clk gpt3_ick; | |
778 | ||
779 | static struct clk_hw_omap gpt3_ick_hw = { | |
780 | .hw = { | |
781 | .clk = &gpt3_ick, | |
782 | }, | |
783 | .ops = &clkhwops_iclk_wait, | |
784 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
785 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
786 | .clkdm_name = "core_l4_clkdm", | |
787 | }; | |
788 | ||
789 | DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); | |
790 | ||
791 | DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
792 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
793 | OMAP24XX_CLKSEL_GPT4_MASK, | |
794 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
795 | OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, | |
796 | gpt10_fck_parent_names, dss1_fck_ops); | |
797 | ||
798 | static struct clk gpt4_ick; | |
799 | ||
800 | static struct clk_hw_omap gpt4_ick_hw = { | |
801 | .hw = { | |
802 | .clk = &gpt4_ick, | |
803 | }, | |
804 | .ops = &clkhwops_iclk_wait, | |
805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
806 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
807 | .clkdm_name = "core_l4_clkdm", | |
808 | }; | |
809 | ||
810 | DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); | |
811 | ||
812 | DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
813 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
814 | OMAP24XX_CLKSEL_GPT5_MASK, | |
815 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
816 | OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, | |
817 | gpt10_fck_parent_names, dss1_fck_ops); | |
818 | ||
819 | static struct clk gpt5_ick; | |
820 | ||
821 | static struct clk_hw_omap gpt5_ick_hw = { | |
822 | .hw = { | |
823 | .clk = &gpt5_ick, | |
824 | }, | |
825 | .ops = &clkhwops_iclk_wait, | |
826 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
827 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
828 | .clkdm_name = "core_l4_clkdm", | |
829 | }; | |
830 | ||
831 | DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); | |
832 | ||
833 | DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
834 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
835 | OMAP24XX_CLKSEL_GPT6_MASK, | |
836 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
837 | OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, | |
838 | gpt10_fck_parent_names, dss1_fck_ops); | |
839 | ||
840 | static struct clk gpt6_ick; | |
841 | ||
842 | static struct clk_hw_omap gpt6_ick_hw = { | |
843 | .hw = { | |
844 | .clk = &gpt6_ick, | |
845 | }, | |
846 | .ops = &clkhwops_iclk_wait, | |
847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
848 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
849 | .clkdm_name = "core_l4_clkdm", | |
850 | }; | |
851 | ||
852 | DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); | |
853 | ||
854 | DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
855 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
856 | OMAP24XX_CLKSEL_GPT7_MASK, | |
857 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
858 | OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, | |
859 | gpt10_fck_parent_names, dss1_fck_ops); | |
860 | ||
861 | static struct clk gpt7_ick; | |
862 | ||
863 | static struct clk_hw_omap gpt7_ick_hw = { | |
864 | .hw = { | |
865 | .clk = &gpt7_ick, | |
866 | }, | |
867 | .ops = &clkhwops_iclk_wait, | |
868 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
869 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
870 | .clkdm_name = "core_l4_clkdm", | |
871 | }; | |
872 | ||
873 | DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); | |
874 | ||
875 | static struct clk gpt8_fck; | |
876 | ||
877 | DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
878 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
879 | OMAP24XX_CLKSEL_GPT8_MASK, | |
880 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
881 | OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, | |
882 | gpt10_fck_parent_names, dss1_fck_ops); | |
883 | ||
884 | static struct clk gpt8_ick; | |
885 | ||
886 | static struct clk_hw_omap gpt8_ick_hw = { | |
887 | .hw = { | |
888 | .clk = &gpt8_ick, | |
889 | }, | |
890 | .ops = &clkhwops_iclk_wait, | |
891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
892 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
893 | .clkdm_name = "core_l4_clkdm", | |
894 | }; | |
895 | ||
896 | DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); | |
897 | ||
898 | DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, | |
899 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
900 | OMAP24XX_CLKSEL_GPT9_MASK, | |
901 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
902 | OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, | |
903 | gpt10_fck_parent_names, dss1_fck_ops); | |
904 | ||
905 | static struct clk gpt9_ick; | |
906 | ||
907 | static struct clk_hw_omap gpt9_ick_hw = { | |
908 | .hw = { | |
909 | .clk = &gpt9_ick, | |
910 | }, | |
911 | .ops = &clkhwops_iclk_wait, | |
912 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
913 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
914 | .clkdm_name = "core_l4_clkdm", | |
915 | }; | |
916 | ||
917 | DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); | |
918 | ||
919 | static struct clk hdq_fck; | |
920 | ||
921 | static struct clk_hw_omap hdq_fck_hw = { | |
922 | .hw = { | |
923 | .clk = &hdq_fck, | |
924 | }, | |
925 | .ops = &clkhwops_wait, | |
926 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
927 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
928 | .clkdm_name = "core_l4_clkdm", | |
929 | }; | |
930 | ||
931 | DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); | |
932 | ||
933 | static struct clk hdq_ick; | |
934 | ||
935 | static struct clk_hw_omap hdq_ick_hw = { | |
936 | .hw = { | |
937 | .clk = &hdq_ick, | |
938 | }, | |
939 | .ops = &clkhwops_iclk_wait, | |
940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
941 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
942 | .clkdm_name = "core_l4_clkdm", | |
943 | }; | |
944 | ||
945 | DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); | |
946 | ||
947 | static struct clk i2c1_ick; | |
948 | ||
949 | static struct clk_hw_omap i2c1_ick_hw = { | |
950 | .hw = { | |
951 | .clk = &i2c1_ick, | |
952 | }, | |
953 | .ops = &clkhwops_iclk_wait, | |
954 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
955 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
956 | .clkdm_name = "core_l4_clkdm", | |
957 | }; | |
958 | ||
959 | DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); | |
960 | ||
961 | static struct clk i2c2_ick; | |
962 | ||
963 | static struct clk_hw_omap i2c2_ick_hw = { | |
964 | .hw = { | |
965 | .clk = &i2c2_ick, | |
966 | }, | |
967 | .ops = &clkhwops_iclk_wait, | |
968 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
969 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
970 | .clkdm_name = "core_l4_clkdm", | |
971 | }; | |
972 | ||
973 | DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); | |
974 | ||
975 | static struct clk i2chs1_fck; | |
976 | ||
977 | static struct clk_hw_omap i2chs1_fck_hw = { | |
978 | .hw = { | |
979 | .clk = &i2chs1_fck, | |
980 | }, | |
981 | .ops = &clkhwops_omap2430_i2chs_wait, | |
982 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
983 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
984 | .clkdm_name = "core_l4_clkdm", | |
985 | }; | |
986 | ||
987 | DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); | |
988 | ||
989 | static struct clk i2chs2_fck; | |
990 | ||
991 | static struct clk_hw_omap i2chs2_fck_hw = { | |
992 | .hw = { | |
993 | .clk = &i2chs2_fck, | |
994 | }, | |
995 | .ops = &clkhwops_omap2430_i2chs_wait, | |
996 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
997 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
998 | .clkdm_name = "core_l4_clkdm", | |
999 | }; | |
1000 | ||
1001 | DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); | |
1002 | ||
1003 | static struct clk icr_ick; | |
1004 | ||
1005 | static struct clk_hw_omap icr_ick_hw = { | |
1006 | .hw = { | |
1007 | .clk = &icr_ick, | |
1008 | }, | |
1009 | .ops = &clkhwops_iclk_wait, | |
1010 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1011 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | |
1012 | .clkdm_name = "wkup_clkdm", | |
1013 | }; | |
1014 | ||
1015 | DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); | |
1016 | ||
1017 | static const struct clksel dsp_ick_clksel[] = { | |
1018 | { .parent = &dsp_fck, .rates = dsp_ick_rates }, | |
1019 | { .parent = NULL }, | |
1020 | }; | |
1021 | ||
1022 | static const char *iva2_1_ick_parent_names[] = { | |
1023 | "dsp_fck", | |
1024 | }; | |
1025 | ||
1026 | DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, | |
1027 | OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
1028 | OMAP24XX_CLKSEL_DSP_IF_MASK, | |
1029 | OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | |
1030 | OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, | |
1031 | iva2_1_ick_parent_names, dsp_fck_ops); | |
1032 | ||
1033 | static struct clk mailboxes_ick; | |
1034 | ||
1035 | static struct clk_hw_omap mailboxes_ick_hw = { | |
1036 | .hw = { | |
1037 | .clk = &mailboxes_ick, | |
1038 | }, | |
1039 | .ops = &clkhwops_iclk_wait, | |
1040 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1041 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1042 | .clkdm_name = "core_l4_clkdm", | |
1043 | }; | |
1044 | ||
1045 | DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); | |
1046 | ||
1047 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1048 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
1049 | { .div = 0 } | |
1050 | }; | |
1051 | ||
1052 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1053 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1054 | { .div = 0 } | |
1055 | }; | |
1056 | ||
1057 | static const struct clksel mcbsp_fck_clksel[] = { | |
1058 | { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, | |
1059 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1060 | { .parent = NULL }, | |
1061 | }; | |
1062 | ||
1063 | static const char *mcbsp1_fck_parent_names[] = { | |
1064 | "func_96m_ck", "mcbsp_clks", | |
1065 | }; | |
1066 | ||
1067 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, | |
1068 | OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1069 | OMAP2_MCBSP1_CLKS_MASK, | |
1070 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1071 | OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, | |
1072 | mcbsp1_fck_parent_names, dss1_fck_ops); | |
1073 | ||
1074 | static struct clk mcbsp1_ick; | |
1075 | ||
1076 | static struct clk_hw_omap mcbsp1_ick_hw = { | |
1077 | .hw = { | |
1078 | .clk = &mcbsp1_ick, | |
1079 | }, | |
1080 | .ops = &clkhwops_iclk_wait, | |
1081 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1082 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1083 | .clkdm_name = "core_l4_clkdm", | |
1084 | }; | |
1085 | ||
1086 | DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); | |
1087 | ||
1088 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, | |
1089 | OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1090 | OMAP2_MCBSP2_CLKS_MASK, | |
1091 | OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1092 | OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, | |
1093 | mcbsp1_fck_parent_names, dss1_fck_ops); | |
1094 | ||
1095 | static struct clk mcbsp2_ick; | |
1096 | ||
1097 | static struct clk_hw_omap mcbsp2_ick_hw = { | |
1098 | .hw = { | |
1099 | .clk = &mcbsp2_ick, | |
1100 | }, | |
1101 | .ops = &clkhwops_iclk_wait, | |
1102 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1103 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1104 | .clkdm_name = "core_l4_clkdm", | |
1105 | }; | |
1106 | ||
1107 | DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); | |
1108 | ||
1109 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, | |
1110 | OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), | |
1111 | OMAP2_MCBSP3_CLKS_MASK, | |
1112 | OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1113 | OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, | |
1114 | mcbsp1_fck_parent_names, dss1_fck_ops); | |
1115 | ||
1116 | static struct clk mcbsp3_ick; | |
1117 | ||
1118 | static struct clk_hw_omap mcbsp3_ick_hw = { | |
1119 | .hw = { | |
1120 | .clk = &mcbsp3_ick, | |
1121 | }, | |
1122 | .ops = &clkhwops_iclk_wait, | |
1123 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1124 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1125 | .clkdm_name = "core_l4_clkdm", | |
1126 | }; | |
1127 | ||
1128 | DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); | |
1129 | ||
1130 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, | |
1131 | OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), | |
1132 | OMAP2_MCBSP4_CLKS_MASK, | |
1133 | OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1134 | OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, | |
1135 | mcbsp1_fck_parent_names, dss1_fck_ops); | |
1136 | ||
1137 | static struct clk mcbsp4_ick; | |
1138 | ||
1139 | static struct clk_hw_omap mcbsp4_ick_hw = { | |
1140 | .hw = { | |
1141 | .clk = &mcbsp4_ick, | |
1142 | }, | |
1143 | .ops = &clkhwops_iclk_wait, | |
1144 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1145 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1146 | .clkdm_name = "core_l4_clkdm", | |
1147 | }; | |
1148 | ||
1149 | DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); | |
1150 | ||
1151 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, | |
1152 | OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), | |
1153 | OMAP2_MCBSP5_CLKS_MASK, | |
1154 | OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1155 | OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, | |
1156 | mcbsp1_fck_parent_names, dss1_fck_ops); | |
1157 | ||
1158 | static struct clk mcbsp5_ick; | |
1159 | ||
1160 | static struct clk_hw_omap mcbsp5_ick_hw = { | |
1161 | .hw = { | |
1162 | .clk = &mcbsp5_ick, | |
1163 | }, | |
1164 | .ops = &clkhwops_iclk_wait, | |
1165 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1166 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1167 | .clkdm_name = "core_l4_clkdm", | |
1168 | }; | |
1169 | ||
1170 | DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); | |
1171 | ||
1172 | static struct clk mcspi1_fck; | |
1173 | ||
1174 | static const char *mcspi1_fck_parent_names[] = { | |
1175 | "func_48m_ck", | |
1176 | }; | |
1177 | ||
1178 | static struct clk_hw_omap mcspi1_fck_hw = { | |
1179 | .hw = { | |
1180 | .clk = &mcspi1_fck, | |
1181 | }, | |
1182 | .ops = &clkhwops_wait, | |
1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1184 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1185 | .clkdm_name = "core_l4_clkdm", | |
1186 | }; | |
1187 | ||
1188 | DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1189 | ||
1190 | static struct clk mcspi1_ick; | |
1191 | ||
1192 | static struct clk_hw_omap mcspi1_ick_hw = { | |
1193 | .hw = { | |
1194 | .clk = &mcspi1_ick, | |
1195 | }, | |
1196 | .ops = &clkhwops_iclk_wait, | |
1197 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1198 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1199 | .clkdm_name = "core_l4_clkdm", | |
1200 | }; | |
1201 | ||
1202 | DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); | |
1203 | ||
1204 | static struct clk mcspi2_fck; | |
1205 | ||
1206 | static struct clk_hw_omap mcspi2_fck_hw = { | |
1207 | .hw = { | |
1208 | .clk = &mcspi2_fck, | |
1209 | }, | |
1210 | .ops = &clkhwops_wait, | |
1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1212 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1213 | .clkdm_name = "core_l4_clkdm", | |
1214 | }; | |
1215 | ||
1216 | DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1217 | ||
1218 | static struct clk mcspi2_ick; | |
1219 | ||
1220 | static struct clk_hw_omap mcspi2_ick_hw = { | |
1221 | .hw = { | |
1222 | .clk = &mcspi2_ick, | |
1223 | }, | |
1224 | .ops = &clkhwops_iclk_wait, | |
1225 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1226 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1227 | .clkdm_name = "core_l4_clkdm", | |
1228 | }; | |
1229 | ||
1230 | DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); | |
1231 | ||
1232 | static struct clk mcspi3_fck; | |
1233 | ||
1234 | static struct clk_hw_omap mcspi3_fck_hw = { | |
1235 | .hw = { | |
1236 | .clk = &mcspi3_fck, | |
1237 | }, | |
1238 | .ops = &clkhwops_wait, | |
1239 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1240 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1241 | .clkdm_name = "core_l4_clkdm", | |
1242 | }; | |
1243 | ||
1244 | DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1245 | ||
1246 | static struct clk mcspi3_ick; | |
1247 | ||
1248 | static struct clk_hw_omap mcspi3_ick_hw = { | |
1249 | .hw = { | |
1250 | .clk = &mcspi3_ick, | |
1251 | }, | |
1252 | .ops = &clkhwops_iclk_wait, | |
1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1254 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1255 | .clkdm_name = "core_l4_clkdm", | |
1256 | }; | |
1257 | ||
1258 | DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); | |
1259 | ||
1260 | static const struct clksel_rate mdm_ick_core_rates[] = { | |
1261 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, | |
1262 | { .div = 4, .val = 4, .flags = RATE_IN_243X }, | |
1263 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, | |
1264 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, | |
1265 | { .div = 0 } | |
1266 | }; | |
1267 | ||
1268 | static const struct clksel mdm_ick_clksel[] = { | |
1269 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, | |
1270 | { .parent = NULL }, | |
1271 | }; | |
1272 | ||
1273 | static const char *mdm_ick_parent_names[] = { | |
1274 | "core_ck", | |
1275 | }; | |
1276 | ||
1277 | DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, | |
1278 | OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | |
1279 | OMAP2430_CLKSEL_MDM_MASK, | |
1280 | OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | |
1281 | OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | |
1282 | &clkhwops_iclk_wait, mdm_ick_parent_names, | |
1283 | dsp_fck_ops); | |
1284 | ||
1285 | static struct clk mdm_intc_ick; | |
1286 | ||
1287 | static struct clk_hw_omap mdm_intc_ick_hw = { | |
1288 | .hw = { | |
1289 | .clk = &mdm_intc_ick, | |
1290 | }, | |
1291 | .ops = &clkhwops_iclk_wait, | |
1292 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1293 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | |
1294 | .clkdm_name = "core_l4_clkdm", | |
1295 | }; | |
1296 | ||
1297 | DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); | |
1298 | ||
1299 | static struct clk mdm_osc_ck; | |
1300 | ||
1301 | static struct clk_hw_omap mdm_osc_ck_hw = { | |
1302 | .hw = { | |
1303 | .clk = &mdm_osc_ck, | |
1304 | }, | |
1305 | .ops = &clkhwops_iclk_wait, | |
1306 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), | |
1307 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | |
1308 | .clkdm_name = "mdm_clkdm", | |
1309 | }; | |
1310 | ||
1311 | DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); | |
1312 | ||
1313 | static struct clk mmchs1_fck; | |
1314 | ||
1315 | static struct clk_hw_omap mmchs1_fck_hw = { | |
1316 | .hw = { | |
1317 | .clk = &mmchs1_fck, | |
1318 | }, | |
1319 | .ops = &clkhwops_wait, | |
1320 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1321 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1322 | .clkdm_name = "core_l4_clkdm", | |
1323 | }; | |
1324 | ||
1325 | DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); | |
1326 | ||
1327 | static struct clk mmchs1_ick; | |
1328 | ||
1329 | static struct clk_hw_omap mmchs1_ick_hw = { | |
1330 | .hw = { | |
1331 | .clk = &mmchs1_ick, | |
1332 | }, | |
1333 | .ops = &clkhwops_iclk_wait, | |
1334 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1335 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1336 | .clkdm_name = "core_l4_clkdm", | |
1337 | }; | |
1338 | ||
1339 | DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); | |
1340 | ||
1341 | static struct clk mmchs2_fck; | |
1342 | ||
1343 | static struct clk_hw_omap mmchs2_fck_hw = { | |
1344 | .hw = { | |
1345 | .clk = &mmchs2_fck, | |
1346 | }, | |
1347 | .ops = &clkhwops_wait, | |
1348 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1349 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1350 | .clkdm_name = "core_l4_clkdm", | |
1351 | }; | |
1352 | ||
1353 | DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); | |
1354 | ||
1355 | static struct clk mmchs2_ick; | |
1356 | ||
1357 | static struct clk_hw_omap mmchs2_ick_hw = { | |
1358 | .hw = { | |
1359 | .clk = &mmchs2_ick, | |
1360 | }, | |
1361 | .ops = &clkhwops_iclk_wait, | |
1362 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1363 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1364 | .clkdm_name = "core_l4_clkdm", | |
1365 | }; | |
1366 | ||
1367 | DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); | |
1368 | ||
1369 | static struct clk mmchsdb1_fck; | |
1370 | ||
1371 | static struct clk_hw_omap mmchsdb1_fck_hw = { | |
1372 | .hw = { | |
1373 | .clk = &mmchsdb1_fck, | |
1374 | }, | |
1375 | .ops = &clkhwops_wait, | |
1376 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1377 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | |
1378 | .clkdm_name = "core_l4_clkdm", | |
1379 | }; | |
1380 | ||
1381 | DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); | |
1382 | ||
1383 | static struct clk mmchsdb2_fck; | |
1384 | ||
1385 | static struct clk_hw_omap mmchsdb2_fck_hw = { | |
1386 | .hw = { | |
1387 | .clk = &mmchsdb2_fck, | |
1388 | }, | |
1389 | .ops = &clkhwops_wait, | |
1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1391 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | |
1392 | .clkdm_name = "core_l4_clkdm", | |
1393 | }; | |
1394 | ||
1395 | DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); | |
1396 | ||
1397 | DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, | |
1398 | OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
1399 | OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, | |
1400 | CLK_DIVIDER_ONE_BASED, NULL); | |
1401 | ||
1402 | static struct clk mpu_wdt_fck; | |
1403 | ||
1404 | static struct clk_hw_omap mpu_wdt_fck_hw = { | |
1405 | .hw = { | |
1406 | .clk = &mpu_wdt_fck, | |
1407 | }, | |
1408 | .ops = &clkhwops_wait, | |
1409 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
1410 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1411 | .clkdm_name = "wkup_clkdm", | |
1412 | }; | |
1413 | ||
1414 | DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); | |
1415 | ||
1416 | static struct clk mpu_wdt_ick; | |
1417 | ||
1418 | static struct clk_hw_omap mpu_wdt_ick_hw = { | |
1419 | .hw = { | |
1420 | .clk = &mpu_wdt_ick, | |
1421 | }, | |
1422 | .ops = &clkhwops_iclk_wait, | |
1423 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1424 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1425 | .clkdm_name = "wkup_clkdm", | |
1426 | }; | |
1427 | ||
1428 | DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); | |
1429 | ||
1430 | static struct clk mspro_fck; | |
1431 | ||
1432 | static struct clk_hw_omap mspro_fck_hw = { | |
1433 | .hw = { | |
1434 | .clk = &mspro_fck, | |
1435 | }, | |
1436 | .ops = &clkhwops_wait, | |
1437 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1438 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1439 | .clkdm_name = "core_l4_clkdm", | |
1440 | }; | |
1441 | ||
1442 | DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); | |
1443 | ||
1444 | static struct clk mspro_ick; | |
1445 | ||
1446 | static struct clk_hw_omap mspro_ick_hw = { | |
1447 | .hw = { | |
1448 | .clk = &mspro_ick, | |
1449 | }, | |
1450 | .ops = &clkhwops_iclk_wait, | |
1451 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1452 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1453 | .clkdm_name = "core_l4_clkdm", | |
1454 | }; | |
1455 | ||
1456 | DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); | |
1457 | ||
1458 | static struct clk omapctrl_ick; | |
1459 | ||
1460 | static struct clk_hw_omap omapctrl_ick_hw = { | |
1461 | .hw = { | |
1462 | .clk = &omapctrl_ick, | |
1463 | }, | |
1464 | .ops = &clkhwops_iclk_wait, | |
1465 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1466 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1467 | .flags = ENABLE_ON_INIT, | |
1468 | .clkdm_name = "wkup_clkdm", | |
1469 | }; | |
1470 | ||
1471 | DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); | |
1472 | ||
1473 | static struct clk pka_ick; | |
1474 | ||
1475 | static struct clk_hw_omap pka_ick_hw = { | |
1476 | .hw = { | |
1477 | .clk = &pka_ick, | |
1478 | }, | |
1479 | .ops = &clkhwops_iclk_wait, | |
1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | |
1481 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1482 | .clkdm_name = "core_l4_clkdm", | |
1483 | }; | |
1484 | ||
1485 | DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); | |
1486 | ||
1487 | static struct clk rng_ick; | |
1488 | ||
1489 | static struct clk_hw_omap rng_ick_hw = { | |
1490 | .hw = { | |
1491 | .clk = &rng_ick, | |
1492 | }, | |
1493 | .ops = &clkhwops_iclk_wait, | |
1494 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | |
1495 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1496 | .clkdm_name = "core_l4_clkdm", | |
1497 | }; | |
1498 | ||
1499 | DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); | |
1500 | ||
1501 | static struct clk sdma_fck; | |
1502 | ||
1503 | DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); | |
1504 | DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); | |
1505 | ||
1506 | static struct clk sdma_ick; | |
1507 | ||
1508 | static struct clk_hw_omap sdma_ick_hw = { | |
1509 | .hw = { | |
1510 | .clk = &sdma_ick, | |
1511 | }, | |
1512 | .ops = &clkhwops_iclk, | |
1513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1514 | .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, | |
1515 | .clkdm_name = "core_l3_clkdm", | |
1516 | }; | |
1517 | ||
1518 | DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); | |
1519 | ||
1520 | static struct clk sdrc_ick; | |
1521 | ||
1522 | static struct clk_hw_omap sdrc_ick_hw = { | |
1523 | .hw = { | |
1524 | .clk = &sdrc_ick, | |
1525 | }, | |
1526 | .ops = &clkhwops_iclk, | |
1527 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1528 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | |
1529 | .flags = ENABLE_ON_INIT, | |
1530 | .clkdm_name = "core_l3_clkdm", | |
1531 | }; | |
1532 | ||
1533 | DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); | |
1534 | ||
1535 | static struct clk sha_ick; | |
1536 | ||
1537 | static struct clk_hw_omap sha_ick_hw = { | |
1538 | .hw = { | |
1539 | .clk = &sha_ick, | |
1540 | }, | |
1541 | .ops = &clkhwops_iclk_wait, | |
1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | |
1543 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1544 | .clkdm_name = "core_l4_clkdm", | |
1545 | }; | |
1546 | ||
1547 | DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); | |
1548 | ||
1549 | static struct clk ssi_l4_ick; | |
1550 | ||
1551 | static struct clk_hw_omap ssi_l4_ick_hw = { | |
1552 | .hw = { | |
1553 | .clk = &ssi_l4_ick, | |
1554 | }, | |
1555 | .ops = &clkhwops_iclk_wait, | |
1556 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1557 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
1558 | .clkdm_name = "core_l4_clkdm", | |
1559 | }; | |
1560 | ||
1561 | DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); | |
1562 | ||
1563 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | |
1564 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1565 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
1566 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
1567 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
1568 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | |
1569 | { .div = 0 } | |
1570 | }; | |
1571 | ||
1572 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
1573 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
1574 | { .parent = NULL }, | |
1575 | }; | |
1576 | ||
1577 | static const char *ssi_ssr_sst_fck_parent_names[] = { | |
1578 | "core_ck", | |
1579 | }; | |
1580 | ||
1581 | DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", | |
1582 | ssi_ssr_sst_fck_clksel, | |
1583 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
1584 | OMAP24XX_CLKSEL_SSI_MASK, | |
1585 | OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1586 | OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, | |
1587 | ssi_ssr_sst_fck_parent_names, dsp_fck_ops); | |
1588 | ||
1589 | static struct clk sync_32k_ick; | |
1590 | ||
1591 | static struct clk_hw_omap sync_32k_ick_hw = { | |
1592 | .hw = { | |
1593 | .clk = &sync_32k_ick, | |
1594 | }, | |
1595 | .ops = &clkhwops_iclk_wait, | |
1596 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1597 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1598 | .flags = ENABLE_ON_INIT, | |
1599 | .clkdm_name = "wkup_clkdm", | |
1600 | }; | |
1601 | ||
1602 | DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); | |
1603 | ||
1604 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
1605 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
1606 | { .div = 0 } | |
1607 | }; | |
1608 | ||
1609 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
1610 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1611 | { .div = 0 } | |
1612 | }; | |
1613 | ||
1614 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
1615 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, | |
1616 | { .div = 0 } | |
1617 | }; | |
1618 | ||
1619 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
1620 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, | |
1621 | { .div = 0 } | |
1622 | }; | |
1623 | ||
1624 | static const struct clksel common_clkout_src_clksel[] = { | |
1625 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
1626 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
1627 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
1628 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
1629 | { .parent = NULL }, | |
1630 | }; | |
1631 | ||
1632 | static const char *sys_clkout_src_parent_names[] = { | |
1633 | "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", | |
1634 | }; | |
1635 | ||
1636 | DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, | |
1637 | OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, | |
1638 | OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, | |
1639 | NULL, sys_clkout_src_parent_names, gpt1_fck_ops); | |
1640 | ||
1641 | DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, | |
1642 | OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, | |
1643 | OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
1644 | ||
1645 | static struct clk uart1_fck; | |
1646 | ||
1647 | static struct clk_hw_omap uart1_fck_hw = { | |
1648 | .hw = { | |
1649 | .clk = &uart1_fck, | |
1650 | }, | |
1651 | .ops = &clkhwops_wait, | |
1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1653 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1654 | .clkdm_name = "core_l4_clkdm", | |
1655 | }; | |
1656 | ||
1657 | DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1658 | ||
1659 | static struct clk uart1_ick; | |
1660 | ||
1661 | static struct clk_hw_omap uart1_ick_hw = { | |
1662 | .hw = { | |
1663 | .clk = &uart1_ick, | |
1664 | }, | |
1665 | .ops = &clkhwops_iclk_wait, | |
1666 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1667 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1668 | .clkdm_name = "core_l4_clkdm", | |
1669 | }; | |
1670 | ||
1671 | DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); | |
1672 | ||
1673 | static struct clk uart2_fck; | |
1674 | ||
1675 | static struct clk_hw_omap uart2_fck_hw = { | |
1676 | .hw = { | |
1677 | .clk = &uart2_fck, | |
1678 | }, | |
1679 | .ops = &clkhwops_wait, | |
1680 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1681 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1682 | .clkdm_name = "core_l4_clkdm", | |
1683 | }; | |
1684 | ||
1685 | DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1686 | ||
1687 | static struct clk uart2_ick; | |
1688 | ||
1689 | static struct clk_hw_omap uart2_ick_hw = { | |
1690 | .hw = { | |
1691 | .clk = &uart2_ick, | |
1692 | }, | |
1693 | .ops = &clkhwops_iclk_wait, | |
1694 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1695 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1696 | .clkdm_name = "core_l4_clkdm", | |
1697 | }; | |
1698 | ||
1699 | DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); | |
1700 | ||
1701 | static struct clk uart3_fck; | |
1702 | ||
1703 | static struct clk_hw_omap uart3_fck_hw = { | |
1704 | .hw = { | |
1705 | .clk = &uart3_fck, | |
1706 | }, | |
1707 | .ops = &clkhwops_wait, | |
1708 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1709 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1710 | .clkdm_name = "core_l4_clkdm", | |
1711 | }; | |
1712 | ||
1713 | DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1714 | ||
1715 | static struct clk uart3_ick; | |
1716 | ||
1717 | static struct clk_hw_omap uart3_ick_hw = { | |
1718 | .hw = { | |
1719 | .clk = &uart3_ick, | |
1720 | }, | |
1721 | .ops = &clkhwops_iclk_wait, | |
1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1723 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1724 | .clkdm_name = "core_l4_clkdm", | |
1725 | }; | |
1726 | ||
1727 | DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); | |
1728 | ||
1729 | static struct clk usb_fck; | |
1730 | ||
1731 | static struct clk_hw_omap usb_fck_hw = { | |
1732 | .hw = { | |
1733 | .clk = &usb_fck, | |
1734 | }, | |
1735 | .ops = &clkhwops_wait, | |
1736 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | |
1737 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1738 | .clkdm_name = "core_l3_clkdm", | |
1739 | }; | |
1740 | ||
1741 | DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); | |
1742 | ||
1743 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
1744 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1745 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
1746 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
1747 | { .div = 0 } | |
1748 | }; | |
1749 | ||
1750 | static const struct clksel usb_l4_ick_clksel[] = { | |
1751 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
1752 | { .parent = NULL }, | |
1753 | }; | |
1754 | ||
1755 | static const char *usb_l4_ick_parent_names[] = { | |
1756 | "core_l3_ck", | |
1757 | }; | |
1758 | ||
1759 | DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, | |
1760 | OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
1761 | OMAP24XX_CLKSEL_USB_MASK, | |
1762 | OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1763 | OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, | |
1764 | usb_l4_ick_parent_names, dsp_fck_ops); | |
1765 | ||
1766 | static struct clk usbhs_ick; | |
1767 | ||
1768 | static struct clk_hw_omap usbhs_ick_hw = { | |
1769 | .hw = { | |
1770 | .clk = &usbhs_ick, | |
1771 | }, | |
1772 | .ops = &clkhwops_iclk_wait, | |
1773 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1774 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | |
1775 | .clkdm_name = "core_l3_clkdm", | |
1776 | }; | |
1777 | ||
1778 | DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); | |
1779 | ||
1780 | static struct clk virt_prcm_set; | |
1781 | ||
1782 | static const char *virt_prcm_set_parent_names[] = { | |
1783 | "mpu_ck", | |
1784 | }; | |
1785 | ||
1786 | static const struct clk_ops virt_prcm_set_ops = { | |
1787 | .recalc_rate = &omap2_table_mpu_recalc, | |
1788 | .set_rate = &omap2_select_table_rate, | |
1789 | .round_rate = &omap2_round_to_table_rate, | |
1790 | }; | |
1791 | ||
1792 | DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); | |
1793 | DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); | |
1794 | ||
1795 | static struct clk wdt1_ick; | |
1796 | ||
1797 | static struct clk_hw_omap wdt1_ick_hw = { | |
1798 | .hw = { | |
1799 | .clk = &wdt1_ick, | |
1800 | }, | |
1801 | .ops = &clkhwops_iclk_wait, | |
1802 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1803 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1804 | .clkdm_name = "wkup_clkdm", | |
1805 | }; | |
1806 | ||
1807 | DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); | |
1808 | ||
6ab9f69e RN |
1809 | static struct clk wdt4_fck; |
1810 | ||
1811 | static struct clk_hw_omap wdt4_fck_hw = { | |
1812 | .hw = { | |
1813 | .clk = &wdt4_fck, | |
1814 | }, | |
1815 | .ops = &clkhwops_wait, | |
1816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1817 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1818 | .clkdm_name = "core_l4_clkdm", | |
1819 | }; | |
1820 | ||
1821 | DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); | |
1822 | ||
1823 | static struct clk wdt4_ick; | |
1824 | ||
1825 | static struct clk_hw_omap wdt4_ick_hw = { | |
1826 | .hw = { | |
1827 | .clk = &wdt4_ick, | |
1828 | }, | |
1829 | .ops = &clkhwops_iclk_wait, | |
1830 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1831 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1832 | .clkdm_name = "core_l4_clkdm", | |
1833 | }; | |
1834 | ||
1835 | DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); | |
1836 | ||
1837 | /* | |
1838 | * clkdev integration | |
1839 | */ | |
1840 | ||
1841 | static struct omap_clk omap2430_clks[] = { | |
1842 | /* external root sources */ | |
78e52e02 K |
1843 | CLK(NULL, "func_32k_ck", &func_32k_ck), |
1844 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), | |
1845 | CLK(NULL, "osc_ck", &osc_ck), | |
1846 | CLK("twl", "fck", &osc_ck), | |
1847 | CLK(NULL, "sys_ck", &sys_ck), | |
1848 | CLK(NULL, "alt_ck", &alt_ck), | |
1849 | CLK(NULL, "mcbsp_clks", &mcbsp_clks), | |
6ab9f69e | 1850 | /* internal analog sources */ |
78e52e02 K |
1851 | CLK(NULL, "dpll_ck", &dpll_ck), |
1852 | CLK(NULL, "apll96_ck", &apll96_ck), | |
1853 | CLK(NULL, "apll54_ck", &apll54_ck), | |
6ab9f69e | 1854 | /* internal prcm root sources */ |
78e52e02 K |
1855 | CLK(NULL, "func_54m_ck", &func_54m_ck), |
1856 | CLK(NULL, "core_ck", &core_ck), | |
1857 | CLK(NULL, "func_96m_ck", &func_96m_ck), | |
1858 | CLK(NULL, "func_48m_ck", &func_48m_ck), | |
1859 | CLK(NULL, "func_12m_ck", &func_12m_ck), | |
1860 | CLK(NULL, "sys_clkout_src", &sys_clkout_src), | |
1861 | CLK(NULL, "sys_clkout", &sys_clkout), | |
1862 | CLK(NULL, "emul_ck", &emul_ck), | |
6ab9f69e | 1863 | /* mpu domain clocks */ |
78e52e02 | 1864 | CLK(NULL, "mpu_ck", &mpu_ck), |
6ab9f69e | 1865 | /* dsp domain clocks */ |
78e52e02 K |
1866 | CLK(NULL, "dsp_fck", &dsp_fck), |
1867 | CLK(NULL, "iva2_1_ick", &iva2_1_ick), | |
6ab9f69e | 1868 | /* GFX domain clocks */ |
78e52e02 K |
1869 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), |
1870 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), | |
1871 | CLK(NULL, "gfx_ick", &gfx_ick), | |
6ab9f69e | 1872 | /* Modem domain clocks */ |
78e52e02 K |
1873 | CLK(NULL, "mdm_ick", &mdm_ick), |
1874 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), | |
6ab9f69e | 1875 | /* DSS domain clocks */ |
78e52e02 K |
1876 | CLK("omapdss_dss", "ick", &dss_ick), |
1877 | CLK(NULL, "dss_ick", &dss_ick), | |
1878 | CLK(NULL, "dss1_fck", &dss1_fck), | |
1879 | CLK(NULL, "dss2_fck", &dss2_fck), | |
1880 | CLK(NULL, "dss_54m_fck", &dss_54m_fck), | |
6ab9f69e | 1881 | /* L3 domain clocks */ |
78e52e02 K |
1882 | CLK(NULL, "core_l3_ck", &core_l3_ck), |
1883 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), | |
1884 | CLK(NULL, "usb_l4_ick", &usb_l4_ick), | |
6ab9f69e | 1885 | /* L4 domain clocks */ |
78e52e02 K |
1886 | CLK(NULL, "l4_ck", &l4_ck), |
1887 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), | |
6ab9f69e | 1888 | /* virtual meta-group clock */ |
78e52e02 | 1889 | CLK(NULL, "virt_prcm_set", &virt_prcm_set), |
6ab9f69e | 1890 | /* general l4 interface ck, multi-parent functional clk */ |
78e52e02 K |
1891 | CLK(NULL, "gpt1_ick", &gpt1_ick), |
1892 | CLK(NULL, "gpt1_fck", &gpt1_fck), | |
1893 | CLK(NULL, "gpt2_ick", &gpt2_ick), | |
1894 | CLK(NULL, "gpt2_fck", &gpt2_fck), | |
1895 | CLK(NULL, "gpt3_ick", &gpt3_ick), | |
1896 | CLK(NULL, "gpt3_fck", &gpt3_fck), | |
1897 | CLK(NULL, "gpt4_ick", &gpt4_ick), | |
1898 | CLK(NULL, "gpt4_fck", &gpt4_fck), | |
1899 | CLK(NULL, "gpt5_ick", &gpt5_ick), | |
1900 | CLK(NULL, "gpt5_fck", &gpt5_fck), | |
1901 | CLK(NULL, "gpt6_ick", &gpt6_ick), | |
1902 | CLK(NULL, "gpt6_fck", &gpt6_fck), | |
1903 | CLK(NULL, "gpt7_ick", &gpt7_ick), | |
1904 | CLK(NULL, "gpt7_fck", &gpt7_fck), | |
1905 | CLK(NULL, "gpt8_ick", &gpt8_ick), | |
1906 | CLK(NULL, "gpt8_fck", &gpt8_fck), | |
1907 | CLK(NULL, "gpt9_ick", &gpt9_ick), | |
1908 | CLK(NULL, "gpt9_fck", &gpt9_fck), | |
1909 | CLK(NULL, "gpt10_ick", &gpt10_ick), | |
1910 | CLK(NULL, "gpt10_fck", &gpt10_fck), | |
1911 | CLK(NULL, "gpt11_ick", &gpt11_ick), | |
1912 | CLK(NULL, "gpt11_fck", &gpt11_fck), | |
1913 | CLK(NULL, "gpt12_ick", &gpt12_ick), | |
1914 | CLK(NULL, "gpt12_fck", &gpt12_fck), | |
1915 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), | |
1916 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), | |
1917 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), | |
1918 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), | |
1919 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), | |
1920 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), | |
1921 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), | |
1922 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), | |
1923 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), | |
1924 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), | |
1925 | CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), | |
1926 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), | |
1927 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), | |
1928 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), | |
1929 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), | |
1930 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick), | |
1931 | CLK(NULL, "mcspi1_ick", &mcspi1_ick), | |
1932 | CLK(NULL, "mcspi1_fck", &mcspi1_fck), | |
1933 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick), | |
1934 | CLK(NULL, "mcspi2_ick", &mcspi2_ick), | |
1935 | CLK(NULL, "mcspi2_fck", &mcspi2_fck), | |
1936 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick), | |
1937 | CLK(NULL, "mcspi3_ick", &mcspi3_ick), | |
1938 | CLK(NULL, "mcspi3_fck", &mcspi3_fck), | |
1939 | CLK(NULL, "uart1_ick", &uart1_ick), | |
1940 | CLK(NULL, "uart1_fck", &uart1_fck), | |
1941 | CLK(NULL, "uart2_ick", &uart2_ick), | |
1942 | CLK(NULL, "uart2_fck", &uart2_fck), | |
1943 | CLK(NULL, "uart3_ick", &uart3_ick), | |
1944 | CLK(NULL, "uart3_fck", &uart3_fck), | |
1945 | CLK(NULL, "gpios_ick", &gpios_ick), | |
1946 | CLK(NULL, "gpios_fck", &gpios_fck), | |
1947 | CLK("omap_wdt", "ick", &mpu_wdt_ick), | |
1948 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), | |
1949 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), | |
1950 | CLK(NULL, "sync_32k_ick", &sync_32k_ick), | |
1951 | CLK(NULL, "wdt1_ick", &wdt1_ick), | |
1952 | CLK(NULL, "omapctrl_ick", &omapctrl_ick), | |
1953 | CLK(NULL, "icr_ick", &icr_ick), | |
1954 | CLK("omap24xxcam", "fck", &cam_fck), | |
1955 | CLK(NULL, "cam_fck", &cam_fck), | |
1956 | CLK("omap24xxcam", "ick", &cam_ick), | |
1957 | CLK(NULL, "cam_ick", &cam_ick), | |
1958 | CLK(NULL, "mailboxes_ick", &mailboxes_ick), | |
1959 | CLK(NULL, "wdt4_ick", &wdt4_ick), | |
1960 | CLK(NULL, "wdt4_fck", &wdt4_fck), | |
1961 | CLK(NULL, "mspro_ick", &mspro_ick), | |
1962 | CLK(NULL, "mspro_fck", &mspro_fck), | |
1963 | CLK(NULL, "fac_ick", &fac_ick), | |
1964 | CLK(NULL, "fac_fck", &fac_fck), | |
1965 | CLK("omap_hdq.0", "ick", &hdq_ick), | |
1966 | CLK(NULL, "hdq_ick", &hdq_ick), | |
1967 | CLK("omap_hdq.1", "fck", &hdq_fck), | |
1968 | CLK(NULL, "hdq_fck", &hdq_fck), | |
1969 | CLK("omap_i2c.1", "ick", &i2c1_ick), | |
1970 | CLK(NULL, "i2c1_ick", &i2c1_ick), | |
1971 | CLK(NULL, "i2chs1_fck", &i2chs1_fck), | |
1972 | CLK("omap_i2c.2", "ick", &i2c2_ick), | |
1973 | CLK(NULL, "i2c2_ick", &i2c2_ick), | |
1974 | CLK(NULL, "i2chs2_fck", &i2chs2_fck), | |
1975 | CLK(NULL, "gpmc_fck", &gpmc_fck), | |
1976 | CLK(NULL, "sdma_fck", &sdma_fck), | |
1977 | CLK(NULL, "sdma_ick", &sdma_ick), | |
1978 | CLK(NULL, "sdrc_ick", &sdrc_ick), | |
1979 | CLK(NULL, "des_ick", &des_ick), | |
1980 | CLK("omap-sham", "ick", &sha_ick), | |
e569e994 MG |
1981 | CLK(NULL, "sha_ick", &sha_ick), |
1982 | CLK("omap_rng", "ick", &rng_ick), | |
78e52e02 K |
1983 | CLK(NULL, "rng_ick", &rng_ick), |
1984 | CLK("omap-aes", "ick", &aes_ick), | |
1985 | CLK(NULL, "pka_ick", &pka_ick), | |
1986 | CLK(NULL, "usb_fck", &usb_fck), | |
1987 | CLK("musb-omap2430", "ick", &usbhs_ick), | |
1988 | CLK(NULL, "usbhs_ick", &usbhs_ick), | |
1989 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick), | |
1990 | CLK(NULL, "mmchs1_ick", &mmchs1_ick), | |
1991 | CLK(NULL, "mmchs1_fck", &mmchs1_fck), | |
1992 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick), | |
1993 | CLK(NULL, "mmchs2_ick", &mmchs2_ick), | |
1994 | CLK(NULL, "mmchs2_fck", &mmchs2_fck), | |
1995 | CLK(NULL, "gpio5_ick", &gpio5_ick), | |
1996 | CLK(NULL, "gpio5_fck", &gpio5_fck), | |
1997 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), | |
1998 | CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), | |
1999 | CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), | |
2000 | CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), | |
2001 | CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), | |
2002 | CLK(NULL, "timer_32k_ck", &func_32k_ck), | |
2003 | CLK(NULL, "timer_sys_ck", &sys_ck), | |
2004 | CLK(NULL, "timer_ext_ck", &alt_ck), | |
2005 | CLK(NULL, "cpufreq_ck", &virt_prcm_set), | |
6ab9f69e RN |
2006 | }; |
2007 | ||
2008 | static const char *enable_init_clks[] = { | |
2009 | "apll96_ck", | |
2010 | "apll54_ck", | |
2011 | "sync_32k_ick", | |
2012 | "omapctrl_ick", | |
2013 | "gpmc_fck", | |
2014 | "sdrc_ick", | |
2015 | }; | |
2016 | ||
2017 | /* | |
2018 | * init code | |
2019 | */ | |
2020 | ||
2021 | int __init omap2430_clk_init(void) | |
2022 | { | |
6ab9f69e RN |
2023 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; |
2024 | cpu_mask = RATE_IN_243X; | |
2025 | rate_table = omap2430_rate_table; | |
2026 | ||
2027 | omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); | |
2028 | ||
2029 | omap2xxx_clkt_vps_check_bootloader_rates(); | |
2030 | ||
78e52e02 | 2031 | omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); |
6ab9f69e | 2032 | |
bdcc6127 JH |
2033 | omap2xxx_clkt_vps_late_init(); |
2034 | ||
6ab9f69e RN |
2035 | omap2_clk_disable_autoidle_all(); |
2036 | ||
2037 | omap2_clk_enable_init_clocks(enable_init_clks, | |
2038 | ARRAY_SIZE(enable_init_clks)); | |
2039 | ||
2040 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", | |
2041 | (clk_get_rate(&sys_ck) / 1000000), | |
2042 | (clk_get_rate(&sys_ck) / 100000) % 10, | |
2043 | (clk_get_rate(&dpll_ck) / 1000000), | |
2044 | (clk_get_rate(&mpu_ck) / 1000000)); | |
2045 | ||
2046 | return 0; | |
2047 | } |