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cb26867e RN |
1 | /* |
2 | * OMAP4 Clock data | |
3 | * | |
4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
6 | * | |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * Mike Turquette (mturquette@ti.com) | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * XXX Some of the ES1 clocks have been removed/changed; once support | |
17 | * is added for discriminating clocks by ES level, these should be added back | |
18 | * in. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/clk-private.h> | |
24 | #include <linux/clkdev.h> | |
25 | #include <linux/io.h> | |
26 | ||
27 | #include "soc.h" | |
28 | #include "iomap.h" | |
29 | #include "clock.h" | |
30 | #include "clock44xx.h" | |
31 | #include "cm1_44xx.h" | |
32 | #include "cm2_44xx.h" | |
33 | #include "cm-regbits-44xx.h" | |
34 | #include "prm44xx.h" | |
35 | #include "prm-regbits-44xx.h" | |
36 | #include "control.h" | |
37 | #include "scrm44xx.h" | |
38 | ||
39 | /* OMAP4 modulemode control */ | |
40 | #define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 | |
41 | #define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 | |
42 | ||
8c197ccf JH |
43 | /* |
44 | * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section | |
45 | * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK | |
46 | * must be set to 196.608 MHz" and hence, the DPLL locked frequency is | |
47 | * half of this value. | |
48 | */ | |
49 | #define OMAP4_DPLL_ABE_DEFFREQ 98304000 | |
50 | ||
cb26867e RN |
51 | /* Root clocks */ |
52 | ||
53 | DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); | |
54 | ||
55 | DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); | |
56 | ||
57 | DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, | |
58 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, | |
59 | 0x0, NULL); | |
60 | ||
61 | DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); | |
62 | ||
63 | DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); | |
64 | ||
65 | DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); | |
66 | ||
67 | DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, | |
68 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | |
69 | 0x0, NULL); | |
70 | ||
71 | DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); | |
72 | ||
73 | DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); | |
74 | ||
75 | DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); | |
76 | ||
77 | DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); | |
78 | ||
79 | DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); | |
80 | ||
81 | DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); | |
82 | ||
83 | DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); | |
84 | ||
85 | DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); | |
86 | ||
87 | static const char *sys_clkin_ck_parents[] = { | |
88 | "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", | |
89 | "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", | |
90 | "virt_38400000_ck", | |
91 | }; | |
92 | ||
93 | DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, | |
94 | OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, | |
95 | OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); | |
96 | ||
97 | DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); | |
98 | ||
99 | DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); | |
100 | ||
101 | DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); | |
102 | ||
103 | DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); | |
104 | ||
105 | DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); | |
106 | ||
107 | /* Module clocks and DPLL outputs */ | |
108 | ||
109 | static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { | |
110 | "sys_clkin_ck", "sys_32k_ck", | |
111 | }; | |
112 | ||
113 | DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, | |
114 | NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, | |
115 | OMAP4430_CLKSEL_WIDTH, 0x0, NULL); | |
116 | ||
117 | DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, | |
118 | 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
119 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
120 | ||
121 | /* DPLL_ABE */ | |
122 | static struct dpll_data dpll_abe_dd = { | |
123 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | |
124 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, | |
125 | .clk_ref = &abe_dpll_refclk_mux_ck, | |
126 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | |
127 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
128 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | |
129 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | |
130 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
131 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
132 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
133 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
134 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
3ff51ed8 JH |
135 | .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK, |
136 | .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK, | |
cb26867e RN |
137 | .max_multiplier = 2047, |
138 | .max_divider = 128, | |
139 | .min_divider = 1, | |
140 | }; | |
141 | ||
142 | ||
143 | static const char *dpll_abe_ck_parents[] = { | |
144 | "abe_dpll_refclk_mux_ck", | |
145 | }; | |
146 | ||
147 | static struct clk dpll_abe_ck; | |
148 | ||
149 | static const struct clk_ops dpll_abe_ck_ops = { | |
150 | .enable = &omap3_noncore_dpll_enable, | |
151 | .disable = &omap3_noncore_dpll_disable, | |
152 | .recalc_rate = &omap4_dpll_regm4xen_recalc, | |
153 | .round_rate = &omap4_dpll_regm4xen_round_rate, | |
154 | .set_rate = &omap3_noncore_dpll_set_rate, | |
155 | .get_parent = &omap2_init_dpll_parent, | |
156 | }; | |
157 | ||
158 | static struct clk_hw_omap dpll_abe_ck_hw = { | |
159 | .hw = { | |
160 | .clk = &dpll_abe_ck, | |
161 | }, | |
162 | .dpll_data = &dpll_abe_dd, | |
163 | .ops = &clkhwops_omap3_dpll, | |
164 | }; | |
165 | ||
166 | DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); | |
167 | ||
168 | static const char *dpll_abe_x2_ck_parents[] = { | |
169 | "dpll_abe_ck", | |
170 | }; | |
171 | ||
172 | static struct clk dpll_abe_x2_ck; | |
173 | ||
174 | static const struct clk_ops dpll_abe_x2_ck_ops = { | |
175 | .recalc_rate = &omap3_clkoutx2_recalc, | |
176 | }; | |
177 | ||
178 | static struct clk_hw_omap dpll_abe_x2_ck_hw = { | |
179 | .hw = { | |
180 | .clk = &dpll_abe_x2_ck, | |
181 | }, | |
182 | .flags = CLOCK_CLKOUTX2, | |
183 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | |
184 | .ops = &clkhwops_omap4_dpllmx, | |
185 | }; | |
186 | ||
187 | DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); | |
188 | ||
189 | static const struct clk_ops omap_hsdivider_ops = { | |
190 | .set_rate = &omap2_clksel_set_rate, | |
191 | .recalc_rate = &omap2_clksel_recalc, | |
192 | .round_rate = &omap2_clksel_round_rate, | |
193 | }; | |
194 | ||
195 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, | |
196 | 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, | |
197 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
198 | ||
199 | DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, | |
200 | 0x0, 1, 8); | |
201 | ||
202 | DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, | |
203 | OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, | |
204 | OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
205 | ||
206 | DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, | |
207 | OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
208 | OMAP4430_CLKSEL_AESS_FCLK_SHIFT, | |
209 | OMAP4430_CLKSEL_AESS_FCLK_WIDTH, | |
210 | 0x0, NULL); | |
211 | ||
212 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, | |
213 | 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, | |
214 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); | |
215 | ||
216 | static const char *core_hsd_byp_clk_mux_ck_parents[] = { | |
217 | "sys_clkin_ck", "dpll_abe_m3x2_ck", | |
218 | }; | |
219 | ||
220 | DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, | |
221 | 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, | |
222 | OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, | |
223 | 0x0, NULL); | |
224 | ||
225 | /* DPLL_CORE */ | |
226 | static struct dpll_data dpll_core_dd = { | |
227 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
228 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | |
229 | .clk_ref = &sys_clkin_ck, | |
230 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, | |
231 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
232 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | |
233 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | |
234 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
235 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
236 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
237 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
238 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
239 | .max_multiplier = 2047, | |
240 | .max_divider = 128, | |
241 | .min_divider = 1, | |
242 | }; | |
243 | ||
244 | ||
245 | static const char *dpll_core_ck_parents[] = { | |
b8675e2c | 246 | "sys_clkin_ck", "core_hsd_byp_clk_mux_ck" |
cb26867e RN |
247 | }; |
248 | ||
249 | static struct clk dpll_core_ck; | |
250 | ||
251 | static const struct clk_ops dpll_core_ck_ops = { | |
252 | .recalc_rate = &omap3_dpll_recalc, | |
253 | .get_parent = &omap2_init_dpll_parent, | |
254 | }; | |
255 | ||
256 | static struct clk_hw_omap dpll_core_ck_hw = { | |
257 | .hw = { | |
258 | .clk = &dpll_core_ck, | |
259 | }, | |
260 | .dpll_data = &dpll_core_dd, | |
261 | .ops = &clkhwops_omap3_dpll, | |
262 | }; | |
263 | ||
264 | DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); | |
265 | ||
266 | static const char *dpll_core_x2_ck_parents[] = { | |
267 | "dpll_core_ck", | |
268 | }; | |
269 | ||
270 | static struct clk dpll_core_x2_ck; | |
271 | ||
272 | static struct clk_hw_omap dpll_core_x2_ck_hw = { | |
273 | .hw = { | |
274 | .clk = &dpll_core_x2_ck, | |
275 | }, | |
276 | }; | |
277 | ||
278 | DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); | |
279 | ||
280 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", | |
281 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, | |
282 | OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); | |
283 | ||
284 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, | |
285 | OMAP4430_CM_DIV_M2_DPLL_CORE, | |
286 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
287 | ||
288 | DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, | |
289 | 2); | |
290 | ||
291 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", | |
292 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, | |
293 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
294 | ||
295 | DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, | |
296 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, | |
297 | OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); | |
298 | ||
628a37d4 PW |
299 | DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, |
300 | 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT, | |
301 | OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
cb26867e RN |
302 | |
303 | DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, | |
304 | 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, | |
305 | OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
306 | ||
307 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", | |
308 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, | |
309 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
310 | ||
311 | DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, | |
312 | 0x0, 1, 2); | |
313 | ||
314 | DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, | |
315 | OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, | |
316 | OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); | |
317 | ||
318 | static const struct clk_ops dmic_fck_ops = { | |
319 | .enable = &omap2_dflt_clk_enable, | |
320 | .disable = &omap2_dflt_clk_disable, | |
321 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
322 | .recalc_rate = &omap2_clksel_recalc, | |
323 | .get_parent = &omap2_clksel_find_parent_index, | |
324 | .set_parent = &omap2_clksel_set_parent, | |
325 | .init = &omap2_init_clk_clkdm, | |
326 | }; | |
327 | ||
328 | static const char *dpll_core_m3x2_ck_parents[] = { | |
329 | "dpll_core_x2_ck", | |
330 | }; | |
331 | ||
332 | static const struct clksel dpll_core_m3x2_div[] = { | |
333 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | |
334 | { .parent = NULL }, | |
335 | }; | |
336 | ||
337 | /* XXX Missing round_rate, set_rate in ops */ | |
338 | DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, | |
339 | OMAP4430_CM_DIV_M3_DPLL_CORE, | |
340 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
341 | OMAP4430_CM_DIV_M3_DPLL_CORE, | |
342 | OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, | |
343 | dpll_core_m3x2_ck_parents, dmic_fck_ops); | |
344 | ||
345 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", | |
346 | &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, | |
347 | OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); | |
348 | ||
349 | static const char *iva_hsd_byp_clk_mux_ck_parents[] = { | |
350 | "sys_clkin_ck", "div_iva_hs_clk", | |
351 | }; | |
352 | ||
353 | DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, | |
354 | 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, | |
355 | OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); | |
356 | ||
357 | /* DPLL_IVA */ | |
358 | static struct dpll_data dpll_iva_dd = { | |
359 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
360 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | |
361 | .clk_ref = &sys_clkin_ck, | |
362 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, | |
363 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
364 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | |
365 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | |
366 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
367 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
368 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
369 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
370 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
371 | .max_multiplier = 2047, | |
372 | .max_divider = 128, | |
373 | .min_divider = 1, | |
374 | }; | |
375 | ||
b8675e2c PW |
376 | static const char *dpll_iva_ck_parents[] = { |
377 | "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck" | |
378 | }; | |
379 | ||
cb26867e RN |
380 | static struct clk dpll_iva_ck; |
381 | ||
9b4fcc86 JH |
382 | static const struct clk_ops dpll_ck_ops = { |
383 | .enable = &omap3_noncore_dpll_enable, | |
384 | .disable = &omap3_noncore_dpll_disable, | |
385 | .recalc_rate = &omap3_dpll_recalc, | |
386 | .round_rate = &omap2_dpll_round_rate, | |
387 | .set_rate = &omap3_noncore_dpll_set_rate, | |
388 | .get_parent = &omap2_init_dpll_parent, | |
389 | }; | |
390 | ||
cb26867e RN |
391 | static struct clk_hw_omap dpll_iva_ck_hw = { |
392 | .hw = { | |
393 | .clk = &dpll_iva_ck, | |
394 | }, | |
395 | .dpll_data = &dpll_iva_dd, | |
396 | .ops = &clkhwops_omap3_dpll, | |
397 | }; | |
398 | ||
b8675e2c | 399 | DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops); |
cb26867e RN |
400 | |
401 | static const char *dpll_iva_x2_ck_parents[] = { | |
402 | "dpll_iva_ck", | |
403 | }; | |
404 | ||
405 | static struct clk dpll_iva_x2_ck; | |
406 | ||
407 | static struct clk_hw_omap dpll_iva_x2_ck_hw = { | |
408 | .hw = { | |
409 | .clk = &dpll_iva_x2_ck, | |
410 | }, | |
411 | }; | |
412 | ||
413 | DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); | |
414 | ||
415 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, | |
416 | 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, | |
417 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
418 | ||
419 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, | |
420 | 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, | |
421 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
422 | ||
423 | /* DPLL_MPU */ | |
424 | static struct dpll_data dpll_mpu_dd = { | |
425 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | |
426 | .clk_bypass = &div_mpu_hs_clk, | |
427 | .clk_ref = &sys_clkin_ck, | |
428 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, | |
429 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
430 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | |
431 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | |
432 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
433 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
434 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
435 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
436 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
437 | .max_multiplier = 2047, | |
438 | .max_divider = 128, | |
439 | .min_divider = 1, | |
440 | }; | |
441 | ||
b8675e2c PW |
442 | static const char *dpll_mpu_ck_parents[] = { |
443 | "sys_clkin_ck", "div_mpu_hs_clk" | |
444 | }; | |
445 | ||
cb26867e RN |
446 | static struct clk dpll_mpu_ck; |
447 | ||
448 | static struct clk_hw_omap dpll_mpu_ck_hw = { | |
449 | .hw = { | |
450 | .clk = &dpll_mpu_ck, | |
451 | }, | |
452 | .dpll_data = &dpll_mpu_dd, | |
453 | .ops = &clkhwops_omap3_dpll, | |
454 | }; | |
455 | ||
b8675e2c | 456 | DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops); |
cb26867e RN |
457 | |
458 | DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); | |
459 | ||
460 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, | |
461 | OMAP4430_CM_DIV_M2_DPLL_MPU, | |
462 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
463 | ||
464 | DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", | |
465 | &dpll_abe_m3x2_ck, 0x0, 1, 2); | |
466 | ||
467 | static const char *per_hsd_byp_clk_mux_ck_parents[] = { | |
468 | "sys_clkin_ck", "per_hs_clk_div_ck", | |
469 | }; | |
470 | ||
471 | DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, | |
472 | 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, | |
473 | OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); | |
474 | ||
475 | /* DPLL_PER */ | |
476 | static struct dpll_data dpll_per_dd = { | |
477 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
478 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | |
479 | .clk_ref = &sys_clkin_ck, | |
480 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, | |
481 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
482 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | |
483 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | |
484 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
485 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
486 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
487 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
488 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
489 | .max_multiplier = 2047, | |
490 | .max_divider = 128, | |
491 | .min_divider = 1, | |
492 | }; | |
493 | ||
b8675e2c PW |
494 | static const char *dpll_per_ck_parents[] = { |
495 | "sys_clkin_ck", "per_hsd_byp_clk_mux_ck" | |
496 | }; | |
cb26867e RN |
497 | |
498 | static struct clk dpll_per_ck; | |
499 | ||
500 | static struct clk_hw_omap dpll_per_ck_hw = { | |
501 | .hw = { | |
502 | .clk = &dpll_per_ck, | |
503 | }, | |
504 | .dpll_data = &dpll_per_dd, | |
505 | .ops = &clkhwops_omap3_dpll, | |
506 | }; | |
507 | ||
b8675e2c | 508 | DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops); |
cb26867e RN |
509 | |
510 | DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, | |
511 | OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, | |
512 | OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); | |
513 | ||
514 | static const char *dpll_per_x2_ck_parents[] = { | |
515 | "dpll_per_ck", | |
516 | }; | |
517 | ||
518 | static struct clk dpll_per_x2_ck; | |
519 | ||
520 | static struct clk_hw_omap dpll_per_x2_ck_hw = { | |
521 | .hw = { | |
522 | .clk = &dpll_per_x2_ck, | |
523 | }, | |
524 | .flags = CLOCK_CLKOUTX2, | |
525 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
526 | .ops = &clkhwops_omap4_dpllmx, | |
527 | }; | |
528 | ||
529 | DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); | |
530 | ||
531 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
532 | 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, | |
533 | OMAP4430_DPLL_CLKOUT_DIV_MASK); | |
534 | ||
535 | static const char *dpll_per_m3x2_ck_parents[] = { | |
536 | "dpll_per_x2_ck", | |
537 | }; | |
538 | ||
539 | static const struct clksel dpll_per_m3x2_div[] = { | |
540 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | |
541 | { .parent = NULL }, | |
542 | }; | |
543 | ||
544 | /* XXX Missing round_rate, set_rate in ops */ | |
545 | DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, | |
546 | OMAP4430_CM_DIV_M3_DPLL_PER, | |
547 | OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
548 | OMAP4430_CM_DIV_M3_DPLL_PER, | |
549 | OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, | |
550 | dpll_per_m3x2_ck_parents, dmic_fck_ops); | |
551 | ||
552 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
553 | 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, | |
554 | OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); | |
555 | ||
556 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
557 | 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, | |
558 | OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); | |
559 | ||
560 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
561 | 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, | |
562 | OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); | |
563 | ||
564 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, | |
565 | 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, | |
566 | OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); | |
567 | ||
568 | DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", | |
569 | &dpll_abe_m3x2_ck, 0x0, 1, 3); | |
570 | ||
571 | /* DPLL_USB */ | |
572 | static struct dpll_data dpll_usb_dd = { | |
573 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | |
574 | .clk_bypass = &usb_hs_clk_div_ck, | |
575 | .flags = DPLL_J_TYPE, | |
576 | .clk_ref = &sys_clkin_ck, | |
577 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, | |
578 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
579 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | |
580 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | |
581 | .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, | |
582 | .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, | |
583 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
584 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
585 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
586 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, | |
587 | .max_multiplier = 4095, | |
588 | .max_divider = 256, | |
589 | .min_divider = 1, | |
590 | }; | |
591 | ||
b8675e2c PW |
592 | static const char *dpll_usb_ck_parents[] = { |
593 | "sys_clkin_ck", "usb_hs_clk_div_ck" | |
594 | }; | |
595 | ||
cb26867e RN |
596 | static struct clk dpll_usb_ck; |
597 | ||
598 | static struct clk_hw_omap dpll_usb_ck_hw = { | |
599 | .hw = { | |
600 | .clk = &dpll_usb_ck, | |
601 | }, | |
602 | .dpll_data = &dpll_usb_dd, | |
603 | .ops = &clkhwops_omap3_dpll, | |
604 | }; | |
605 | ||
b8675e2c | 606 | DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops); |
cb26867e RN |
607 | |
608 | static const char *dpll_usb_clkdcoldo_ck_parents[] = { | |
609 | "dpll_usb_ck", | |
610 | }; | |
611 | ||
612 | static struct clk dpll_usb_clkdcoldo_ck; | |
613 | ||
614 | static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { | |
615 | }; | |
616 | ||
617 | static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { | |
618 | .hw = { | |
619 | .clk = &dpll_usb_clkdcoldo_ck, | |
620 | }, | |
621 | .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, | |
622 | .ops = &clkhwops_omap4_dpllmx, | |
623 | }; | |
624 | ||
625 | DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, | |
626 | dpll_usb_clkdcoldo_ck_ops); | |
627 | ||
628 | DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, | |
629 | OMAP4430_CM_DIV_M2_DPLL_USB, | |
630 | OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); | |
631 | ||
632 | static const char *ducati_clk_mux_ck_parents[] = { | |
633 | "div_core_ck", "dpll_per_m6x2_ck", | |
634 | }; | |
635 | ||
636 | DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, | |
637 | OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, | |
638 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
639 | ||
640 | DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
641 | 0x0, 1, 16); | |
642 | ||
643 | DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, | |
644 | 1, 4); | |
645 | ||
646 | DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
647 | 0x0, 1, 8); | |
648 | ||
649 | static const struct clk_div_table func_48m_fclk_rates[] = { | |
650 | { .div = 4, .val = 0 }, | |
651 | { .div = 8, .val = 1 }, | |
652 | { .div = 0 }, | |
653 | }; | |
654 | DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
655 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
656 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, | |
657 | NULL); | |
658 | ||
659 | DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
660 | 0x0, 1, 4); | |
661 | ||
662 | static const struct clk_div_table func_64m_fclk_rates[] = { | |
663 | { .div = 2, .val = 0 }, | |
664 | { .div = 4, .val = 1 }, | |
665 | { .div = 0 }, | |
666 | }; | |
667 | DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, | |
668 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
669 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, | |
670 | NULL); | |
671 | ||
672 | static const struct clk_div_table func_96m_fclk_rates[] = { | |
673 | { .div = 2, .val = 0 }, | |
674 | { .div = 4, .val = 1 }, | |
675 | { .div = 0 }, | |
676 | }; | |
677 | DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, | |
678 | 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
679 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, | |
680 | NULL); | |
681 | ||
682 | static const struct clk_div_table init_60m_fclk_rates[] = { | |
683 | { .div = 1, .val = 0 }, | |
684 | { .div = 8, .val = 1 }, | |
685 | { .div = 0 }, | |
686 | }; | |
687 | DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, | |
688 | 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, | |
689 | OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, | |
690 | 0x0, init_60m_fclk_rates, NULL); | |
691 | ||
692 | DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, | |
693 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, | |
694 | OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); | |
695 | ||
696 | DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, | |
697 | OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, | |
698 | OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); | |
699 | ||
700 | DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, | |
701 | 0x0, 1, 16); | |
702 | ||
703 | static const char *l4_wkup_clk_mux_ck_parents[] = { | |
704 | "sys_clkin_ck", "lp_clk_div_ck", | |
705 | }; | |
706 | ||
707 | DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, | |
708 | OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
709 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
710 | ||
711 | static const struct clk_div_table ocp_abe_iclk_rates[] = { | |
712 | { .div = 2, .val = 0 }, | |
713 | { .div = 1, .val = 1 }, | |
714 | { .div = 0 }, | |
715 | }; | |
716 | DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, | |
717 | OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
718 | OMAP4430_CLKSEL_AESS_FCLK_SHIFT, | |
719 | OMAP4430_CLKSEL_AESS_FCLK_WIDTH, | |
720 | 0x0, ocp_abe_iclk_rates, NULL); | |
721 | ||
722 | DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, | |
723 | 0x0, 1, 4); | |
724 | ||
725 | DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, | |
726 | OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, | |
727 | OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); | |
728 | ||
729 | DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, | |
730 | OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, | |
731 | OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); | |
732 | ||
b8675e2c PW |
733 | static const char *dbgclk_mux_ck_parents[] = { |
734 | "sys_clkin_ck" | |
735 | }; | |
736 | ||
cb26867e RN |
737 | static struct clk dbgclk_mux_ck; |
738 | DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); | |
b8675e2c | 739 | DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents, |
cb26867e RN |
740 | dpll_usb_clkdcoldo_ck_ops); |
741 | ||
742 | /* Leaf clocks controlled by modules */ | |
743 | ||
744 | DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
745 | OMAP4430_CM_L4SEC_AES1_CLKCTRL, | |
746 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
747 | ||
748 | DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
749 | OMAP4430_CM_L4SEC_AES2_CLKCTRL, | |
750 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
751 | ||
752 | DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, | |
753 | OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
754 | 0x0, NULL); | |
755 | ||
756 | DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
757 | OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
758 | OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); | |
759 | ||
760 | static const struct clk_div_table div_ts_ck_rates[] = { | |
761 | { .div = 8, .val = 0 }, | |
762 | { .div = 16, .val = 1 }, | |
763 | { .div = 32, .val = 2 }, | |
764 | { .div = 0 }, | |
765 | }; | |
766 | DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
767 | 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
768 | OMAP4430_CLKSEL_24_25_SHIFT, | |
769 | OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, | |
770 | NULL); | |
771 | ||
772 | DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, | |
773 | OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
774 | OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, | |
775 | 0x0, NULL); | |
776 | ||
777 | DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, | |
778 | OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | |
779 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
780 | 0x0, NULL); | |
781 | ||
782 | static const char *dmic_sync_mux_ck_parents[] = { | |
783 | "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", | |
784 | }; | |
785 | ||
786 | DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, | |
787 | 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
788 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
789 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
790 | ||
791 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | |
792 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | |
793 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
794 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
795 | { .parent = NULL }, | |
796 | }; | |
797 | ||
798 | static const char *dmic_fck_parents[] = { | |
799 | "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", | |
800 | }; | |
801 | ||
802 | /* Merged func_dmic_abe_gfclk into dmic */ | |
803 | static struct clk dmic_fck; | |
804 | ||
805 | DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, | |
806 | OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
807 | OMAP4430_CLKSEL_SOURCE_MASK, | |
808 | OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
809 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
810 | dmic_fck_parents, dmic_fck_ops); | |
811 | ||
812 | DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, | |
813 | OMAP4430_CM_TESLA_TESLA_CLKCTRL, | |
814 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
815 | ||
816 | DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, | |
817 | OMAP4430_CM_DSS_DSS_CLKCTRL, | |
818 | OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); | |
819 | ||
820 | DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, | |
821 | OMAP4430_CM_DSS_DSS_CLKCTRL, | |
822 | OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); | |
823 | ||
824 | DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, | |
825 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | |
826 | 0x0, NULL); | |
827 | ||
828 | DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, | |
829 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, | |
830 | 0x0, NULL); | |
831 | ||
832 | DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
833 | OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
834 | 0x0, NULL); | |
835 | ||
836 | DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, | |
837 | OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, | |
838 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
839 | ||
840 | DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, | |
841 | OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | |
842 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
843 | ||
844 | DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, | |
845 | OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | |
846 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
847 | ||
848 | DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, | |
849 | OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, | |
850 | OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); | |
851 | ||
852 | DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, | |
853 | OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, | |
854 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
855 | ||
856 | DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
857 | OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
858 | OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); | |
859 | ||
860 | DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, | |
861 | OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
862 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
863 | ||
864 | DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
865 | OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
866 | 0x0, NULL); | |
867 | ||
868 | DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
869 | OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
870 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
871 | ||
872 | DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
873 | OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
874 | OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); | |
875 | ||
876 | DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
877 | OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
878 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
879 | ||
880 | DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
881 | OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
882 | 0x0, NULL); | |
883 | ||
884 | DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
885 | OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
886 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
887 | ||
888 | DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
889 | OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
890 | 0x0, NULL); | |
891 | ||
892 | DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
893 | OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
894 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
895 | ||
896 | DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, | |
897 | OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
898 | 0x0, NULL); | |
899 | ||
900 | DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
901 | OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
902 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
903 | ||
904 | DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, | |
905 | OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
906 | 0x0, NULL); | |
907 | ||
908 | static const struct clksel sgx_clk_mux_sel[] = { | |
909 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, | |
910 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, | |
911 | { .parent = NULL }, | |
912 | }; | |
913 | ||
914 | static const char *gpu_fck_parents[] = { | |
915 | "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", | |
916 | }; | |
917 | ||
918 | /* Merged sgx_clk_mux into gpu */ | |
919 | DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, | |
920 | OMAP4430_CM_GFX_GFX_CLKCTRL, | |
921 | OMAP4430_CLKSEL_SGX_FCLK_MASK, | |
922 | OMAP4430_CM_GFX_GFX_CLKCTRL, | |
923 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
924 | gpu_fck_parents, dmic_fck_ops); | |
925 | ||
926 | DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, | |
927 | OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | |
928 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
929 | ||
930 | DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, | |
931 | OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, | |
932 | OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | |
933 | NULL); | |
934 | ||
935 | DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, | |
936 | OMAP4430_CM_L4PER_I2C1_CLKCTRL, | |
937 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
938 | ||
939 | DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, | |
940 | OMAP4430_CM_L4PER_I2C2_CLKCTRL, | |
941 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
942 | ||
943 | DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, | |
944 | OMAP4430_CM_L4PER_I2C3_CLKCTRL, | |
945 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
946 | ||
947 | DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, | |
948 | OMAP4430_CM_L4PER_I2C4_CLKCTRL, | |
949 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
950 | ||
951 | DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, | |
952 | OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | |
953 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
954 | ||
955 | DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, | |
956 | OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, | |
957 | 0x0, NULL); | |
958 | ||
959 | DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, | |
960 | OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
961 | 0x0, NULL); | |
962 | ||
963 | DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, | |
964 | OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | |
965 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
966 | ||
967 | DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, | |
968 | OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | |
969 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
970 | ||
971 | static struct clk l3_instr_ick; | |
972 | ||
973 | static const char *l3_instr_ick_parent_names[] = { | |
974 | "l3_div_ck", | |
975 | }; | |
976 | ||
977 | static const struct clk_ops l3_instr_ick_ops = { | |
978 | .enable = &omap2_dflt_clk_enable, | |
979 | .disable = &omap2_dflt_clk_disable, | |
980 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
981 | .init = &omap2_init_clk_clkdm, | |
982 | }; | |
983 | ||
984 | static struct clk_hw_omap l3_instr_ick_hw = { | |
985 | .hw = { | |
986 | .clk = &l3_instr_ick, | |
987 | }, | |
988 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | |
989 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
990 | .clkdm_name = "l3_instr_clkdm", | |
991 | }; | |
992 | ||
993 | DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); | |
994 | ||
995 | static struct clk l3_main_3_ick; | |
996 | static struct clk_hw_omap l3_main_3_ick_hw = { | |
997 | .hw = { | |
998 | .clk = &l3_main_3_ick, | |
999 | }, | |
1000 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | |
1001 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
1002 | .clkdm_name = "l3_instr_clkdm", | |
1003 | }; | |
1004 | ||
1005 | DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); | |
1006 | ||
1007 | DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
1008 | OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1009 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
1010 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
1011 | ||
1012 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |
1013 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | |
1014 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1015 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1016 | { .parent = NULL }, | |
1017 | }; | |
1018 | ||
1019 | static const char *mcasp_fck_parents[] = { | |
1020 | "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", | |
1021 | }; | |
1022 | ||
1023 | /* Merged func_mcasp_abe_gfclk into mcasp */ | |
1024 | DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, | |
1025 | OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1026 | OMAP4430_CLKSEL_SOURCE_MASK, | |
1027 | OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1028 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1029 | mcasp_fck_parents, dmic_fck_ops); | |
1030 | ||
1031 | DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
1032 | OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1033 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
1034 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
1035 | ||
1036 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | |
1037 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | |
1038 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1039 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1040 | { .parent = NULL }, | |
1041 | }; | |
1042 | ||
1043 | static const char *mcbsp1_fck_parents[] = { | |
1044 | "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", | |
1045 | }; | |
1046 | ||
1047 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ | |
1048 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, | |
1049 | OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1050 | OMAP4430_CLKSEL_SOURCE_MASK, | |
1051 | OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1052 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1053 | mcbsp1_fck_parents, dmic_fck_ops); | |
1054 | ||
1055 | DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
1056 | OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1057 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
1058 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
1059 | ||
1060 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | |
1061 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | |
1062 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1063 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1064 | { .parent = NULL }, | |
1065 | }; | |
1066 | ||
1067 | static const char *mcbsp2_fck_parents[] = { | |
1068 | "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", | |
1069 | }; | |
1070 | ||
1071 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ | |
1072 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, | |
1073 | OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1074 | OMAP4430_CLKSEL_SOURCE_MASK, | |
1075 | OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1076 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1077 | mcbsp2_fck_parents, dmic_fck_ops); | |
1078 | ||
1079 | DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, | |
1080 | OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1081 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
1082 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
1083 | ||
1084 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | |
1085 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | |
1086 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1087 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1088 | { .parent = NULL }, | |
1089 | }; | |
1090 | ||
1091 | static const char *mcbsp3_fck_parents[] = { | |
1092 | "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", | |
1093 | }; | |
1094 | ||
1095 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ | |
1096 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, | |
1097 | OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1098 | OMAP4430_CLKSEL_SOURCE_MASK, | |
1099 | OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1100 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1101 | mcbsp3_fck_parents, dmic_fck_ops); | |
1102 | ||
1103 | static const char *mcbsp4_sync_mux_ck_parents[] = { | |
1104 | "func_96m_fclk", "per_abe_nc_fclk", | |
1105 | }; | |
1106 | ||
1107 | DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, | |
1108 | OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1109 | OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, | |
1110 | OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); | |
1111 | ||
1112 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | |
1113 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | |
1114 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1115 | { .parent = NULL }, | |
1116 | }; | |
1117 | ||
1118 | static const char *mcbsp4_fck_parents[] = { | |
1119 | "mcbsp4_sync_mux_ck", "pad_clks_ck", | |
1120 | }; | |
1121 | ||
1122 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ | |
1123 | DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, | |
1124 | OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1125 | OMAP4430_CLKSEL_SOURCE_24_24_MASK, | |
1126 | OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1127 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1128 | mcbsp4_fck_parents, dmic_fck_ops); | |
1129 | ||
1130 | DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, | |
1131 | OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
1132 | 0x0, NULL); | |
1133 | ||
1134 | DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1135 | OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | |
1136 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1137 | ||
1138 | DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1139 | OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | |
1140 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1141 | ||
1142 | DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1143 | OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | |
1144 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1145 | ||
1146 | DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1147 | OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | |
1148 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1149 | ||
1150 | static const struct clksel hsmmc1_fclk_sel[] = { | |
1151 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | |
1152 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | |
1153 | { .parent = NULL }, | |
1154 | }; | |
1155 | ||
1156 | static const char *mmc1_fck_parents[] = { | |
1157 | "func_64m_fclk", "func_96m_fclk", | |
1158 | }; | |
1159 | ||
1160 | /* Merged hsmmc1_fclk into mmc1 */ | |
1161 | DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, | |
1162 | OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1163 | OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | |
1164 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1165 | mmc1_fck_parents, dmic_fck_ops); | |
1166 | ||
1167 | /* Merged hsmmc2_fclk into mmc2 */ | |
1168 | DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, | |
1169 | OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1170 | OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | |
1171 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1172 | mmc1_fck_parents, dmic_fck_ops); | |
1173 | ||
1174 | DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1175 | OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | |
1176 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1177 | ||
1178 | DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1179 | OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | |
1180 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1181 | ||
1182 | DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1183 | OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | |
1184 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1185 | ||
1186 | DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1187 | OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
1188 | OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); | |
1189 | ||
1190 | DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
1191 | OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
1192 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
1193 | ||
1194 | static struct clk ocp_wp_noc_ick; | |
1195 | ||
1196 | static struct clk_hw_omap ocp_wp_noc_ick_hw = { | |
1197 | .hw = { | |
1198 | .clk = &ocp_wp_noc_ick, | |
1199 | }, | |
1200 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | |
1201 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
1202 | .clkdm_name = "l3_instr_clkdm", | |
1203 | }; | |
1204 | ||
1205 | DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); | |
1206 | ||
1207 | DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
1208 | OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
1209 | 0x0, NULL); | |
1210 | ||
1211 | DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, | |
1212 | OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | |
1213 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1214 | ||
1215 | DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, | |
1216 | OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
1217 | 0x0, NULL); | |
1218 | ||
1219 | DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, | |
1220 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1221 | OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); | |
1222 | ||
1223 | DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, | |
1224 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1225 | OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); | |
1226 | ||
1227 | DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, | |
1228 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1229 | OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); | |
1230 | ||
1231 | DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, | |
1232 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1233 | OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); | |
1234 | ||
1235 | DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, | |
1236 | OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
1237 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1238 | ||
1239 | DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, | |
1240 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1241 | OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); | |
1242 | ||
1243 | DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, | |
1244 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1245 | OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); | |
1246 | ||
1247 | DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", | |
1248 | &pad_slimbus_core_clks_ck, 0x0, | |
1249 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1250 | OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); | |
1251 | ||
1252 | DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, | |
1253 | OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
1254 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1255 | ||
1256 | DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
1257 | 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
1258 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1259 | ||
1260 | DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
1261 | 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
1262 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1263 | ||
1264 | DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, | |
1265 | 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
1266 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1267 | ||
1268 | static const struct clksel dmt1_clk_mux_sel[] = { | |
1269 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1270 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
1271 | { .parent = NULL }, | |
1272 | }; | |
1273 | ||
1274 | /* Merged dmt1_clk_mux into timer1 */ | |
1275 | DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, | |
1276 | OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1277 | OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
1278 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1279 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1280 | ||
1281 | /* Merged cm2_dm10_mux into timer10 */ | |
1282 | DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1283 | OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
1284 | OMAP4430_CLKSEL_MASK, | |
1285 | OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
1286 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1287 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1288 | ||
1289 | /* Merged cm2_dm11_mux into timer11 */ | |
1290 | DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1291 | OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
1292 | OMAP4430_CLKSEL_MASK, | |
1293 | OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
1294 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1295 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1296 | ||
1297 | /* Merged cm2_dm2_mux into timer2 */ | |
1298 | DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1299 | OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
1300 | OMAP4430_CLKSEL_MASK, | |
1301 | OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
1302 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1303 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1304 | ||
1305 | /* Merged cm2_dm3_mux into timer3 */ | |
1306 | DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1307 | OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
1308 | OMAP4430_CLKSEL_MASK, | |
1309 | OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
1310 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1311 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1312 | ||
1313 | /* Merged cm2_dm4_mux into timer4 */ | |
1314 | DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1315 | OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
1316 | OMAP4430_CLKSEL_MASK, | |
1317 | OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
1318 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1319 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1320 | ||
1321 | static const struct clksel timer5_sync_mux_sel[] = { | |
1322 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | |
1323 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
1324 | { .parent = NULL }, | |
1325 | }; | |
1326 | ||
1327 | static const char *timer5_fck_parents[] = { | |
1328 | "syc_clk_div_ck", "sys_32k_ck", | |
1329 | }; | |
1330 | ||
1331 | /* Merged timer5_sync_mux into timer5 */ | |
1332 | DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, | |
1333 | OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1334 | OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
1335 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1336 | timer5_fck_parents, dmic_fck_ops); | |
1337 | ||
1338 | /* Merged timer6_sync_mux into timer6 */ | |
1339 | DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, | |
1340 | OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1341 | OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
1342 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1343 | timer5_fck_parents, dmic_fck_ops); | |
1344 | ||
1345 | /* Merged timer7_sync_mux into timer7 */ | |
1346 | DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, | |
1347 | OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1348 | OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
1349 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1350 | timer5_fck_parents, dmic_fck_ops); | |
1351 | ||
1352 | /* Merged timer8_sync_mux into timer8 */ | |
1353 | DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, | |
1354 | OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, | |
1355 | OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
1356 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1357 | timer5_fck_parents, dmic_fck_ops); | |
1358 | ||
1359 | /* Merged cm2_dm9_mux into timer9 */ | |
1360 | DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, | |
1361 | OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
1362 | OMAP4430_CLKSEL_MASK, | |
1363 | OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
1364 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, | |
1365 | abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); | |
1366 | ||
1367 | DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1368 | OMAP4430_CM_L4PER_UART1_CLKCTRL, | |
1369 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1370 | ||
1371 | DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1372 | OMAP4430_CM_L4PER_UART2_CLKCTRL, | |
1373 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1374 | ||
1375 | DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1376 | OMAP4430_CM_L4PER_UART3_CLKCTRL, | |
1377 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1378 | ||
1379 | DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, | |
1380 | OMAP4430_CM_L4PER_UART4_CLKCTRL, | |
1381 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1382 | ||
1383 | static struct clk usb_host_fs_fck; | |
1384 | ||
1385 | static const char *usb_host_fs_fck_parent_names[] = { | |
1386 | "func_48mc_fclk", | |
1387 | }; | |
1388 | ||
1389 | static const struct clk_ops usb_host_fs_fck_ops = { | |
1390 | .enable = &omap2_dflt_clk_enable, | |
1391 | .disable = &omap2_dflt_clk_disable, | |
1392 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
1393 | }; | |
1394 | ||
1395 | static struct clk_hw_omap usb_host_fs_fck_hw = { | |
1396 | .hw = { | |
1397 | .clk = &usb_host_fs_fck, | |
1398 | }, | |
1399 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, | |
1400 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
1401 | .clkdm_name = "l3_init_clkdm", | |
1402 | }; | |
1403 | ||
1404 | DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, | |
1405 | usb_host_fs_fck_ops); | |
1406 | ||
1407 | static const char *utmi_p1_gfclk_parents[] = { | |
1408 | "init_60m_fclk", "xclk60mhsp1_ck", | |
1409 | }; | |
1410 | ||
1411 | DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, | |
1412 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1413 | OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, | |
1414 | 0x0, NULL); | |
1415 | ||
1416 | DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, | |
1417 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1418 | OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); | |
1419 | ||
1420 | static const char *utmi_p2_gfclk_parents[] = { | |
1421 | "init_60m_fclk", "xclk60mhsp2_ck", | |
1422 | }; | |
1423 | ||
1424 | DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, | |
1425 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1426 | OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, | |
1427 | 0x0, NULL); | |
1428 | ||
1429 | DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, | |
1430 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1431 | OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); | |
1432 | ||
1433 | DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1434 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1435 | OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); | |
1436 | ||
1437 | DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", | |
1438 | &dpll_usb_m2_ck, 0x0, | |
1439 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1440 | OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); | |
1441 | ||
1442 | DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", | |
1443 | &init_60m_fclk, 0x0, | |
1444 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1445 | OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); | |
1446 | ||
1447 | DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", | |
1448 | &init_60m_fclk, 0x0, | |
1449 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1450 | OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); | |
1451 | ||
1452 | DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", | |
1453 | &dpll_usb_m2_ck, 0x0, | |
1454 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1455 | OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); | |
1456 | ||
1457 | DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, | |
1458 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1459 | OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); | |
1460 | ||
1461 | DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1462 | OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
1463 | OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); | |
1464 | ||
1465 | static const char *otg_60m_gfclk_parents[] = { | |
1466 | "utmi_phy_clkout_ck", "xclk60motg_ck", | |
1467 | }; | |
1468 | ||
1469 | DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, | |
1470 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, | |
1471 | OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); | |
1472 | ||
1473 | DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, | |
1474 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
1475 | OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); | |
1476 | ||
1477 | DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, | |
1478 | OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
1479 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
1480 | ||
1481 | DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, | |
1482 | OMAP4430_CM_ALWON_USBPHY_CLKCTRL, | |
1483 | OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); | |
1484 | ||
1485 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1486 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1487 | OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); | |
1488 | ||
1489 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1490 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1491 | OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); | |
1492 | ||
1493 | DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, | |
1494 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1495 | OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); | |
1496 | ||
1497 | DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, | |
1498 | OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
1499 | OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); | |
1500 | ||
1501 | static const struct clk_div_table usim_ck_rates[] = { | |
1502 | { .div = 14, .val = 0 }, | |
1503 | { .div = 18, .val = 1 }, | |
1504 | { .div = 0 }, | |
1505 | }; | |
1506 | DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, | |
1507 | OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
1508 | OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, | |
1509 | 0x0, usim_ck_rates, NULL); | |
1510 | ||
1511 | DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, | |
1512 | OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, | |
1513 | 0x0, NULL); | |
1514 | ||
1515 | DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, | |
1516 | OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, | |
1517 | 0x0, NULL); | |
1518 | ||
1519 | DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, | |
1520 | OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
1521 | 0x0, NULL); | |
1522 | ||
1523 | DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, | |
1524 | OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, | |
1525 | 0x0, NULL); | |
1526 | ||
1527 | /* Remaining optional clocks */ | |
1528 | static const char *pmd_stm_clock_mux_ck_parents[] = { | |
1529 | "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", | |
1530 | }; | |
1531 | ||
1532 | DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, | |
1533 | OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, | |
1534 | OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); | |
1535 | ||
1536 | DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, | |
1537 | OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1538 | OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, | |
1539 | OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); | |
1540 | ||
1541 | DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", | |
1542 | &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1543 | OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, | |
1544 | OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | |
1545 | NULL); | |
1546 | ||
1547 | static const char *trace_clk_div_ck_parents[] = { | |
1548 | "pmd_trace_clk_mux_ck", | |
1549 | }; | |
1550 | ||
1551 | static const struct clksel trace_clk_div_div[] = { | |
1552 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | |
1553 | { .parent = NULL }, | |
1554 | }; | |
1555 | ||
1556 | static struct clk trace_clk_div_ck; | |
1557 | ||
1558 | static const struct clk_ops trace_clk_div_ck_ops = { | |
1559 | .recalc_rate = &omap2_clksel_recalc, | |
1560 | .set_rate = &omap2_clksel_set_rate, | |
1561 | .round_rate = &omap2_clksel_round_rate, | |
1562 | .init = &omap2_init_clk_clkdm, | |
1563 | .enable = &omap2_clkops_enable_clkdm, | |
1564 | .disable = &omap2_clkops_disable_clkdm, | |
1565 | }; | |
1566 | ||
1567 | static struct clk_hw_omap trace_clk_div_ck_hw = { | |
1568 | .hw = { | |
1569 | .clk = &trace_clk_div_ck, | |
1570 | }, | |
1571 | .clkdm_name = "emu_sys_clkdm", | |
1572 | .clksel = trace_clk_div_div, | |
1573 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
1574 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | |
1575 | }; | |
1576 | ||
1577 | DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, | |
1578 | trace_clk_div_ck_ops); | |
1579 | ||
1580 | /* SCRM aux clk nodes */ | |
1581 | ||
1582 | static const struct clksel auxclk_src_sel[] = { | |
1583 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1584 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, | |
1585 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, | |
1586 | { .parent = NULL }, | |
1587 | }; | |
1588 | ||
1589 | static const char *auxclk_src_ck_parents[] = { | |
1590 | "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", | |
1591 | }; | |
1592 | ||
1593 | static const struct clk_ops auxclk_src_ck_ops = { | |
1594 | .enable = &omap2_dflt_clk_enable, | |
1595 | .disable = &omap2_dflt_clk_disable, | |
1596 | .is_enabled = &omap2_dflt_clk_is_enabled, | |
1597 | .recalc_rate = &omap2_clksel_recalc, | |
1598 | .get_parent = &omap2_clksel_find_parent_index, | |
1599 | }; | |
1600 | ||
1601 | DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, | |
1602 | OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, | |
1603 | OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, | |
1604 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1605 | ||
1606 | DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, | |
1607 | OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1608 | 0x0, NULL); | |
1609 | ||
1610 | DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, | |
1611 | OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, | |
1612 | OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, | |
1613 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1614 | ||
1615 | DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, | |
1616 | OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1617 | 0x0, NULL); | |
1618 | ||
1619 | DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, | |
1620 | OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, | |
1621 | OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, | |
1622 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1623 | ||
1624 | DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, | |
1625 | OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1626 | 0x0, NULL); | |
1627 | ||
1628 | DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, | |
1629 | OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, | |
1630 | OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, | |
1631 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1632 | ||
1633 | DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, | |
1634 | OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1635 | 0x0, NULL); | |
1636 | ||
1637 | DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, | |
1638 | OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, | |
1639 | OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, | |
1640 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1641 | ||
1642 | DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, | |
1643 | OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1644 | 0x0, NULL); | |
1645 | ||
1646 | DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, | |
1647 | OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, | |
1648 | OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, | |
1649 | auxclk_src_ck_parents, auxclk_src_ck_ops); | |
1650 | ||
1651 | DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, | |
1652 | OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, | |
1653 | 0x0, NULL); | |
1654 | ||
1655 | static const char *auxclkreq_ck_parents[] = { | |
1656 | "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", | |
1657 | "auxclk5_ck", | |
1658 | }; | |
1659 | ||
1660 | DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1661 | OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1662 | 0x0, NULL); | |
1663 | ||
1664 | DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1665 | OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1666 | 0x0, NULL); | |
1667 | ||
1668 | DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1669 | OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1670 | 0x0, NULL); | |
1671 | ||
1672 | DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1673 | OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1674 | 0x0, NULL); | |
1675 | ||
1676 | DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1677 | OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1678 | 0x0, NULL); | |
1679 | ||
1680 | DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, | |
1681 | OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, | |
1682 | 0x0, NULL); | |
1683 | ||
1684 | /* | |
1685 | * clkdev | |
1686 | */ | |
1687 | ||
1688 | static struct omap_clk omap44xx_clks[] = { | |
1689 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | |
1690 | CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), | |
1691 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | |
1692 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | |
1693 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | |
1694 | CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), | |
1695 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | |
1696 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | |
1697 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | |
1698 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | |
1699 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | |
1700 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | |
1701 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | |
1702 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | |
1703 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | |
1704 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | |
1705 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), | |
1706 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), | |
1707 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | |
1708 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | |
1709 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | |
1710 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), | |
1711 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), | |
1712 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | |
1713 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), | |
1714 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), | |
1715 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | |
1716 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | |
1717 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | |
1718 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), | |
1719 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), | |
1720 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | |
1721 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), | |
1722 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | |
1723 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), | |
1724 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | |
1725 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | |
1726 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), | |
1727 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), | |
1728 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | |
1729 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | |
1730 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), | |
1731 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), | |
1732 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | |
1733 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), | |
1734 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), | |
1735 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), | |
1736 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | |
1737 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), | |
1738 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), | |
1739 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | |
1740 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), | |
1741 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | |
1742 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | |
1743 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | |
1744 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | |
1745 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | |
1746 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), | |
1747 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), | |
1748 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), | |
1749 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), | |
1750 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), | |
1751 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), | |
1752 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), | |
1753 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | |
1754 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | |
1755 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | |
1756 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | |
1757 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | |
1758 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | |
1759 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | |
1760 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | |
1761 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | |
1762 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | |
1763 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | |
1764 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | |
1765 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), | |
1766 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | |
1767 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | |
1768 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | |
1769 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | |
1770 | CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), | |
1771 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), | |
1772 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | |
1773 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), | |
1774 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | |
1775 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), | |
1776 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), | |
1777 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), | |
1778 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), | |
1779 | CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), | |
1780 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), | |
1781 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), | |
1782 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), | |
1783 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), | |
1784 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), | |
1785 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), | |
1786 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), | |
1787 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), | |
1788 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), | |
1789 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), | |
1790 | CLK("omapdss_dss", "ick", &dss_fck, CK_443X), | |
1791 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), | |
1792 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), | |
1793 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), | |
1794 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), | |
1795 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), | |
1796 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), | |
1797 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), | |
1798 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), | |
1799 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), | |
1800 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), | |
1801 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), | |
1802 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), | |
1803 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), | |
1804 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), | |
1805 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), | |
1806 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), | |
1807 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), | |
1808 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), | |
1809 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), | |
1810 | CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), | |
1811 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), | |
1812 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), | |
1813 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), | |
1814 | CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), | |
1815 | CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), | |
1816 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), | |
1817 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), | |
1818 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), | |
1819 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), | |
1820 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), | |
1821 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), | |
1822 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), | |
1823 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), | |
1824 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), | |
1825 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), | |
1826 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), | |
1827 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), | |
1828 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), | |
1829 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), | |
1830 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), | |
1831 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), | |
1832 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), | |
1833 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), | |
1834 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), | |
1835 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), | |
1836 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), | |
1837 | CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), | |
1838 | CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), | |
1839 | CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), | |
1840 | CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), | |
1841 | CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), | |
1842 | CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), | |
1843 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), | |
1844 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), | |
1845 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), | |
1846 | CLK(NULL, "rng_ick", &rng_ick, CK_443X), | |
1847 | CLK("omap_rng", "ick", &rng_ick, CK_443X), | |
1848 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), | |
1849 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), | |
1850 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), | |
1851 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | |
1852 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), | |
1853 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), | |
1854 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), | |
1855 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), | |
1856 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), | |
1857 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), | |
1858 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), | |
1859 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), | |
1860 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), | |
1861 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), | |
1862 | CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), | |
1863 | CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), | |
1864 | CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), | |
1865 | CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), | |
1866 | CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), | |
1867 | CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), | |
1868 | CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), | |
1869 | CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), | |
1870 | CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), | |
1871 | CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), | |
1872 | CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), | |
1873 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), | |
1874 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), | |
1875 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), | |
1876 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), | |
1877 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), | |
1878 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), | |
1879 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), | |
1880 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | |
1881 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | |
1882 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | |
1883 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), | |
1884 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), | |
1885 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), | |
1886 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | |
1887 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), | |
1888 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | |
1889 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), | |
1890 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), | |
1891 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), | |
1892 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | |
1893 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), | |
1894 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), | |
1895 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), | |
1896 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), | |
1897 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | |
1898 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | |
1899 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), | |
1900 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), | |
1901 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), | |
1902 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | |
1903 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | |
1904 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), | |
1905 | CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), | |
1906 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), | |
1907 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | |
1908 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | |
1909 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | |
1910 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | |
1911 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), | |
1912 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), | |
1913 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), | |
1914 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), | |
1915 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), | |
1916 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), | |
1917 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), | |
1918 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), | |
1919 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), | |
1920 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), | |
1921 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), | |
1922 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), | |
1923 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), | |
1924 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), | |
1925 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), | |
1926 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), | |
1927 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), | |
1928 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), | |
1929 | CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), | |
1930 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), | |
1931 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), | |
1932 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), | |
1933 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), | |
1934 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), | |
1935 | CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), | |
1936 | CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), | |
1937 | CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), | |
1938 | CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), | |
1939 | CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), | |
1940 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), | |
1941 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | |
1942 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | |
1943 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | |
1944 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), | |
1945 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), | |
1946 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), | |
1947 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), | |
1948 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), | |
1949 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | |
1950 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | |
1951 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | |
1952 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), | |
1953 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), | |
1954 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), | |
1955 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | |
1956 | CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), | |
1957 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ | |
1958 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1959 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1960 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1961 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1962 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1963 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1964 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1965 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1966 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1967 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1968 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1969 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1970 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1971 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1972 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1973 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1974 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
1975 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
ba68c7ef JH |
1976 | CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), |
1977 | CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1978 | CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
1979 | CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
cb26867e RN |
1980 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), |
1981 | }; | |
1982 | ||
1983 | static const char *enable_init_clks[] = { | |
1984 | "emif1_fck", | |
1985 | "emif2_fck", | |
1986 | "gpmc_ick", | |
1987 | "l3_instr_ick", | |
1988 | "l3_main_3_ick", | |
1989 | "ocp_wp_noc_ick", | |
1990 | }; | |
1991 | ||
1992 | int __init omap4xxx_clk_init(void) | |
1993 | { | |
1994 | u32 cpu_clkflg; | |
1995 | struct omap_clk *c; | |
8c197ccf | 1996 | int rc; |
cb26867e RN |
1997 | |
1998 | if (cpu_is_omap443x()) { | |
1999 | cpu_mask = RATE_IN_4430; | |
2000 | cpu_clkflg = CK_443X; | |
2001 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { | |
2002 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; | |
2003 | cpu_clkflg = CK_446X | CK_443X; | |
2004 | ||
2005 | if (cpu_is_omap447x()) | |
2006 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); | |
2007 | } else { | |
2008 | return 0; | |
2009 | } | |
2010 | ||
2011 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
2012 | c++) { | |
2013 | if (c->cpu & cpu_clkflg) { | |
2014 | clkdev_add(&c->lk); | |
2015 | if (!__clk_init(NULL, c->lk.clk)) | |
2016 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | |
2017 | } | |
2018 | } | |
2019 | ||
2020 | omap2_clk_disable_autoidle_all(); | |
2021 | ||
2022 | omap2_clk_enable_init_clocks(enable_init_clks, | |
2023 | ARRAY_SIZE(enable_init_clks)); | |
2024 | ||
8c197ccf JH |
2025 | /* |
2026 | * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power | |
2027 | * state when turning the ABE clock domain. Workaround this by | |
2028 | * locking the ABE DPLL on boot. | |
2029 | */ | |
2030 | if (cpu_is_omap446x()) { | |
2031 | rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); | |
2032 | if (!rc) | |
2033 | rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); | |
2034 | if (rc) | |
2035 | pr_err("%s: failed to configure ABE DPLL!\n", __func__); | |
2036 | } | |
2037 | ||
cb26867e RN |
2038 | return 0; |
2039 | } |