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b1823d86 PW |
1 | /* |
2 | * DPLL + CORE_CLK composite clock functions | |
3 | * | |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | |
5 | * Copyright (C) 2004-2010 Nokia Corporation | |
6 | * | |
7 | * Contacts: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
10 | * | |
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | |
12 | * Gordon McNutt and RidgeRun, Inc. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | * | |
18 | * XXX The DPLL and CORE clocks should be split into two separate clock | |
19 | * types. | |
20 | */ | |
21 | #undef DEBUG | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/io.h> | |
27 | ||
622297fd | 28 | #include "../plat-omap/sram.h" |
b1823d86 PW |
29 | |
30 | #include "clock.h" | |
31 | #include "clock2xxx.h" | |
32 | #include "opp2xxx.h" | |
59fb659b | 33 | #include "cm2xxx_3xxx.h" |
b1823d86 | 34 | #include "cm-regbits-24xx.h" |
3e6ece13 | 35 | #include "sdrc.h" |
b1823d86 PW |
36 | |
37 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | |
38 | ||
39 | /** | |
40 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | |
41 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | |
42 | * | |
43 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | |
44 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | |
45 | * (the latter is unusual). This currently should be called with | |
46 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | |
47 | * core_ck. | |
48 | */ | |
49 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | |
50 | { | |
51 | long long core_clk; | |
52 | u32 v; | |
53 | ||
54 | core_clk = omap2_get_dpll_rate(clk); | |
55 | ||
c4d7e58f | 56 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
b1823d86 PW |
57 | v &= OMAP24XX_CORE_CLK_SRC_MASK; |
58 | ||
59 | if (v == CORE_CLK_SRC_32K) | |
60 | core_clk = 32768; | |
61 | else | |
62 | core_clk *= v; | |
63 | ||
64 | return core_clk; | |
65 | } | |
66 | ||
67 | /* | |
68 | * Uses the current prcm set to tell if a rate is valid. | |
69 | * You can go slower, but not faster within a given rate set. | |
70 | */ | |
71 | static long omap2_dpllcore_round_rate(unsigned long target_rate) | |
72 | { | |
73 | u32 high, low, core_clk_src; | |
74 | ||
c4d7e58f | 75 | core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
b1823d86 PW |
76 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; |
77 | ||
78 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | |
79 | high = curr_prcm_set->dpll_speed * 2; | |
80 | low = curr_prcm_set->dpll_speed; | |
81 | } else { /* DPLL clockout x 2 */ | |
82 | high = curr_prcm_set->dpll_speed; | |
83 | low = curr_prcm_set->dpll_speed / 2; | |
84 | } | |
85 | ||
86 | #ifdef DOWN_VARIABLE_DPLL | |
87 | if (target_rate > high) | |
88 | return high; | |
89 | else | |
90 | return target_rate; | |
91 | #else | |
92 | if (target_rate > low) | |
93 | return high; | |
94 | else | |
95 | return low; | |
96 | #endif | |
97 | ||
98 | } | |
99 | ||
100 | unsigned long omap2_dpllcore_recalc(struct clk *clk) | |
101 | { | |
102 | return omap2xxx_clk_get_core_rate(clk); | |
103 | } | |
104 | ||
105 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |
106 | { | |
107 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | |
108 | u32 bypass = 0; | |
109 | struct prcm_config tmpset; | |
110 | const struct dpll_data *dd; | |
111 | ||
112 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | |
c4d7e58f | 113 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
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114 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
115 | ||
116 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | |
117 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | |
118 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | |
119 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | |
120 | } else if (rate != cur_rate) { | |
121 | valid_rate = omap2_dpllcore_round_rate(rate); | |
122 | if (valid_rate != rate) | |
123 | return -EINVAL; | |
124 | ||
125 | if (mult == 1) | |
126 | low = curr_prcm_set->dpll_speed; | |
127 | else | |
128 | low = curr_prcm_set->dpll_speed / 2; | |
129 | ||
130 | dd = clk->dpll_data; | |
131 | if (!dd) | |
132 | return -EINVAL; | |
133 | ||
134 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | |
135 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | |
136 | dd->div1_mask); | |
137 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | |
c4d7e58f | 138 | tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
b1823d86 PW |
139 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
140 | if (rate > low) { | |
141 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | |
142 | mult = ((rate / 2) / 1000000); | |
143 | done_rate = CORE_CLK_SRC_DPLL_X2; | |
144 | } else { | |
145 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | |
146 | mult = (rate / 1000000); | |
147 | done_rate = CORE_CLK_SRC_DPLL; | |
148 | } | |
149 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | |
150 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | |
151 | ||
152 | /* Worst case */ | |
153 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | |
154 | ||
155 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | |
156 | bypass = 1; | |
157 | ||
158 | /* For omap2xxx_sdrc_init_params() */ | |
159 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | |
160 | ||
161 | /* Force dll lock mode */ | |
162 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | |
163 | bypass); | |
164 | ||
165 | /* Errata: ret dll entry state */ | |
166 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); | |
167 | omap2xxx_sdrc_reprogram(done_rate, 0); | |
168 | } | |
169 | ||
170 | return 0; | |
171 | } | |
172 |