[deliverable/linux.git] / arch / arm / mach-omap2 / clkt2xxx_dpllcore.c

/*
 * DPLL + CORE_CLK composite clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
 * Gordon McNutt and RidgeRun, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX The DPLL and CORE clocks should be split into two separate clock
 * types.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "../plat-omap/sram.h"

#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"

/* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */

/*
 * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
 */
static struct clk *dpll_core_ck;

/**
 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
 *
 * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
 * (the latter is unusual).  This currently should be called with
 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
 * core_ck.
 */
unsigned long omap2xxx_clk_get_core_rate(void)
{
	long long core_clk;
	u32 v;

	WARN_ON(!dpll_core_ck);

	core_clk = omap2_get_dpll_rate(dpll_core_ck);

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	v &= OMAP24XX_CORE_CLK_SRC_MASK;

	if (v == CORE_CLK_SRC_32K)
		core_clk = 32768;
	else
		core_clk *= v;

	return core_clk;
}

/*
 * Uses the current prcm set to tell if a rate is valid.
 * You can go slower, but not faster within a given rate set.
 */
static long omap2_dpllcore_round_rate(unsigned long target_rate)
{
	u32 high, low, core_clk_src;

	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;

	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
		high = curr_prcm_set->dpll_speed * 2;
		low = curr_prcm_set->dpll_speed;
	} else {				/* DPLL clockout x 2 */
		high = curr_prcm_set->dpll_speed;
		low = curr_prcm_set->dpll_speed / 2;
	}

#ifdef DOWN_VARIABLE_DPLL
	if (target_rate > high)
		return high;
	else
		return target_rate;
#else
	if (target_rate > low)
		return high;
	else
		return low;
#endif

}

unsigned long omap2_dpllcore_recalc(struct clk *clk)
{
	return omap2xxx_clk_get_core_rate();
}

int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
{
	u32 cur_rate, low, mult, div, valid_rate, done_rate;
	u32 bypass = 0;
	struct prcm_config tmpset;
	const struct dpll_data *dd;

	cur_rate = omap2xxx_clk_get_core_rate();
	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	mult &= OMAP24XX_CORE_CLK_SRC_MASK;

	if ((rate == (cur_rate / 2)) && (mult == 2)) {
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	} else if (rate != cur_rate) {
		valid_rate = omap2_dpllcore_round_rate(rate);
		if (valid_rate != rate)
			return -EINVAL;

		if (mult == 1)
			low = curr_prcm_set->dpll_speed;
		else
			low = curr_prcm_set->dpll_speed / 2;

		dd = clk->dpll_data;
		if (!dd)
			return -EINVAL;

		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
					   dd->div1_mask);
		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
		tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
		if (rate > low) {
			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
			mult = ((rate / 2) / 1000000);
			done_rate = CORE_CLK_SRC_DPLL_X2;
		} else {
			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
			mult = (rate / 1000000);
			done_rate = CORE_CLK_SRC_DPLL;
		}
		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));

		/* Worst case */
		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;

		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
			bypass = 1;

		/* For omap2xxx_sdrc_init_params() */
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);

		/* Force dll lock mode */
		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
			       bypass);

		/* Errata: ret dll entry state */
		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
		omap2xxx_sdrc_reprogram(done_rate, 0);
	}

	return 0;
}

/**
 * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
 * @clk: struct clk *dpll_ck
 *
 * Store a local copy of @clk in dpll_core_ck so other code can query
 * the core rate without having to clk_get(), which can sleep.  Must
 * only be called once.  No return value.  XXX If the clock
 * registration process is ever changed such that dpll_ck is no longer
 * statically defined, this code may need to change to increment some
 * kind of use count on dpll_ck.
 */
void omap2xxx_clkt_dpllcore_init(struct clk *clk)
{
	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
	dpll_core_ck = clk;
}
Commit	Line	Data
b1823d86 PW	1	/*
	2	* DPLL + CORE_CLK composite clock functions
	3	*
	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2010 Nokia Corporation
	6	*
	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
	10	*
	11	* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
	12	* Gordon McNutt and RidgeRun, Inc.
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*
	18	* XXX The DPLL and CORE clocks should be split into two separate clock
	19	* types.
	20	*/
	21	#undef DEBUG
	22
	23	#include <linux/kernel.h>
	24	#include <linux/errno.h>
	25	#include <linux/clk.h>
	26	#include <linux/io.h>
	27
622297fd	28	#include "../plat-omap/sram.h"
b1823d86 PW	29
	30	#include "clock.h"
	31	#include "clock2xxx.h"
	32	#include "opp2xxx.h"
59fb659b	33	#include "cm2xxx_3xxx.h"
b1823d86	34	#include "cm-regbits-24xx.h"
3e6ece13	35	#include "sdrc.h"
b1823d86 PW	36
	37	/* #define DOWN_VARIABLE_DPLL 1 / / Experimental */
	38
5f039377 PW	39	/*
	40	* dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
	41	* (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
	42	* during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
	43	*/
	44	static struct clk *dpll_core_ck;
	45
b1823d86 PW	46	/**
b1823d86 PW	47	* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
b1823d86 PW	48	*
	49	* Returns the CORE_CLK rate. CORE_CLK can have one of three rate
	50	* sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
	51	* (the latter is unusual). This currently should be called with
	52	* struct clk *dpll_ck, which is a composite clock of dpll_ck and
	53	* core_ck.
	54	*/
5f039377	55	unsigned long omap2xxx_clk_get_core_rate(void)
b1823d86 PW	56	{
	57	long long core_clk;
	58	u32 v;
	59
5f039377 PW	60	WARN_ON(!dpll_core_ck);
	61
	62	core_clk = omap2_get_dpll_rate(dpll_core_ck);
b1823d86	63
c4d7e58f	64	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
b1823d86 PW	65	v &= OMAP24XX_CORE_CLK_SRC_MASK;
	66
	67	if (v == CORE_CLK_SRC_32K)
	68	core_clk = 32768;
	69	else
	70	core_clk *= v;
	71
	72	return core_clk;
	73	}
	74
	75	/*
	76	* Uses the current prcm set to tell if a rate is valid.
	77	* You can go slower, but not faster within a given rate set.
	78	*/
	79	static long omap2_dpllcore_round_rate(unsigned long target_rate)
	80	{
	81	u32 high, low, core_clk_src;
	82
c4d7e58f	83	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
b1823d86 PW	84	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
	85
	86	if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
	87	high = curr_prcm_set->dpll_speed * 2;
	88	low = curr_prcm_set->dpll_speed;
	89	} else { /* DPLL clockout x 2 */
	90	high = curr_prcm_set->dpll_speed;
	91	low = curr_prcm_set->dpll_speed / 2;
	92	}
	93
	94	#ifdef DOWN_VARIABLE_DPLL
	95	if (target_rate > high)
	96	return high;
	97	else
	98	return target_rate;
	99	#else
	100	if (target_rate > low)
	101	return high;
	102	else
	103	return low;
	104	#endif
	105
	106	}
	107
	108	unsigned long omap2_dpllcore_recalc(struct clk *clk)
	109	{
5f039377	110	return omap2xxx_clk_get_core_rate();
b1823d86 PW	111	}
	112
	113	int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
	114	{
	115	u32 cur_rate, low, mult, div, valid_rate, done_rate;
	116	u32 bypass = 0;
	117	struct prcm_config tmpset;
	118	const struct dpll_data *dd;
	119
5f039377	120	cur_rate = omap2xxx_clk_get_core_rate();
c4d7e58f	121	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
b1823d86 PW	122	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
	123
	124	if ((rate == (cur_rate / 2)) && (mult == 2)) {
	125	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
	126	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
	127	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	128	} else if (rate != cur_rate) {
	129	valid_rate = omap2_dpllcore_round_rate(rate);
	130	if (valid_rate != rate)
	131	return -EINVAL;
	132
	133	if (mult == 1)
	134	low = curr_prcm_set->dpll_speed;
	135	else
	136	low = curr_prcm_set->dpll_speed / 2;
	137
	138	dd = clk->dpll_data;
	139	if (!dd)
	140	return -EINVAL;
	141
	142	tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
	143	tmpset.cm_clksel1_pll &= ~(dd->mult_mask \|
	144	dd->div1_mask);
	145	div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
c4d7e58f	146	tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
b1823d86 PW	147	tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
	148	if (rate > low) {
	149	tmpset.cm_clksel2_pll \|= CORE_CLK_SRC_DPLL_X2;
	150	mult = ((rate / 2) / 1000000);
	151	done_rate = CORE_CLK_SRC_DPLL_X2;
	152	} else {
	153	tmpset.cm_clksel2_pll \|= CORE_CLK_SRC_DPLL;
	154	mult = (rate / 1000000);
	155	done_rate = CORE_CLK_SRC_DPLL;
	156	}
	157	tmpset.cm_clksel1_pll \|= (div << __ffs(dd->mult_mask));
	158	tmpset.cm_clksel1_pll \|= (mult << __ffs(dd->div1_mask));
	159
	160	/* Worst case */
	161	tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
	162
	163	if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
	164	bypass = 1;
	165
	166	/* For omap2xxx_sdrc_init_params() */
	167	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	168
	169	/* Force dll lock mode */
	170	omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
	171	bypass);
	172
	173	/* Errata: ret dll entry state */
	174	omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
	175	omap2xxx_sdrc_reprogram(done_rate, 0);
	176	}
	177
	178	return 0;
	179	}
	180
5f039377 PW	181	/**
	182	* omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
	183	* @clk: struct clk *dpll_ck
	184	*
	185	* Store a local copy of @clk in dpll_core_ck so other code can query
	186	* the core rate without having to clk_get(), which can sleep. Must
	187	* only be called once. No return value. XXX If the clock
	188	* registration process is ever changed such that dpll_ck is no longer
	189	* statically defined, this code may need to change to increment some
	190	* kind of use count on dpll_ck.
	191	*/
	192	void omap2xxx_clkt_dpllcore_init(struct clk *clk)
	193	{
	194	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
	195	dpll_core_ck = clk;
	196	}