[deliverable/linux.git] / arch / arm / mach-omap2 / clkt2xxx_virt_prcm_set.c

/*
 * OMAP2xxx DVFS virtual clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
 * Gordon McNutt and RidgeRun, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX Some of this code should be replaceable by the upcoming OPP layer
 * code.  However, some notion of "rate set" is probably still necessary
 * for OMAP2xxx at least.  Rate sets should be generalized so they can be
 * used for any OMAP chip, not just OMAP2xxx.  In particular, Richard Woodruff
 * has in the past expressed a preference to use rate sets for OPP changes,
 * rather than dynamically recalculating the clock tree, so if someone wants
 * this badly enough to write the code to handle it, we should support it
 * as an option.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>

#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"

const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;

/**
 * omap2_table_mpu_recalc - just return the MPU speed
 * @clk: virt_prcm_set struct clk
 *
 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 */
unsigned long omap2_table_mpu_recalc(struct clk *clk)
{
	return curr_prcm_set->mpu_speed;
}

/*
 * Look for a rate equal or less than the target rate given a configuration set.
 *
 * What's not entirely clear is "which" field represents the key field.
 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 * just uses the ARM rates.
 */
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
	const struct prcm_config *ptr;
	long highest_rate;

	highest_rate = -EINVAL;

	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
		if (!(ptr->flags & cpu_mask))
			continue;
		if (ptr->xtal_speed != sclk->rate)
			continue;

		highest_rate = ptr->mpu_speed;

		/* Can check only after xtal frequency check */
		if (ptr->mpu_speed <= rate)
			break;
	}
	return highest_rate;
}

/* Sets basic clocks based on the specified rate */
int omap2_select_table_rate(struct clk *clk, unsigned long rate)
{
	u32 cur_rate, done_rate, bypass = 0, tmp;
	const struct prcm_config *prcm;
	unsigned long found_speed = 0;
	unsigned long flags;

	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
			continue;

		if (prcm->xtal_speed != sclk->rate)
			continue;

		if (prcm->mpu_speed <= rate) {
			found_speed = prcm->mpu_speed;
			break;
		}
	}

	if (!found_speed) {
		printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
		       rate / 1000000);
		return -EINVAL;
	}

	curr_prcm_set = prcm;
	cur_rate = omap2xxx_clk_get_core_rate(dclk);

	if (prcm->dpll_speed == cur_rate / 2) {
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
	} else if (prcm->dpll_speed == cur_rate * 2) {
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	} else if (prcm->dpll_speed != cur_rate) {
		local_irq_save(flags);

		if (prcm->dpll_speed == prcm->xtal_speed)
			bypass = 1;

		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
		    CORE_CLK_SRC_DPLL_X2)
			done_rate = CORE_CLK_SRC_DPLL_X2;
		else
			done_rate = CORE_CLK_SRC_DPLL;

		/* MPU divider */
		omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);

		/* dsp + iva1 div(2420), iva2.1(2430) */
		omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
				 OMAP24XX_DSP_MOD, CM_CLKSEL);

		omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);

		/* Major subsystem dividers */
		tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
		omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
				 CM_CLKSEL1);

		if (cpu_is_omap2430())
			omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
					 OMAP2430_MDM_MOD, CM_CLKSEL);

		/* x2 to enter omap2xxx_sdrc_init_params() */
		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);

		omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
			       bypass);

		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
		omap2xxx_sdrc_reprogram(done_rate, 0);

		local_irq_restore(flags);
	}

	return 0;
}
Commit	Line	Data
734f69a7 PW	1	/*
	2	* OMAP2xxx DVFS virtual clock functions
	3	*
	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2010 Nokia Corporation
	6	*
	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
	10	*
	11	* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
	12	* Gordon McNutt and RidgeRun, Inc.
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*
	18	* XXX Some of this code should be replaceable by the upcoming OPP layer
	19	* code. However, some notion of "rate set" is probably still necessary
	20	* for OMAP2xxx at least. Rate sets should be generalized so they can be
	21	* used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
	22	* has in the past expressed a preference to use rate sets for OPP changes,
	23	* rather than dynamically recalculating the clock tree, so if someone wants
	24	* this badly enough to write the code to handle it, we should support it
	25	* as an option.
	26	*/
	27	#undef DEBUG
	28
	29	#include <linux/kernel.h>
	30	#include <linux/errno.h>
	31	#include <linux/clk.h>
	32	#include <linux/io.h>
	33	#include <linux/cpufreq.h>
5a0e3ad6	34	#include <linux/slab.h>
734f69a7	35
2c799cef	36	#include <plat/cpu.h>
734f69a7 PW	37	#include <plat/clock.h>
	38	#include <plat/sram.h>
	39	#include <plat/sdrc.h>
	40
	41	#include "clock.h"
	42	#include "clock2xxx.h"
	43	#include "opp2xxx.h"
59fb659b	44	#include "cm2xxx_3xxx.h"
734f69a7 PW	45	#include "cm-regbits-24xx.h"
	46
	47	const struct prcm_config *curr_prcm_set;
	48	const struct prcm_config *rate_table;
	49
	50	/**
	51	* omap2_table_mpu_recalc - just return the MPU speed
	52	* @clk: virt_prcm_set struct clk
	53	*
	54	* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
	55	*/
	56	unsigned long omap2_table_mpu_recalc(struct clk *clk)
	57	{
	58	return curr_prcm_set->mpu_speed;
	59	}
	60
	61	/*
	62	* Look for a rate equal or less than the target rate given a configuration set.
	63	*
	64	* What's not entirely clear is "which" field represents the key field.
	65	* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
	66	* just uses the ARM rates.
	67	*/
	68	long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
	69	{
	70	const struct prcm_config *ptr;
	71	long highest_rate;
734f69a7 PW	72
	73	highest_rate = -EINVAL;
	74
	75	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
	76	if (!(ptr->flags & cpu_mask))
	77	continue;
59dd7224	78	if (ptr->xtal_speed != sclk->rate)
734f69a7 PW	79	continue;
	80
	81	highest_rate = ptr->mpu_speed;
	82
	83	/* Can check only after xtal frequency check */
	84	if (ptr->mpu_speed <= rate)
	85	break;
	86	}
	87	return highest_rate;
	88	}
	89
	90	/* Sets basic clocks based on the specified rate */
	91	int omap2_select_table_rate(struct clk *clk, unsigned long rate)
	92	{
	93	u32 cur_rate, done_rate, bypass = 0, tmp;
	94	const struct prcm_config *prcm;
	95	unsigned long found_speed = 0;
	96	unsigned long flags;
734f69a7 PW	97
	98	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
	99	if (!(prcm->flags & cpu_mask))
	100	continue;
	101
59dd7224	102	if (prcm->xtal_speed != sclk->rate)
734f69a7 PW	103	continue;
	104
	105	if (prcm->mpu_speed <= rate) {
	106	found_speed = prcm->mpu_speed;
	107	break;
	108	}
	109	}
	110
	111	if (!found_speed) {
	112	printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
	113	rate / 1000000);
	114	return -EINVAL;
	115	}
	116
	117	curr_prcm_set = prcm;
	118	cur_rate = omap2xxx_clk_get_core_rate(dclk);
	119
	120	if (prcm->dpll_speed == cur_rate / 2) {
	121	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
	122	} else if (prcm->dpll_speed == cur_rate * 2) {
	123	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	124	} else if (prcm->dpll_speed != cur_rate) {
	125	local_irq_save(flags);
	126
	127	if (prcm->dpll_speed == prcm->xtal_speed)
	128	bypass = 1;
	129
	130	if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
	131	CORE_CLK_SRC_DPLL_X2)
	132	done_rate = CORE_CLK_SRC_DPLL_X2;
	133	else
	134	done_rate = CORE_CLK_SRC_DPLL;
	135
	136	/* MPU divider */
c4d7e58f	137	omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
734f69a7 PW	138
734f69a7 PW	139	/* dsp + iva1 div(2420), iva2.1(2430) */
c4d7e58f	140	omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
734f69a7 PW	141	OMAP24XX_DSP_MOD, CM_CLKSEL);
734f69a7 PW	142
c4d7e58f	143	omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
734f69a7 PW	144
734f69a7 PW	145	/* Major subsystem dividers */
c4d7e58f PW	146	tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
c4d7e58f PW	147	omap2_cm_write_mod_reg(prcm->cm_clksel1_core \| tmp, CORE_MOD,
734f69a7 PW	148	CM_CLKSEL1);
	149
	150	if (cpu_is_omap2430())
c4d7e58f	151	omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
734f69a7 PW	152	OMAP2430_MDM_MOD, CM_CLKSEL);
	153
	154	/* x2 to enter omap2xxx_sdrc_init_params() */
	155	omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
	156
	157	omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
	158	bypass);
	159
	160	omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
	161	omap2xxx_sdrc_reprogram(done_rate, 0);
	162
	163	local_irq_restore(flags);
	164	}
	165
	166	return 0;
	167	}