[deliverable/linux.git] / arch / arm / mach-omap2 / clkt34xx_dpll3m2.c

/*
 * OMAP34xx M2 divider clock code
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Jouni Högander
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "../plat-omap/sram.h"

#include "clock.h"
#include "clock3xxx.h"
#include "clock34xx.h"
#include "sdrc.h"

#define CYCLES_PER_MHZ			1000000

/*
 * CORE DPLL (DPLL3) M2 divider rate programming functions
 *
 * These call into SRAM code to do the actual CM writes, since the SDRAM
 * is clocked from DPLL3.
 */

/**
 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 * @clk: struct clk * of DPLL to set
 * @rate: rounded target rate
 *
 * Program the DPLL M2 divider with the rounded target rate.  Returns
 * -EINVAL upon error, or 0 upon success.
 */
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
	u32 new_div = 0;
	u32 unlock_dll = 0;
	u32 c;
	unsigned long validrate, sdrcrate, _mpurate;
	struct omap_sdrc_params *sdrc_cs0;
	struct omap_sdrc_params *sdrc_cs1;
	int ret;
	unsigned long clkrate;

	if (!clk || !rate)
		return -EINVAL;

	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	if (validrate != rate)
		return -EINVAL;

	sdrcrate = __clk_get_rate(sdrc_ick_p);
	clkrate = __clk_get_rate(clk);
	if (rate > clkrate)
		sdrcrate <<= ((rate / clkrate) >> 1);
	else
		sdrcrate >>= ((clkrate / rate) >> 1);

	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
	if (ret)
		return -EINVAL;

	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
		pr_debug("clock: will unlock SDRC DLL\n");
		unlock_dll = 1;
	}

	/*
	 * XXX This only needs to be done when the CPU frequency changes
	 */
	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
	c += 1;  /* for safety */
	c *= SDRC_MPURATE_LOOPS;
	c >>= SDRC_MPURATE_SCALE;
	if (c == 0)
		c = 1;

	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
		 clkrate, validrate);
	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	if (sdrc_cs1)
		pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
			 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
			 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);

	if (sdrc_cs1)
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clkrate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	else
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clkrate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  0, 0, 0, 0);
	clk->rate = rate;

	return 0;
}
Commit	Line	Data
35e424e2 PW	1	/*
	2	* OMAP34xx M2 divider clock code
	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2007-2010 Nokia Corporation
	6	*
	7	* Paul Walmsley
	8	* Jouni Högander
	9	*
	10	* Parts of this code are based on code written by
	11	* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17	#undef DEBUG
	18
	19	#include <linux/kernel.h>
	20	#include <linux/errno.h>
	21	#include <linux/clk.h>
	22	#include <linux/io.h>
	23
622297fd	24	#include "../plat-omap/sram.h"
35e424e2 PW	25
35e424e2 PW	26	#include "clock.h"
657ebfad	27	#include "clock3xxx.h"
35e424e2 PW	28	#include "clock34xx.h"
	29	#include "sdrc.h"
	30
	31	#define CYCLES_PER_MHZ 1000000
	32
	33	/*
	34	* CORE DPLL (DPLL3) M2 divider rate programming functions
	35	*
	36	* These call into SRAM code to do the actual CM writes, since the SDRAM
	37	* is clocked from DPLL3.
	38	*/
	39
	40	/**
	41	* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
	42	* @clk: struct clk * of DPLL to set
	43	* @rate: rounded target rate
	44	*
	45	* Program the DPLL M2 divider with the rounded target rate. Returns
	46	* -EINVAL upon error, or 0 upon success.
	47	*/
	48	int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
	49	{
	50	u32 new_div = 0;
	51	u32 unlock_dll = 0;
	52	u32 c;
	53	unsigned long validrate, sdrcrate, _mpurate;
	54	struct omap_sdrc_params *sdrc_cs0;
	55	struct omap_sdrc_params *sdrc_cs1;
	56	int ret;
5dcc3b97	57	unsigned long clkrate;
35e424e2 PW	58
	59	if (!clk \|\| !rate)
	60	return -EINVAL;
	61
	62	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	63	if (validrate != rate)
	64	return -EINVAL;
	65
5dcc3b97 RN	66	sdrcrate = __clk_get_rate(sdrc_ick_p);
	67	clkrate = __clk_get_rate(clk);
	68	if (rate > clkrate)
	69	sdrcrate <<= ((rate / clkrate) >> 1);
35e424e2	70	else
5dcc3b97	71	sdrcrate >>= ((clkrate / rate) >> 1);
35e424e2 PW	72
	73	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
	74	if (ret)
	75	return -EINVAL;
	76
	77	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
	78	pr_debug("clock: will unlock SDRC DLL\n");
	79	unlock_dll = 1;
	80	}
	81
	82	/*
	83	* XXX This only needs to be done when the CPU frequency changes
	84	*/
5dcc3b97	85	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
35e424e2 PW	86	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
	87	c += 1; /* for safety */
	88	c *= SDRC_MPURATE_LOOPS;
	89	c >>= SDRC_MPURATE_SCALE;
	90	if (c == 0)
	91	c = 1;
	92
5dcc3b97 RN	93	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
5dcc3b97 RN	94	clkrate, validrate);
7852ec05	95	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
35e424e2 PW	96	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	97	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	98	if (sdrc_cs1)
7852ec05 PW	99	pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
	100	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	101	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
35e424e2 PW	102
	103	if (sdrc_cs1)
	104	omap3_configure_core_dpll(
5dcc3b97	105	new_div, unlock_dll, c, rate > clkrate,
35e424e2 PW	106	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	107	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	108	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	109	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	110	else
	111	omap3_configure_core_dpll(
5dcc3b97	112	new_div, unlock_dll, c, rate > clkrate,
35e424e2 PW	113	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	114	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	115	0, 0, 0, 0);
5fd2a84a	116	clk->rate = rate;
35e424e2 PW	117
	118	return 0;
	119	}
	120