projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 35e424e2 PW |
1 | /* |
| 2 | * OMAP34xx M2 divider clock code | |
| 3 | * | |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | |
| 6 | * | |
| 7 | * Paul Walmsley | |
| 8 | * Jouni Högander | |
| 9 | * | |
| 10 | * Parts of this code are based on code written by | |
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or modify | |
| 14 | * it under the terms of the GNU General Public License version 2 as | |
| 15 | * published by the Free Software Foundation. | |
| 16 | */ | |
| 17 | #undef DEBUG | |
| 18 | ||
| 19 | #include <linux/kernel.h> | |
| 20 | #include <linux/errno.h> | |
| 21 | #include <linux/clk.h> | |
| 22 | #include <linux/io.h> | |
| 23 | ||
| 24 | #include <plat/clock.h> | |
| 25 | #include <plat/sram.h> | |
| 26 | #include <plat/sdrc.h> | |
| 27 | ||
| 28 | #include "clock.h" | |
| 29 | #include "clock34xx.h" | |
| 30 | #include "sdrc.h" | |
| 31 | ||
| 32 | #define CYCLES_PER_MHZ 1000000 | |
| 33 | ||
| 34 | /* | |
| 35 | * CORE DPLL (DPLL3) M2 divider rate programming functions | |
| 36 | * | |
| 37 | * These call into SRAM code to do the actual CM writes, since the SDRAM | |
| 38 | * is clocked from DPLL3. | |
| 39 | */ | |
| 40 | ||
| 41 | /** | |
| 42 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | |
| 43 | * @clk: struct clk * of DPLL to set | |
| 44 | * @rate: rounded target rate | |
| 45 | * | |
| 46 | * Program the DPLL M2 divider with the rounded target rate. Returns | |
| 47 | * -EINVAL upon error, or 0 upon success. | |
| 48 | */ | |
| 49 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |
| 50 | { | |
| 51 | u32 new_div = 0; | |
| 52 | u32 unlock_dll = 0; | |
| 53 | u32 c; | |
| 54 | unsigned long validrate, sdrcrate, _mpurate; | |
| 55 | struct omap_sdrc_params *sdrc_cs0; | |
| 56 | struct omap_sdrc_params *sdrc_cs1; | |
| 57 | int ret; | |
| 58 | ||
| 59 | if (!clk || !rate) | |
| 60 | return -EINVAL; | |
| 61 | ||
| 62 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | |
| 63 | if (validrate != rate) | |
| 64 | return -EINVAL; | |
| 65 | ||
| 66 | sdrcrate = sdrc_ick_p->rate; | |
| 67 | if (rate > clk->rate) | |
| 68 | sdrcrate <<= ((rate / clk->rate) >> 1); | |
| 69 | else | |
| 70 | sdrcrate >>= ((clk->rate / rate) >> 1); | |
| 71 | ||
| 72 | ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); | |
| 73 | if (ret) | |
| 74 | return -EINVAL; | |
| 75 | ||
| 76 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { | |
| 77 | pr_debug("clock: will unlock SDRC DLL\n"); | |
| 78 | unlock_dll = 1; | |
| 79 | } | |
| 80 | ||
| 81 | /* | |
| 82 | * XXX This only needs to be done when the CPU frequency changes | |
| 83 | */ | |
| 84 | _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; | |
| 85 | c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | |
| 86 | c += 1; /* for safety */ | |
| 87 | c *= SDRC_MPURATE_LOOPS; | |
| 88 | c >>= SDRC_MPURATE_SCALE; | |
| 89 | if (c == 0) | |
| 90 | c = 1; | |
| 91 | ||
| 92 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | |
| 93 | validrate); | |
| 94 | pr_debug("clock: SDRC CS0 timing params used:" | |
| 95 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | |
| 96 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
| 97 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); | |
| 98 | if (sdrc_cs1) | |
| 99 | pr_debug("clock: SDRC CS1 timing params used: " | |
| 100 | " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", | |
| 101 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | |
| 102 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | |
| 103 | ||
| 104 | if (sdrc_cs1) | |
| 105 | omap3_configure_core_dpll( | |
| 106 | new_div, unlock_dll, c, rate > clk->rate, | |
| 107 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
| 108 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | |
| 109 | sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, | |
| 110 | sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); | |
| 111 | else | |
| 112 | omap3_configure_core_dpll( | |
| 113 | new_div, unlock_dll, c, rate > clk->rate, | |
| 114 | sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, | |
| 115 | sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, | |
| 116 | 0, 0, 0, 0); | |
| 117 | ||
| 118 | return 0; | |
| 119 | } | |
| 120 |