[deliverable/linux.git] / arch / arm / mach-omap2 / clkt_dpll.c

/*
 * OMAP2/3/4 DPLL clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk-provider.h>
#include <linux/io.h>

#include <asm/div64.h>

#include "clock.h"

/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER		2
#define DPLL_MIN_DIVIDER		1

/* Possible error results from _dpll_test_mult */
#define DPLL_MULT_UNDERFLOW		-1

/*
 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
 * The higher the scale factor, the greater the risk of arithmetic overflow,
 * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
 * must be a power of DPLL_SCALE_BASE.
 */
#define DPLL_SCALE_FACTOR		64
#define DPLL_SCALE_BASE			2
#define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))

/*
 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
 * From device data manual section 4.3 "DPLL and DLL Specifications".
 */
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000

/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW		-1
#define DPLL_FINT_INVALID		-2

/* Private functions */

/*
 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
 * @clk: DPLL struct clk to test
 * @n: divider value (N) to test
 *
 * Tests whether a particular divider @n will result in a valid DPLL
 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
 * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
 * (assuming that it is counting N upwards), or -2 if the enclosing loop
 * should skip to the next iteration (again assuming N is increasing).
 */
static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
{
	struct dpll_data *dd;
	long fint, fint_min, fint_max;
	int ret = 0;

	dd = clk->dpll_data;

	/* DPLL divider must result in a valid jitter correction val */
	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;

	if (dd->flags & DPLL_J_TYPE) {
		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	} else {
		fint_min = ti_clk_features.fint_min;
		fint_max = ti_clk_features.fint_max;
	}

	if (!fint_min || !fint_max) {
		WARN(1, "No fint limits available!\n");
		return DPLL_FINT_INVALID;
	}

	if (fint < ti_clk_features.fint_min) {
		pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
			 n);
		dd->max_divider = n;
		ret = DPLL_FINT_UNDERFLOW;
	} else if (fint > ti_clk_features.fint_max) {
		pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
			 n);
		dd->min_divider = n;
		ret = DPLL_FINT_INVALID;
	} else if (fint > ti_clk_features.fint_band1_max &&
		   fint < ti_clk_features.fint_band2_min) {
		pr_debug("rejecting n=%d due to Fint failure\n", n);
		ret = DPLL_FINT_INVALID;
	}

	return ret;
}

static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
					    unsigned int m, unsigned int n)
{
	unsigned long long num;

	num = (unsigned long long)parent_rate * m;
	do_div(num, n);
	return num;
}

/*
 * _dpll_test_mult - test a DPLL multiplier value
 * @m: pointer to the DPLL m (multiplier) value under test
 * @n: current DPLL n (divider) value under test
 * @new_rate: pointer to storage for the resulting rounded rate
 * @target_rate: the desired DPLL rate
 * @parent_rate: the DPLL's parent clock rate
 *
 * This code tests a DPLL multiplier value, ensuring that the
 * resulting rate will not be higher than the target_rate, and that
 * the multiplier value itself is valid for the DPLL.  Initially, the
 * integer pointed to by the m argument should be prescaled by
 * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
 * a non-scaled m upon return.  This non-scaled m will result in a
 * new_rate as close as possible to target_rate (but not greater than
 * target_rate) given the current (parent_rate, n, prescaled m)
 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
 * non-scaled m attempted to underflow, which can allow the calling
 * function to bail out early; or 0 upon success.
 */
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
			   unsigned long target_rate,
			   unsigned long parent_rate)
{
	int r = 0, carry = 0;

	/* Unscale m and round if necessary */
	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
		carry = 1;
	*m = (*m / DPLL_SCALE_FACTOR) + carry;

	/*
	 * The new rate must be <= the target rate to avoid programming
	 * a rate that is impossible for the hardware to handle
	 */
	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
	if (*new_rate > target_rate) {
		(*m)--;
		*new_rate = 0;
	}

	/* Guard against m underflow */
	if (*m < DPLL_MIN_MULTIPLIER) {
		*m = DPLL_MIN_MULTIPLIER;
		*new_rate = 0;
		r = DPLL_MULT_UNDERFLOW;
	}

	if (*new_rate == 0)
		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);

	return r;
}

/**
 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
 * @v: bitfield value of the DPLL enable
 *
 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
 */
static int _omap2_dpll_is_in_bypass(u32 v)
{
	u8 mask, val;

	mask = ti_clk_features.dpll_bypass_vals;

	/*
	 * Each set bit in the mask corresponds to a bypass value equal
	 * to the bitshift. Go through each set-bit in the mask and
	 * compare against the given register value.
	 */
	while (mask) {
		val = __ffs(mask);
		mask ^= (1 << val);
		if (v == val)
			return 1;
	}

	return 0;
}

/* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	u32 v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	v = omap2_clk_readl(clk, dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	/* Reparent the struct clk in case the dpll is in bypass */
	if (_omap2_dpll_is_in_bypass(v))
		return 1;

	return 0;
}

/**
 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
 * @clk: struct clk * of a DPLL
 *
 * DPLLs can be locked or bypassed - basically, enabled or disabled.
 * When locked, the DPLL output depends on the M and N values.  When
 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
 * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
 * if the clock @clk is not a DPLL.
 */
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
{
	long long dpll_clk;
	u32 dpll_mult, dpll_div, v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return 0;

	/* Return bypass rate if DPLL is bypassed */
	v = omap2_clk_readl(clk, dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	if (_omap2_dpll_is_in_bypass(v))
		return __clk_get_rate(dd->clk_bypass);

	v = omap2_clk_readl(clk, dd->mult_div1_reg);
	dpll_mult = v & dd->mult_mask;
	dpll_mult >>= __ffs(dd->mult_mask);
	dpll_div = v & dd->div1_mask;
	dpll_div >>= __ffs(dd->div1_mask);

	dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
	do_div(dpll_clk, dpll_div + 1);

	return dpll_clk;
}

/* DPLL rate rounding code */

/**
 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
 * @clk: struct clk * for a DPLL
 * @target_rate: desired DPLL clock rate
 *
 * Given a DPLL and a desired target rate, round the target rate to a
 * possible, programmable rate for this DPLL.  Attempts to select the
 * minimum possible n.  Stores the computed (m, n) in the DPLL's
 * dpll_data structure so set_rate() will not need to call this
 * (expensive) function again.  Returns ~0 if the target rate cannot
 * be rounded, or the rounded rate upon success.
 */
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
		unsigned long *parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	int m, n, r, scaled_max_m;
	unsigned long scaled_rt_rp;
	unsigned long new_rate = 0;
	struct dpll_data *dd;
	unsigned long ref_rate;
	const char *clk_name;

	if (!clk || !clk->dpll_data)
		return ~0;

	dd = clk->dpll_data;

	ref_rate = __clk_get_rate(dd->clk_ref);
	clk_name = __clk_get_name(hw->clk);
	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
		 clk_name, target_rate);

	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;

	dd->last_rounded_rate = 0;

	for (n = dd->min_divider; n <= dd->max_divider; n++) {

		/* Is the (input clk, divider) pair valid for the DPLL? */
		r = _dpll_test_fint(clk, n);
		if (r == DPLL_FINT_UNDERFLOW)
			break;
		else if (r == DPLL_FINT_INVALID)
			continue;

		/* Compute the scaled DPLL multiplier, based on the divider */
		m = scaled_rt_rp * n;

		/*
		 * Since we're counting n up, a m overflow means we
		 * can bail out completely (since as n increases in
		 * the next iteration, there's no way that m can
		 * increase beyond the current m)
		 */
		if (m > scaled_max_m)
			break;

		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
				    ref_rate);

		/* m can't be set low enough for this n - try with a larger n */
		if (r == DPLL_MULT_UNDERFLOW)
			continue;

		pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
			 clk_name, m, n, new_rate);

		if (target_rate == new_rate) {
			dd->last_rounded_m = m;
			dd->last_rounded_n = n;
			dd->last_rounded_rate = target_rate;
			break;
		}
	}

	if (target_rate != new_rate) {
		pr_debug("clock: %s: cannot round to rate %lu\n",
			 clk_name, target_rate);
		return ~0;
	}

	return target_rate;
}
Commit	Line	Data
0b96af68 PW	1	/*
	2	* OMAP2/3/4 DPLL clock functions
	3	*
	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2010 Nokia Corporation
	6	*
	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15	#undef DEBUG
	16
	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
32cc0021	19	#include <linux/clk-provider.h>
0b96af68 PW	20	#include <linux/io.h>
	21
	22	#include <asm/div64.h>
	23
0b96af68	24	#include "clock.h"
0b96af68 PW	25
0b96af68 PW	26	/* DPLL rate rounding: minimum DPLL multiplier, divider values */
93340a22	27	#define DPLL_MIN_MULTIPLIER 2
0b96af68 PW	28	#define DPLL_MIN_DIVIDER 1
	29
	30	/* Possible error results from _dpll_test_mult */
	31	#define DPLL_MULT_UNDERFLOW -1
	32
	33	/*
	34	* Scale factor to mitigate roundoff errors in DPLL rate rounding.
	35	* The higher the scale factor, the greater the risk of arithmetic overflow,
	36	* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
	37	* must be a power of DPLL_SCALE_BASE.
	38	*/
	39	#define DPLL_SCALE_FACTOR 64
	40	#define DPLL_SCALE_BASE 2
	41	#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
	42	(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
	43
1194d7b8 JH	44	/*
	45	* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
	46	* From device data manual section 4.3 "DPLL and DLL Specifications".
	47	*/
	48	#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
	49	#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
0b96af68 PW	50
	51	/* _dpll_test_fint() return codes */
	52	#define DPLL_FINT_UNDERFLOW -1
	53	#define DPLL_FINT_INVALID -2
	54
	55	/* Private functions */
	56
	57	/*
	58	* _dpll_test_fint - test whether an Fint value is valid for the DPLL
	59	* @clk: DPLL struct clk to test
	60	* @n: divider value (N) to test
	61	*
	62	* Tests whether a particular divider @n will result in a valid DPLL
	63	* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
	64	* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
	65	* (assuming that it is counting N upwards), or -2 if the enclosing loop
	66	* should skip to the next iteration (again assuming N is increasing).
	67	*/
6340c872	68	static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
0b96af68 PW	69	{
0b96af68 PW	70	struct dpll_data *dd;
1194d7b8	71	long fint, fint_min, fint_max;
0b96af68 PW	72	int ret = 0;
	73
	74	dd = clk->dpll_data;
	75
	76	/* DPLL divider must result in a valid jitter correction val */
32cc0021	77	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
0b96af68	78
a24886e2	79	if (dd->flags & DPLL_J_TYPE) {
1194d7b8 JH	80	fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
	81	fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	82	} else {
a24886e2 TK	83	fint_min = ti_clk_features.fint_min;
a24886e2 TK	84	fint_max = ti_clk_features.fint_max;
1194d7b8 JH	85	}
1194d7b8 JH	86
a24886e2 TK	87	if (!fint_min \|\| !fint_max) {
	88	WARN(1, "No fint limits available!\n");
	89	return DPLL_FINT_INVALID;
1194d7b8 JH	90	}
1194d7b8 JH	91
a24886e2	92	if (fint < ti_clk_features.fint_min) {
7852ec05 PW	93	pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
7852ec05 PW	94	n);
0b96af68 PW	95	dd->max_divider = n;
0b96af68 PW	96	ret = DPLL_FINT_UNDERFLOW;
a24886e2	97	} else if (fint > ti_clk_features.fint_max) {
7852ec05 PW	98	pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
7852ec05 PW	99	n);
0b96af68 PW	100	dd->min_divider = n;
0b96af68 PW	101	ret = DPLL_FINT_INVALID;
a24886e2 TK	102	} else if (fint > ti_clk_features.fint_band1_max &&
a24886e2 TK	103	fint < ti_clk_features.fint_band2_min) {
1194d7b8 JH	104	pr_debug("rejecting n=%d due to Fint failure\n", n);
1194d7b8 JH	105	ret = DPLL_FINT_INVALID;
0b96af68 PW	106	}
	107
	108	return ret;
	109	}
	110
	111	static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
	112	unsigned int m, unsigned int n)
	113	{
	114	unsigned long long num;
	115
	116	num = (unsigned long long)parent_rate * m;
	117	do_div(num, n);
	118	return num;
	119	}
	120
	121	/*
	122	* _dpll_test_mult - test a DPLL multiplier value
	123	* @m: pointer to the DPLL m (multiplier) value under test
	124	* @n: current DPLL n (divider) value under test
	125	* @new_rate: pointer to storage for the resulting rounded rate
	126	* @target_rate: the desired DPLL rate
	127	* @parent_rate: the DPLL's parent clock rate
	128	*
	129	* This code tests a DPLL multiplier value, ensuring that the
	130	* resulting rate will not be higher than the target_rate, and that
	131	* the multiplier value itself is valid for the DPLL. Initially, the
	132	* integer pointed to by the m argument should be prescaled by
	133	* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
	134	* a non-scaled m upon return. This non-scaled m will result in a
	135	* new_rate as close as possible to target_rate (but not greater than
	136	* target_rate) given the current (parent_rate, n, prescaled m)
	137	* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
	138	* non-scaled m attempted to underflow, which can allow the calling
	139	* function to bail out early; or 0 upon success.
	140	*/
	141	static int _dpll_test_mult(int m, int n, unsigned long new_rate,
	142	unsigned long target_rate,
	143	unsigned long parent_rate)
	144	{
	145	int r = 0, carry = 0;
	146
	147	/* Unscale m and round if necessary */
	148	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
	149	carry = 1;
	150	m = (m / DPLL_SCALE_FACTOR) + carry;
	151
	152	/*
	153	* The new rate must be <= the target rate to avoid programming
	154	* a rate that is impossible for the hardware to handle
	155	*/
	156	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
	157	if (*new_rate > target_rate) {
	158	(*m)--;
	159	*new_rate = 0;
	160	}
	161
	162	/* Guard against m underflow */
	163	if (*m < DPLL_MIN_MULTIPLIER) {
	164	*m = DPLL_MIN_MULTIPLIER;
	165	*new_rate = 0;
	166	r = DPLL_MULT_UNDERFLOW;
	167	}
	168
	169	if (*new_rate == 0)
170	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
171
172	return r;
173	}
174
5f84aeb6 TK	175	/**
	176	* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
	177	* @v: bitfield value of the DPLL enable
	178	*
	179	* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
	180	* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
	181	*/
	182	static int _omap2_dpll_is_in_bypass(u32 v)
	183	{
512d91cb TK	184	u8 mask, val;
	185
	186	mask = ti_clk_features.dpll_bypass_vals;
	187
	188	/*
	189	* Each set bit in the mask corresponds to a bypass value equal
	190	* to the bitshift. Go through each set-bit in the mask and
	191	* compare against the given register value.
	192	*/
	193	while (mask) {
	194	val = __ffs(mask);
	195	mask ^= (1 << val);
	196	if (v == val)
5f84aeb6 TK	197	return 1;
	198	}
	199
	200	return 0;
	201	}
	202
0b96af68	203	/* Public functions */
32cc0021 MT	204	u8 omap2_init_dpll_parent(struct clk_hw *hw)
	205	{
	206	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0b96af68 PW	207	u32 v;
	208	struct dpll_data *dd;
	209
	210	dd = clk->dpll_data;
	211	if (!dd)
32cc0021	212	return -EINVAL;
0b96af68	213
519ab8b2	214	v = omap2_clk_readl(clk, dd->control_reg);
0b96af68 PW	215	v &= dd->enable_mask;
	216	v >>= __ffs(dd->enable_mask);
	217
241d3a8d	218	/* Reparent the struct clk in case the dpll is in bypass */
5f84aeb6 TK	219	if (_omap2_dpll_is_in_bypass(v))
	220	return 1;
	221
32cc0021	222	return 0;
0b96af68 PW	223	}
	224
	225	/**
	226	* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
	227	* @clk: struct clk * of a DPLL
	228	*
	229	* DPLLs can be locked or bypassed - basically, enabled or disabled.
	230	* When locked, the DPLL output depends on the M and N values. When
	231	* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
	232	* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
	233	* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
	234	* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
	235	* Returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is
	236	* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
	237	* if the clock @clk is not a DPLL.
	238	*/
32cc0021	239	unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
0b96af68 PW	240	{
	241	long long dpll_clk;
	242	u32 dpll_mult, dpll_div, v;
	243	struct dpll_data *dd;
	244
	245	dd = clk->dpll_data;
	246	if (!dd)
	247	return 0;
	248
	249	/* Return bypass rate if DPLL is bypassed */
519ab8b2	250	v = omap2_clk_readl(clk, dd->control_reg);
0b96af68 PW	251	v &= dd->enable_mask;
	252	v >>= __ffs(dd->enable_mask);
	253
5f84aeb6 TK	254	if (_omap2_dpll_is_in_bypass(v))
5f84aeb6 TK	255	return __clk_get_rate(dd->clk_bypass);
0b96af68	256
519ab8b2	257	v = omap2_clk_readl(clk, dd->mult_div1_reg);
0b96af68 PW	258	dpll_mult = v & dd->mult_mask;
	259	dpll_mult >>= __ffs(dd->mult_mask);
	260	dpll_div = v & dd->div1_mask;
	261	dpll_div >>= __ffs(dd->div1_mask);
	262
5dcc3b97	263	dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
0b96af68 PW	264	do_div(dpll_clk, dpll_div + 1);
	265
	266	return dpll_clk;
	267	}
	268
	269	/* DPLL rate rounding code */
	270
0b96af68 PW	271	/**
	272	* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
	273	* @clk: struct clk * for a DPLL
	274	* @target_rate: desired DPLL clock rate
	275	*
241d3a8d PW	276	* Given a DPLL and a desired target rate, round the target rate to a
	277	* possible, programmable rate for this DPLL. Attempts to select the
	278	* minimum possible n. Stores the computed (m, n) in the DPLL's
	279	* dpll_data structure so set_rate() will not need to call this
	280	* (expensive) function again. Returns ~0 if the target rate cannot
	281	* be rounded, or the rounded rate upon success.
0b96af68	282	*/
32cc0021 MT	283	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
	284	unsigned long *parent_rate)
	285	{
	286	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
241d3a8d PW	287	int m, n, r, scaled_max_m;
	288	unsigned long scaled_rt_rp;
	289	unsigned long new_rate = 0;
0b96af68	290	struct dpll_data *dd;
5dcc3b97 RN	291	unsigned long ref_rate;
5dcc3b97 RN	292	const char *clk_name;
0b96af68 PW	293
	294	if (!clk \|\| !clk->dpll_data)
	295	return ~0;
	296
	297	dd = clk->dpll_data;
	298
5dcc3b97	299	ref_rate = __clk_get_rate(dd->clk_ref);
32cc0021	300	clk_name = __clk_get_name(hw->clk);
0cc1d944	301	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
5dcc3b97	302	clk_name, target_rate);
0b96af68	303
5dcc3b97	304	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
0b96af68 PW	305	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
	306
	307	dd->last_rounded_rate = 0;
	308
	309	for (n = dd->min_divider; n <= dd->max_divider; n++) {
	310
	311	/* Is the (input clk, divider) pair valid for the DPLL? */
	312	r = _dpll_test_fint(clk, n);
	313	if (r == DPLL_FINT_UNDERFLOW)
	314	break;
	315	else if (r == DPLL_FINT_INVALID)
	316	continue;
	317
	318	/* Compute the scaled DPLL multiplier, based on the divider */
	319	m = scaled_rt_rp * n;
	320
	321	/*
	322	* Since we're counting n up, a m overflow means we
	323	* can bail out completely (since as n increases in
	324	* the next iteration, there's no way that m can
	325	* increase beyond the current m)
	326	*/
	327	if (m > scaled_max_m)
	328	break;
	329
	330	r = _dpll_test_mult(&m, n, &new_rate, target_rate,
5dcc3b97	331	ref_rate);
0b96af68 PW	332
	333	/* m can't be set low enough for this n - try with a larger n */
	334	if (r == DPLL_MULT_UNDERFLOW)
	335	continue;
	336
0cc1d944	337	pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
5dcc3b97	338	clk_name, m, n, new_rate);
0b96af68	339
241d3a8d PW	340	if (target_rate == new_rate) {
	341	dd->last_rounded_m = m;
	342	dd->last_rounded_n = n;
	343	dd->last_rounded_rate = target_rate;
	344	break;
0b96af68 PW	345	}
	346	}
	347
241d3a8d	348	if (target_rate != new_rate) {
0cc1d944	349	pr_debug("clock: %s: cannot round to rate %lu\n",
5dcc3b97	350	clk_name, target_rate);
0b96af68 PW	351	return ~0;
	352	}
	353
241d3a8d	354	return target_rate;
0b96af68 PW	355	}
0b96af68 PW	356