Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
543d9378 PW |
18 | #include <linux/list.h> |
19 | #include <linux/errno.h> | |
4d30e82c PW |
20 | #include <linux/err.h> |
21 | #include <linux/delay.h> | |
543d9378 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
fbd3bdb2 | 24 | #include <linux/bitops.h> |
543d9378 | 25 | |
ce491cf8 | 26 | #include <plat/clock.h> |
1540f214 | 27 | #include "clockdomain.h" |
ce491cf8 TL |
28 | #include <plat/cpu.h> |
29 | #include <plat/prcm.h> | |
543d9378 | 30 | |
543d9378 | 31 | #include "clock.h" |
59fb659b | 32 | #include "cm2xxx_3xxx.h" |
543d9378 PW |
33 | #include "cm-regbits-24xx.h" |
34 | #include "cm-regbits-34xx.h" | |
35 | ||
543d9378 PW |
36 | u8 cpu_mask; |
37 | ||
30962d9d PW |
38 | /* |
39 | * OMAP2+ specific clock functions | |
40 | */ | |
543d9378 | 41 | |
4b1f76ed PW |
42 | /* Private functions */ |
43 | ||
44 | /** | |
45 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
46 | * @clk: struct clk * belonging to the module | |
47 | * | |
48 | * If the necessary clocks for the OMAP hardware IP block that | |
49 | * corresponds to clock @clk are enabled, then wait for the module to | |
50 | * indicate readiness (i.e., to leave IDLE). This code does not | |
51 | * belong in the clock code and will be moved in the medium term to | |
52 | * module-dependent code. No return value. | |
53 | */ | |
54 | static void _omap2_module_wait_ready(struct clk *clk) | |
55 | { | |
56 | void __iomem *companion_reg, *idlest_reg; | |
419cc97d | 57 | u8 other_bit, idlest_bit, idlest_val; |
4b1f76ed PW |
58 | |
59 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
60 | if (clk->ops->find_companion) { | |
61 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
62 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
63 | return; | |
64 | } | |
65 | ||
419cc97d | 66 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
4b1f76ed | 67 | |
419cc97d RL |
68 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
69 | clk->name); | |
4b1f76ed PW |
70 | } |
71 | ||
4b1f76ed PW |
72 | /* Public functions */ |
73 | ||
333943ba PW |
74 | /** |
75 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
76 | * @clk: OMAP clock struct ptr to use | |
77 | * | |
78 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
79 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
80 | * called during clk_register(). No return value. | |
81 | */ | |
82 | void omap2_init_clk_clkdm(struct clk *clk) | |
83 | { | |
84 | struct clockdomain *clkdm; | |
85 | ||
86 | if (!clk->clkdm_name) | |
87 | return; | |
88 | ||
89 | clkdm = clkdm_lookup(clk->clkdm_name); | |
90 | if (clkdm) { | |
91 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
92 | clk->name, clk->clkdm_name); | |
93 | clk->clkdm = clkdm; | |
94 | } else { | |
95 | pr_debug("clock: could not associate clk %s to " | |
96 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
97 | } | |
98 | } | |
99 | ||
543d9378 | 100 | /** |
72350b29 PW |
101 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
102 | * @clk: struct clk * to find the companion clock of | |
103 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
104 | * @other_bit: u8 ** to return the companion clock bit shift in | |
105 | * | |
106 | * Note: We don't need special code here for INVERT_ENABLE for the | |
107 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
108 | * CM_CLKEN_PLL | |
543d9378 | 109 | * |
72350b29 PW |
110 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
111 | * just a matter of XORing the bits. | |
112 | * | |
113 | * Some clocks don't have companion clocks. For example, modules with | |
114 | * only an interface clock (such as MAILBOXES) don't have a companion | |
115 | * clock. Right now, this code relies on the hardware exporting a bit | |
116 | * in the correct companion register that indicates that the | |
117 | * nonexistent 'companion clock' is active. Future patches will | |
118 | * associate this type of code with per-module data structures to | |
119 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 120 | */ |
72350b29 PW |
121 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
122 | u8 *other_bit) | |
543d9378 | 123 | { |
72350b29 | 124 | u32 r; |
543d9378 PW |
125 | |
126 | /* | |
72350b29 PW |
127 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
128 | * it's just a matter of XORing the bits. | |
543d9378 | 129 | */ |
72350b29 | 130 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 131 | |
72350b29 PW |
132 | *other_reg = (__force void __iomem *)r; |
133 | *other_bit = clk->enable_bit; | |
134 | } | |
543d9378 | 135 | |
72350b29 PW |
136 | /** |
137 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
138 | * @clk: struct clk * to find IDLEST info for | |
139 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
140 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
141 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
142 | * |
143 | * Return the CM_IDLEST register address and bit shift corresponding | |
144 | * to the module that "owns" this clock. This default code assumes | |
145 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
146 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
147 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
148 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 149 | */ |
72350b29 | 150 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
419cc97d | 151 | u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 152 | { |
72350b29 | 153 | u32 r; |
543d9378 | 154 | |
72350b29 PW |
155 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
156 | *idlest_reg = (__force void __iomem *)r; | |
157 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
158 | |
159 | /* | |
160 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
161 | * 34xx reverses this, just to keep us on our toes | |
162 | * AM35xx uses both, depending on the module. | |
163 | */ | |
164 | if (cpu_is_omap24xx()) | |
165 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
166 | else if (cpu_is_omap34xx()) | |
167 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
168 | else | |
169 | BUG(); | |
170 | ||
72350b29 | 171 | } |
543d9378 | 172 | |
72350b29 | 173 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 174 | { |
ee1eec36 | 175 | u32 v; |
543d9378 | 176 | |
c0fc18c5 | 177 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 178 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
179 | clk->name); |
180 | return 0; /* REVISIT: -EINVAL */ | |
181 | } | |
182 | ||
ee1eec36 | 183 | v = __raw_readl(clk->enable_reg); |
543d9378 | 184 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 185 | v &= ~(1 << clk->enable_bit); |
543d9378 | 186 | else |
ee1eec36 PW |
187 | v |= (1 << clk->enable_bit); |
188 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 189 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 190 | |
72350b29 | 191 | if (clk->ops->find_idlest) |
4b1f76ed | 192 | _omap2_module_wait_ready(clk); |
543d9378 | 193 | |
72350b29 | 194 | return 0; |
bc51da4e RK |
195 | } |
196 | ||
72350b29 | 197 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 198 | { |
ee1eec36 | 199 | u32 v; |
543d9378 | 200 | |
fecb494b | 201 | if (!clk->enable_reg) { |
543d9378 PW |
202 | /* |
203 | * 'Independent' here refers to a clock which is not | |
204 | * controlled by its parent. | |
205 | */ | |
206 | printk(KERN_ERR "clock: clk_disable called on independent " | |
207 | "clock %s which has no enable_reg\n", clk->name); | |
208 | return; | |
209 | } | |
210 | ||
ee1eec36 | 211 | v = __raw_readl(clk->enable_reg); |
543d9378 | 212 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 213 | v |= (1 << clk->enable_bit); |
543d9378 | 214 | else |
ee1eec36 PW |
215 | v &= ~(1 << clk->enable_bit); |
216 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 217 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
218 | } |
219 | ||
b36ee724 | 220 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 221 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 222 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
223 | .find_companion = omap2_clk_dflt_find_companion, |
224 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
225 | }; |
226 | ||
bc51da4e RK |
227 | const struct clkops clkops_omap2_dflt = { |
228 | .enable = omap2_dflt_clk_enable, | |
229 | .disable = omap2_dflt_clk_disable, | |
230 | }; | |
231 | ||
30962d9d PW |
232 | /** |
233 | * omap2_clk_disable - disable a clock, if the system is not using it | |
234 | * @clk: struct clk * to disable | |
235 | * | |
236 | * Decrements the usecount on struct clk @clk. If there are no users | |
237 | * left, call the clkops-specific clock disable function to disable it | |
238 | * in hardware. If the clock is part of a clockdomain (which they all | |
239 | * should be), request that the clockdomain be disabled. (It too has | |
240 | * a usecount, and so will not be disabled in the hardware until it no | |
241 | * longer has any users.) If the clock has a parent clock (most of | |
242 | * them do), then call ourselves, recursing on the parent clock. This | |
243 | * can cause an entire branch of the clock tree to be powered off by | |
244 | * simply disabling one clock. Intended to be called with the clockfw_lock | |
245 | * spinlock held. No return value. | |
246 | */ | |
543d9378 PW |
247 | void omap2_clk_disable(struct clk *clk) |
248 | { | |
30962d9d PW |
249 | if (clk->usecount == 0) { |
250 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " | |
251 | "already 0?", clk->name); | |
252 | return; | |
543d9378 | 253 | } |
30962d9d PW |
254 | |
255 | pr_debug("clock: %s: decrementing usecount\n", clk->name); | |
256 | ||
257 | clk->usecount--; | |
258 | ||
259 | if (clk->usecount > 0) | |
260 | return; | |
261 | ||
262 | pr_debug("clock: %s: disabling in hardware\n", clk->name); | |
263 | ||
264 | clk->ops->disable(clk); | |
265 | ||
266 | if (clk->clkdm) | |
267 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
268 | ||
269 | if (clk->parent) | |
270 | omap2_clk_disable(clk->parent); | |
543d9378 PW |
271 | } |
272 | ||
30962d9d PW |
273 | /** |
274 | * omap2_clk_enable - request that the system enable a clock | |
275 | * @clk: struct clk * to enable | |
276 | * | |
277 | * Increments the usecount on struct clk @clk. If there were no users | |
278 | * previously, then recurse up the clock tree, enabling all of the | |
279 | * clock's parents and all of the parent clockdomains, and finally, | |
280 | * enabling @clk's clockdomain, and @clk itself. Intended to be | |
281 | * called with the clockfw_lock spinlock held. Returns 0 upon success | |
282 | * or a negative error code upon failure. | |
283 | */ | |
543d9378 PW |
284 | int omap2_clk_enable(struct clk *clk) |
285 | { | |
30962d9d | 286 | int ret; |
543d9378 | 287 | |
30962d9d | 288 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
333943ba | 289 | |
30962d9d PW |
290 | clk->usecount++; |
291 | ||
292 | if (clk->usecount > 1) | |
293 | return 0; | |
333943ba | 294 | |
30962d9d PW |
295 | pr_debug("clock: %s: enabling in hardware\n", clk->name); |
296 | ||
297 | if (clk->parent) { | |
298 | ret = omap2_clk_enable(clk->parent); | |
a7f8c599 | 299 | if (ret) { |
30962d9d PW |
300 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
301 | clk->name, clk->parent->name, ret); | |
302 | goto oce_err1; | |
303 | } | |
304 | } | |
a7f8c599 | 305 | |
30962d9d PW |
306 | if (clk->clkdm) { |
307 | ret = omap2_clkdm_clk_enable(clk->clkdm, clk); | |
308 | if (ret) { | |
309 | WARN(1, "clock: %s: could not enable clockdomain %s: " | |
310 | "%d\n", clk->name, clk->clkdm->name, ret); | |
311 | goto oce_err2; | |
543d9378 PW |
312 | } |
313 | } | |
314 | ||
30962d9d PW |
315 | ret = clk->ops->enable(clk); |
316 | if (ret) { | |
317 | WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); | |
318 | goto oce_err3; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | ||
323 | oce_err3: | |
8263e5b3 RK |
324 | if (clk->clkdm) |
325 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
30962d9d PW |
326 | oce_err2: |
327 | if (clk->parent) | |
328 | omap2_clk_disable(clk->parent); | |
329 | oce_err1: | |
a7f8c599 | 330 | clk->usecount--; |
30962d9d | 331 | |
543d9378 PW |
332 | return ret; |
333 | } | |
334 | ||
435699db PW |
335 | /* Given a clock and a rate apply a clock specific rounding function */ |
336 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |
337 | { | |
338 | if (clk->round_rate) | |
339 | return clk->round_rate(clk, rate); | |
340 | ||
341 | return clk->rate; | |
342 | } | |
343 | ||
543d9378 PW |
344 | /* Set the clock rate for a clock source */ |
345 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
346 | { | |
347 | int ret = -EINVAL; | |
348 | ||
349 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
350 | ||
543d9378 | 351 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
fecb494b | 352 | if (clk->set_rate) |
543d9378 PW |
353 | ret = clk->set_rate(clk, rate); |
354 | ||
543d9378 PW |
355 | return ret; |
356 | } | |
357 | ||
543d9378 PW |
358 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
359 | { | |
543d9378 PW |
360 | if (!clk->clksel) |
361 | return -EINVAL; | |
362 | ||
1a337717 PW |
363 | if (clk->parent == new_parent) |
364 | return 0; | |
365 | ||
df791b3e | 366 | return omap2_clksel_set_parent(clk, new_parent); |
543d9378 PW |
367 | } |
368 | ||
657ebfad PW |
369 | /* OMAP3/4 non-CORE DPLL clkops */ |
370 | ||
371 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | |
372 | ||
373 | const struct clkops clkops_omap3_noncore_dpll_ops = { | |
374 | .enable = omap3_noncore_dpll_enable, | |
375 | .disable = omap3_noncore_dpll_disable, | |
376 | }; | |
377 | ||
378 | #endif | |
379 | ||
380 | ||
30962d9d PW |
381 | /* |
382 | * OMAP2+ clock reset and init functions | |
383 | */ | |
543d9378 PW |
384 | |
385 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
386 | void omap2_clk_disable_unused(struct clk *clk) | |
387 | { | |
388 | u32 regval32, v; | |
389 | ||
390 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
391 | ||
392 | regval32 = __raw_readl(clk->enable_reg); | |
393 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
394 | return; | |
395 | ||
6041c27f | 396 | pr_debug("Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
397 | if (cpu_is_omap34xx()) { |
398 | omap2_clk_enable(clk); | |
399 | omap2_clk_disable(clk); | |
30962d9d PW |
400 | } else { |
401 | clk->ops->disable(clk); | |
402 | } | |
fe617af7 PDS |
403 | if (clk->clkdm != NULL) |
404 | pwrdm_clkdm_state_switch(clk->clkdm); | |
543d9378 PW |
405 | } |
406 | #endif | |
69ecefca | 407 | |
4d30e82c PW |
408 | /** |
409 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
410 | * @mpurate_ck_name: clk name of the clock to change rate | |
411 | * | |
412 | * Change the ARM MPU clock rate to the rate specified on the command | |
413 | * line, if one was specified. @mpurate_ck_name should be | |
414 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
415 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
416 | * handled by the virt_prcm_set clock, but this should be handled by | |
417 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
418 | * code in the near future and should be removed from the clock code. | |
419 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
420 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
421 | * cannot be found, or 0 upon success. | |
422 | */ | |
423 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
424 | { | |
425 | struct clk *mpurate_ck; | |
426 | int r; | |
427 | ||
428 | if (!mpurate) | |
429 | return -EINVAL; | |
430 | ||
431 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
432 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
433 | return -ENOENT; | |
434 | ||
435 | r = clk_set_rate(mpurate_ck, mpurate); | |
436 | if (IS_ERR_VALUE(r)) { | |
437 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", | |
438 | mpurate_ck->name, mpurate, r); | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | calibrate_delay(); | |
443 | recalculate_root_clocks(); | |
444 | ||
445 | clk_put(mpurate_ck); | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | /** | |
451 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
452 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
453 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
454 | * @mpu_ck_name: clk name for the ARM MPU clock | |
455 | * | |
456 | * Prints a short message to the console with the HFCLKIN oscillator | |
457 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
458 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
459 | * to be handled by the OPP layer code in the near future and should be | |
460 | * removed from the clock code. No return value. | |
461 | */ | |
462 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
463 | const char *core_ck_name, | |
464 | const char *mpu_ck_name) | |
465 | { | |
466 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
467 | unsigned long hfclkin_rate; | |
468 | ||
469 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
470 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
471 | return; | |
472 | ||
473 | core_ck = clk_get(NULL, core_ck_name); | |
474 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
475 | return; | |
476 | ||
477 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
478 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
479 | return; | |
480 | ||
481 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
482 | ||
483 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " | |
484 | "%ld.%01ld/%ld/%ld MHz\n", | |
485 | (hfclkin_rate / 1000000), | |
486 | ((hfclkin_rate / 100000) % 10), | |
487 | (clk_get_rate(core_ck) / 1000000), | |
488 | (clk_get_rate(mpu_ck) / 1000000)); | |
489 | } | |
490 | ||
69ecefca PW |
491 | /* Common data */ |
492 | ||
493 | struct clk_functions omap2_clk_functions = { | |
494 | .clk_enable = omap2_clk_enable, | |
495 | .clk_disable = omap2_clk_disable, | |
496 | .clk_round_rate = omap2_clk_round_rate, | |
497 | .clk_set_rate = omap2_clk_set_rate, | |
498 | .clk_set_parent = omap2_clk_set_parent, | |
499 | .clk_disable_unused = omap2_clk_disable_unused, | |
500 | #ifdef CONFIG_CPU_FREQ | |
501 | /* These will be removed when the OPP code is integrated */ | |
502 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | |
503 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | |
504 | #endif | |
505 | }; | |
506 |