Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
1fe9be82 | 18 | #include <linux/export.h> |
543d9378 PW |
19 | #include <linux/list.h> |
20 | #include <linux/errno.h> | |
4d30e82c PW |
21 | #include <linux/err.h> |
22 | #include <linux/delay.h> | |
32cc0021 | 23 | #include <linux/clk-provider.h> |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
78e52e02 | 26 | #include <linux/clk-private.h> |
5e7c58dc | 27 | #include <asm/cpu.h> |
dbc04161 | 28 | |
dbc04161 TL |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include "soc.h" | |
32 | #include "clockdomain.h" | |
543d9378 | 33 | #include "clock.h" |
c4ceedcb | 34 | #include "cm.h" |
ff4ae5d9 PW |
35 | #include "cm2xxx.h" |
36 | #include "cm3xxx.h" | |
543d9378 PW |
37 | #include "cm-regbits-24xx.h" |
38 | #include "cm-regbits-34xx.h" | |
c4ceedcb PW |
39 | #include "common.h" |
40 | ||
41 | /* | |
42 | * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait | |
43 | * for a module to indicate that it is no longer in idle | |
44 | */ | |
45 | #define MAX_MODULE_ENABLE_WAIT 100000 | |
543d9378 | 46 | |
99541195 | 47 | u16 cpu_mask; |
543d9378 | 48 | |
12706c54 PW |
49 | /* |
50 | * clkdm_control: if true, then when a clock is enabled in the | |
51 | * hardware, its clockdomain will first be enabled; and when a clock | |
52 | * is disabled in the hardware, its clockdomain will be disabled | |
53 | * afterwards. | |
54 | */ | |
55 | static bool clkdm_control = true; | |
56 | ||
23fb8ba3 | 57 | static LIST_HEAD(clk_hw_omap_clocks); |
3ada6b10 TK |
58 | void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; |
59 | ||
60 | void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) | |
61 | { | |
62 | if (clk->flags & MEMMAP_ADDRESSING) { | |
63 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
64 | writel_relaxed(val, clk_memmaps[r->index] + r->offset); | |
65 | } else { | |
66 | writel_relaxed(val, reg); | |
67 | } | |
68 | } | |
69 | ||
70 | u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) | |
71 | { | |
72 | u32 val; | |
73 | ||
74 | if (clk->flags & MEMMAP_ADDRESSING) { | |
75 | struct clk_omap_reg *r = (struct clk_omap_reg *)® | |
76 | val = readl_relaxed(clk_memmaps[r->index] + r->offset); | |
77 | } else { | |
78 | val = readl_relaxed(reg); | |
79 | } | |
80 | ||
81 | return val; | |
82 | } | |
32cc0021 MT |
83 | |
84 | /* | |
85 | * Used for clocks that have the same value as the parent clock, | |
86 | * divided by some factor | |
87 | */ | |
88 | unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, | |
89 | unsigned long parent_rate) | |
90 | { | |
91 | struct clk_hw_omap *oclk; | |
92 | ||
93 | if (!hw) { | |
94 | pr_warn("%s: hw is NULL\n", __func__); | |
95 | return -EINVAL; | |
96 | } | |
97 | ||
98 | oclk = to_clk_hw_omap(hw); | |
99 | ||
100 | WARN_ON(!oclk->fixed_div); | |
101 | ||
102 | return parent_rate / oclk->fixed_div; | |
103 | } | |
1fe9be82 | 104 | |
30962d9d PW |
105 | /* |
106 | * OMAP2+ specific clock functions | |
107 | */ | |
543d9378 | 108 | |
4b1f76ed PW |
109 | /* Private functions */ |
110 | ||
c4ceedcb PW |
111 | |
112 | /** | |
113 | * _wait_idlest_generic - wait for a module to leave the idle state | |
519ab8b2 | 114 | * @clk: module clock to wait for (needed for register offsets) |
c4ceedcb PW |
115 | * @reg: virtual address of module IDLEST register |
116 | * @mask: value to mask against to determine if the module is active | |
117 | * @idlest: idle state indicator (0 or 1) for the clock | |
118 | * @name: name of the clock (for printk) | |
119 | * | |
120 | * Wait for a module to leave idle, where its idle-status register is | |
121 | * not inside the CM module. Returns 1 if the module left idle | |
122 | * promptly, or 0 if the module did not leave idle before the timeout | |
123 | * elapsed. XXX Deprecated - should be moved into drivers for the | |
124 | * individual IP block that the IDLEST register exists in. | |
125 | */ | |
519ab8b2 TK |
126 | static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, |
127 | u32 mask, u8 idlest, const char *name) | |
c4ceedcb PW |
128 | { |
129 | int i = 0, ena = 0; | |
130 | ||
131 | ena = (idlest) ? 0 : mask; | |
132 | ||
519ab8b2 | 133 | omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), |
c4ceedcb PW |
134 | MAX_MODULE_ENABLE_WAIT, i); |
135 | ||
136 | if (i < MAX_MODULE_ENABLE_WAIT) | |
137 | pr_debug("omap clock: module associated with clock %s ready after %d loops\n", | |
138 | name, i); | |
139 | else | |
140 | pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", | |
141 | name, MAX_MODULE_ENABLE_WAIT); | |
142 | ||
143 | return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; | |
144 | }; | |
145 | ||
4b1f76ed PW |
146 | /** |
147 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
148 | * @clk: struct clk * belonging to the module | |
149 | * | |
150 | * If the necessary clocks for the OMAP hardware IP block that | |
151 | * corresponds to clock @clk are enabled, then wait for the module to | |
152 | * indicate readiness (i.e., to leave IDLE). This code does not | |
153 | * belong in the clock code and will be moved in the medium term to | |
154 | * module-dependent code. No return value. | |
155 | */ | |
32cc0021 | 156 | static void _omap2_module_wait_ready(struct clk_hw_omap *clk) |
4b1f76ed PW |
157 | { |
158 | void __iomem *companion_reg, *idlest_reg; | |
c4ceedcb PW |
159 | u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; |
160 | s16 prcm_mod; | |
161 | int r; | |
4b1f76ed PW |
162 | |
163 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
164 | if (clk->ops->find_companion) { | |
165 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
519ab8b2 | 166 | if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) |
4b1f76ed PW |
167 | return; |
168 | } | |
169 | ||
419cc97d | 170 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
c4ceedcb PW |
171 | r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); |
172 | if (r) { | |
173 | /* IDLEST register not in the CM module */ | |
519ab8b2 TK |
174 | _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), |
175 | idlest_val, __clk_get_name(clk->hw.clk)); | |
c4ceedcb PW |
176 | } else { |
177 | cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); | |
178 | }; | |
4b1f76ed PW |
179 | } |
180 | ||
4b1f76ed PW |
181 | /* Public functions */ |
182 | ||
333943ba PW |
183 | /** |
184 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
185 | * @clk: OMAP clock struct ptr to use | |
186 | * | |
187 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
188 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
189 | * called during clk_register(). No return value. | |
190 | */ | |
32cc0021 MT |
191 | void omap2_init_clk_clkdm(struct clk_hw *hw) |
192 | { | |
193 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
333943ba | 194 | struct clockdomain *clkdm; |
5dcc3b97 | 195 | const char *clk_name; |
333943ba PW |
196 | |
197 | if (!clk->clkdm_name) | |
198 | return; | |
199 | ||
32cc0021 | 200 | clk_name = __clk_get_name(hw->clk); |
5dcc3b97 | 201 | |
333943ba PW |
202 | clkdm = clkdm_lookup(clk->clkdm_name); |
203 | if (clkdm) { | |
204 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
5dcc3b97 | 205 | clk_name, clk->clkdm_name); |
333943ba PW |
206 | clk->clkdm = clkdm; |
207 | } else { | |
7852ec05 | 208 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
5dcc3b97 | 209 | clk_name, clk->clkdm_name); |
333943ba PW |
210 | } |
211 | } | |
212 | ||
12706c54 PW |
213 | /** |
214 | * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable | |
215 | * | |
216 | * Prevent the OMAP clock code from calling into the clockdomain code | |
217 | * when a hardware clock in that clockdomain is enabled or disabled. | |
218 | * Intended to be called at init time from omap*_clk_init(). No | |
219 | * return value. | |
220 | */ | |
221 | void __init omap2_clk_disable_clkdm_control(void) | |
222 | { | |
223 | clkdm_control = false; | |
224 | } | |
225 | ||
543d9378 | 226 | /** |
72350b29 PW |
227 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
228 | * @clk: struct clk * to find the companion clock of | |
229 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
230 | * @other_bit: u8 ** to return the companion clock bit shift in | |
231 | * | |
232 | * Note: We don't need special code here for INVERT_ENABLE for the | |
233 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
234 | * CM_CLKEN_PLL | |
543d9378 | 235 | * |
72350b29 PW |
236 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
237 | * just a matter of XORing the bits. | |
238 | * | |
239 | * Some clocks don't have companion clocks. For example, modules with | |
240 | * only an interface clock (such as MAILBOXES) don't have a companion | |
241 | * clock. Right now, this code relies on the hardware exporting a bit | |
242 | * in the correct companion register that indicates that the | |
243 | * nonexistent 'companion clock' is active. Future patches will | |
244 | * associate this type of code with per-module data structures to | |
245 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 246 | */ |
32cc0021 | 247 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
32cc0021 | 248 | void __iomem **other_reg, u8 *other_bit) |
543d9378 | 249 | { |
72350b29 | 250 | u32 r; |
543d9378 PW |
251 | |
252 | /* | |
72350b29 PW |
253 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
254 | * it's just a matter of XORing the bits. | |
543d9378 | 255 | */ |
72350b29 | 256 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 257 | |
72350b29 PW |
258 | *other_reg = (__force void __iomem *)r; |
259 | *other_bit = clk->enable_bit; | |
260 | } | |
543d9378 | 261 | |
72350b29 PW |
262 | /** |
263 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
264 | * @clk: struct clk * to find IDLEST info for | |
265 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
266 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
267 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
268 | * |
269 | * Return the CM_IDLEST register address and bit shift corresponding | |
270 | * to the module that "owns" this clock. This default code assumes | |
271 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
272 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
273 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
274 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 275 | */ |
32cc0021 | 276 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, |
32cc0021 | 277 | void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 278 | { |
72350b29 | 279 | u32 r; |
543d9378 | 280 | |
72350b29 PW |
281 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
282 | *idlest_reg = (__force void __iomem *)r; | |
283 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
284 | |
285 | /* | |
286 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
287 | * 34xx reverses this, just to keep us on our toes | |
288 | * AM35xx uses both, depending on the module. | |
289 | */ | |
290 | if (cpu_is_omap24xx()) | |
291 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
292 | else if (cpu_is_omap34xx()) | |
293 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
294 | else | |
295 | BUG(); | |
296 | ||
72350b29 | 297 | } |
543d9378 | 298 | |
32cc0021 MT |
299 | /** |
300 | * omap2_dflt_clk_enable - enable a clock in the hardware | |
301 | * @hw: struct clk_hw * of the clock to enable | |
302 | * | |
303 | * Enable the clock @hw in the hardware. We first call into the OMAP | |
304 | * clockdomain code to "enable" the corresponding clockdomain if this | |
305 | * is the first enabled user of the clockdomain. Then program the | |
306 | * hardware to enable the clock. Then wait for the IP block that uses | |
307 | * this clock to leave idle (if applicable). Returns the error value | |
308 | * from clkdm_clk_enable() if it terminated with an error, or -EINVAL | |
309 | * if @hw has a null clock enable_reg, or zero upon success. | |
310 | */ | |
311 | int omap2_dflt_clk_enable(struct clk_hw *hw) | |
312 | { | |
313 | struct clk_hw_omap *clk; | |
314 | u32 v; | |
315 | int ret = 0; | |
316 | ||
317 | clk = to_clk_hw_omap(hw); | |
318 | ||
319 | if (clkdm_control && clk->clkdm) { | |
320 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
321 | if (ret) { | |
322 | WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", | |
323 | __func__, __clk_get_name(hw->clk), | |
324 | clk->clkdm->name, ret); | |
325 | return ret; | |
326 | } | |
327 | } | |
328 | ||
329 | if (unlikely(clk->enable_reg == NULL)) { | |
330 | pr_err("%s: %s missing enable_reg\n", __func__, | |
331 | __clk_get_name(hw->clk)); | |
332 | ret = -EINVAL; | |
333 | goto err; | |
334 | } | |
335 | ||
336 | /* FIXME should not have INVERT_ENABLE bit here */ | |
519ab8b2 | 337 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
338 | if (clk->flags & INVERT_ENABLE) |
339 | v &= ~(1 << clk->enable_bit); | |
340 | else | |
341 | v |= (1 << clk->enable_bit); | |
519ab8b2 TK |
342 | omap2_clk_writel(v, clk, clk->enable_reg); |
343 | v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ | |
32cc0021 MT |
344 | |
345 | if (clk->ops && clk->ops->find_idlest) | |
346 | _omap2_module_wait_ready(clk); | |
347 | ||
348 | return 0; | |
349 | ||
350 | err: | |
351 | if (clkdm_control && clk->clkdm) | |
352 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
353 | return ret; | |
354 | } | |
355 | ||
356 | /** | |
357 | * omap2_dflt_clk_disable - disable a clock in the hardware | |
358 | * @hw: struct clk_hw * of the clock to disable | |
359 | * | |
360 | * Disable the clock @hw in the hardware, and call into the OMAP | |
361 | * clockdomain code to "disable" the corresponding clockdomain if all | |
362 | * clocks/hwmods in that clockdomain are now disabled. No return | |
363 | * value. | |
364 | */ | |
365 | void omap2_dflt_clk_disable(struct clk_hw *hw) | |
366 | { | |
367 | struct clk_hw_omap *clk; | |
368 | u32 v; | |
369 | ||
370 | clk = to_clk_hw_omap(hw); | |
371 | if (!clk->enable_reg) { | |
372 | /* | |
373 | * 'independent' here refers to a clock which is not | |
374 | * controlled by its parent. | |
375 | */ | |
376 | pr_err("%s: independent clock %s has no enable_reg\n", | |
377 | __func__, __clk_get_name(hw->clk)); | |
378 | return; | |
379 | } | |
380 | ||
519ab8b2 | 381 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
382 | if (clk->flags & INVERT_ENABLE) |
383 | v |= (1 << clk->enable_bit); | |
384 | else | |
385 | v &= ~(1 << clk->enable_bit); | |
519ab8b2 | 386 | omap2_clk_writel(v, clk, clk->enable_reg); |
32cc0021 MT |
387 | /* No OCP barrier needed here since it is a disable operation */ |
388 | ||
389 | if (clkdm_control && clk->clkdm) | |
390 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
391 | } | |
392 | ||
393 | /** | |
394 | * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw | |
395 | * @hw: struct clk_hw * of the clock being enabled | |
396 | * | |
397 | * Increment the usecount of the clockdomain of the clock pointed to | |
398 | * by @hw; if the usecount is 1, the clockdomain will be "enabled." | |
399 | * Only needed for clocks that don't use omap2_dflt_clk_enable() as | |
400 | * their enable function pointer. Passes along the return value of | |
401 | * clkdm_clk_enable(), -EINVAL if @hw is not associated with a | |
402 | * clockdomain, or 0 if clock framework-based clockdomain control is | |
403 | * not implemented. | |
404 | */ | |
405 | int omap2_clkops_enable_clkdm(struct clk_hw *hw) | |
406 | { | |
407 | struct clk_hw_omap *clk; | |
408 | int ret = 0; | |
409 | ||
410 | clk = to_clk_hw_omap(hw); | |
411 | ||
412 | if (unlikely(!clk->clkdm)) { | |
413 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
414 | __clk_get_name(hw->clk)); | |
415 | return -EINVAL; | |
416 | } | |
417 | ||
418 | if (unlikely(clk->enable_reg)) | |
419 | pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, | |
420 | __clk_get_name(hw->clk)); | |
421 | ||
422 | if (!clkdm_control) { | |
423 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
424 | __func__, __clk_get_name(hw->clk)); | |
425 | return 0; | |
426 | } | |
427 | ||
428 | ret = clkdm_clk_enable(clk->clkdm, hw->clk); | |
429 | WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", | |
430 | __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); | |
431 | ||
432 | return ret; | |
433 | } | |
434 | ||
435 | /** | |
436 | * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw | |
437 | * @hw: struct clk_hw * of the clock being disabled | |
438 | * | |
439 | * Decrement the usecount of the clockdomain of the clock pointed to | |
440 | * by @hw; if the usecount is 0, the clockdomain will be "disabled." | |
441 | * Only needed for clocks that don't use omap2_dflt_clk_disable() as their | |
442 | * disable function pointer. No return value. | |
443 | */ | |
444 | void omap2_clkops_disable_clkdm(struct clk_hw *hw) | |
445 | { | |
446 | struct clk_hw_omap *clk; | |
447 | ||
448 | clk = to_clk_hw_omap(hw); | |
449 | ||
450 | if (unlikely(!clk->clkdm)) { | |
451 | pr_err("%s: %s: no clkdm set ?!\n", __func__, | |
452 | __clk_get_name(hw->clk)); | |
453 | return; | |
454 | } | |
455 | ||
456 | if (unlikely(clk->enable_reg)) | |
457 | pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, | |
458 | __clk_get_name(hw->clk)); | |
459 | ||
460 | if (!clkdm_control) { | |
461 | pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", | |
462 | __func__, __clk_get_name(hw->clk)); | |
463 | return; | |
464 | } | |
465 | ||
466 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
467 | } | |
468 | ||
469 | /** | |
470 | * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? | |
471 | * @hw: struct clk_hw * to check | |
472 | * | |
473 | * Return 1 if the clock represented by @hw is enabled in the | |
474 | * hardware, or 0 otherwise. Intended for use in the struct | |
475 | * clk_ops.is_enabled function pointer. | |
476 | */ | |
477 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw) | |
478 | { | |
479 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
480 | u32 v; | |
481 | ||
519ab8b2 | 482 | v = omap2_clk_readl(clk, clk->enable_reg); |
32cc0021 MT |
483 | |
484 | if (clk->flags & INVERT_ENABLE) | |
485 | v ^= BIT(clk->enable_bit); | |
486 | ||
487 | v &= BIT(clk->enable_bit); | |
488 | ||
489 | return v ? 1 : 0; | |
490 | } | |
491 | ||
492 | static int __initdata mpurate; | |
493 | ||
494 | /* | |
495 | * By default we use the rate set by the bootloader. | |
496 | * You can override this with mpurate= cmdline option. | |
497 | */ | |
498 | static int __init omap_clk_setup(char *str) | |
499 | { | |
500 | get_option(&str, &mpurate); | |
501 | ||
502 | if (!mpurate) | |
503 | return 1; | |
504 | ||
505 | if (mpurate < 1000) | |
506 | mpurate *= 1000000; | |
507 | ||
508 | return 1; | |
509 | } | |
510 | __setup("mpurate=", omap_clk_setup); | |
511 | ||
23fb8ba3 RN |
512 | /** |
513 | * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock | |
514 | * @clk: struct clk * to initialize | |
515 | * | |
516 | * Add an OMAP clock @clk to the internal list of OMAP clocks. Used | |
517 | * temporarily for autoidle handling, until this support can be | |
518 | * integrated into the common clock framework code in some way. No | |
519 | * return value. | |
520 | */ | |
521 | void omap2_init_clk_hw_omap_clocks(struct clk *clk) | |
522 | { | |
523 | struct clk_hw_omap *c; | |
524 | ||
525 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
526 | return; | |
527 | ||
528 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
529 | list_add(&c->node, &clk_hw_omap_clocks); | |
530 | } | |
531 | ||
532 | /** | |
533 | * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that | |
534 | * support it | |
535 | * | |
536 | * Enable clock autoidle on all OMAP clocks that have allow_idle | |
537 | * function pointers associated with them. This function is intended | |
538 | * to be temporary until support for this is added to the common clock | |
539 | * code. Returns 0. | |
540 | */ | |
541 | int omap2_clk_enable_autoidle_all(void) | |
542 | { | |
543 | struct clk_hw_omap *c; | |
544 | ||
545 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
546 | if (c->ops && c->ops->allow_idle) | |
547 | c->ops->allow_idle(c); | |
b1a07b47 TK |
548 | |
549 | of_ti_clk_allow_autoidle_all(); | |
550 | ||
23fb8ba3 RN |
551 | return 0; |
552 | } | |
553 | ||
554 | /** | |
555 | * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that | |
556 | * support it | |
557 | * | |
558 | * Disable clock autoidle on all OMAP clocks that have allow_idle | |
559 | * function pointers associated with them. This function is intended | |
560 | * to be temporary until support for this is added to the common clock | |
561 | * code. Returns 0. | |
562 | */ | |
563 | int omap2_clk_disable_autoidle_all(void) | |
564 | { | |
565 | struct clk_hw_omap *c; | |
566 | ||
567 | list_for_each_entry(c, &clk_hw_omap_clocks, node) | |
568 | if (c->ops && c->ops->deny_idle) | |
569 | c->ops->deny_idle(c); | |
b1a07b47 TK |
570 | |
571 | of_ti_clk_deny_autoidle_all(); | |
572 | ||
23fb8ba3 RN |
573 | return 0; |
574 | } | |
575 | ||
818b40e5 TK |
576 | /** |
577 | * omap2_clk_deny_idle - disable autoidle on an OMAP clock | |
578 | * @clk: struct clk * to disable autoidle for | |
579 | * | |
580 | * Disable autoidle on an OMAP clock. | |
581 | */ | |
582 | int omap2_clk_deny_idle(struct clk *clk) | |
583 | { | |
584 | struct clk_hw_omap *c; | |
585 | ||
586 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
587 | return -EINVAL; | |
588 | ||
589 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
590 | if (c->ops && c->ops->deny_idle) | |
591 | c->ops->deny_idle(c); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /** | |
596 | * omap2_clk_allow_idle - enable autoidle on an OMAP clock | |
597 | * @clk: struct clk * to enable autoidle for | |
598 | * | |
599 | * Enable autoidle on an OMAP clock. | |
600 | */ | |
601 | int omap2_clk_allow_idle(struct clk *clk) | |
602 | { | |
603 | struct clk_hw_omap *c; | |
604 | ||
605 | if (__clk_get_flags(clk) & CLK_IS_BASIC) | |
606 | return -EINVAL; | |
607 | ||
608 | c = to_clk_hw_omap(__clk_get_hw(clk)); | |
609 | if (c->ops && c->ops->allow_idle) | |
610 | c->ops->allow_idle(c); | |
611 | return 0; | |
612 | } | |
613 | ||
8577413c RN |
614 | /** |
615 | * omap2_clk_enable_init_clocks - prepare & enable a list of clocks | |
616 | * @clk_names: ptr to an array of strings of clock names to enable | |
617 | * @num_clocks: number of clock names in @clk_names | |
618 | * | |
619 | * Prepare and enable a list of clocks, named by @clk_names. No | |
620 | * return value. XXX Deprecated; only needed until these clocks are | |
621 | * properly claimed and enabled by the drivers or core code that uses | |
622 | * them. XXX What code disables & calls clk_put on these clocks? | |
623 | */ | |
624 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) | |
625 | { | |
626 | struct clk *init_clk; | |
627 | int i; | |
628 | ||
629 | for (i = 0; i < num_clocks; i++) { | |
630 | init_clk = clk_get(NULL, clk_names[i]); | |
631 | clk_prepare_enable(init_clk); | |
632 | } | |
633 | } | |
634 | ||
32cc0021 MT |
635 | const struct clk_hw_omap_ops clkhwops_wait = { |
636 | .find_idlest = omap2_clk_dflt_find_idlest, | |
637 | .find_companion = omap2_clk_dflt_find_companion, | |
638 | }; | |
32cc0021 | 639 | |
78e52e02 K |
640 | /** |
641 | * omap_clocks_register - register an array of omap_clk | |
642 | * @ocs: pointer to an array of omap_clk to register | |
643 | */ | |
644 | void __init omap_clocks_register(struct omap_clk oclks[], int cnt) | |
645 | { | |
646 | struct omap_clk *c; | |
647 | ||
648 | for (c = oclks; c < oclks + cnt; c++) { | |
649 | clkdev_add(&c->lk); | |
650 | if (!__clk_init(NULL, c->lk.clk)) | |
651 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | |
652 | } | |
653 | } | |
654 | ||
4d30e82c PW |
655 | /** |
656 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
657 | * @mpurate_ck_name: clk name of the clock to change rate | |
658 | * | |
659 | * Change the ARM MPU clock rate to the rate specified on the command | |
660 | * line, if one was specified. @mpurate_ck_name should be | |
661 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
662 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
663 | * handled by the virt_prcm_set clock, but this should be handled by | |
664 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
665 | * code in the near future and should be removed from the clock code. | |
666 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
667 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
668 | * cannot be found, or 0 upon success. | |
669 | */ | |
670 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
671 | { | |
672 | struct clk *mpurate_ck; | |
673 | int r; | |
674 | ||
675 | if (!mpurate) | |
676 | return -EINVAL; | |
677 | ||
678 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
679 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
680 | return -ENOENT; | |
681 | ||
682 | r = clk_set_rate(mpurate_ck, mpurate); | |
c48cd659 | 683 | if (r < 0) { |
4d30e82c | 684 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
32cc0021 | 685 | mpurate_ck_name, mpurate, r); |
f6281f66 | 686 | clk_put(mpurate_ck); |
4d30e82c PW |
687 | return -EINVAL; |
688 | } | |
689 | ||
690 | calibrate_delay(); | |
4d30e82c PW |
691 | clk_put(mpurate_ck); |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | /** | |
697 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
698 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
699 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
700 | * @mpu_ck_name: clk name for the ARM MPU clock | |
701 | * | |
702 | * Prints a short message to the console with the HFCLKIN oscillator | |
703 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
704 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
705 | * to be handled by the OPP layer code in the near future and should be | |
706 | * removed from the clock code. No return value. | |
707 | */ | |
708 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
709 | const char *core_ck_name, | |
710 | const char *mpu_ck_name) | |
711 | { | |
712 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
713 | unsigned long hfclkin_rate; | |
714 | ||
715 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
716 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
717 | return; | |
718 | ||
719 | core_ck = clk_get(NULL, core_ck_name); | |
720 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
721 | return; | |
722 | ||
723 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
724 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
725 | return; | |
726 | ||
727 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
728 | ||
7852ec05 PW |
729 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
730 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), | |
4d30e82c PW |
731 | (clk_get_rate(core_ck) / 1000000), |
732 | (clk_get_rate(mpu_ck) / 1000000)); | |
733 | } |