Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
543d9378 PW |
18 | #include <linux/list.h> |
19 | #include <linux/errno.h> | |
4d30e82c PW |
20 | #include <linux/err.h> |
21 | #include <linux/delay.h> | |
543d9378 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
fbd3bdb2 | 24 | #include <linux/bitops.h> |
543d9378 | 25 | |
ce491cf8 TL |
26 | #include <plat/clock.h> |
27 | #include <plat/clockdomain.h> | |
28 | #include <plat/cpu.h> | |
29 | #include <plat/prcm.h> | |
543d9378 | 30 | |
543d9378 PW |
31 | #include "clock.h" |
32 | #include "prm.h" | |
33 | #include "prm-regbits-24xx.h" | |
34 | #include "cm.h" | |
35 | #include "cm-regbits-24xx.h" | |
36 | #include "cm-regbits-34xx.h" | |
37 | ||
543d9378 PW |
38 | u8 cpu_mask; |
39 | ||
30962d9d PW |
40 | /* |
41 | * OMAP2+ specific clock functions | |
42 | */ | |
543d9378 | 43 | |
4b1f76ed PW |
44 | /* Private functions */ |
45 | ||
46 | /** | |
47 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
48 | * @clk: struct clk * belonging to the module | |
49 | * | |
50 | * If the necessary clocks for the OMAP hardware IP block that | |
51 | * corresponds to clock @clk are enabled, then wait for the module to | |
52 | * indicate readiness (i.e., to leave IDLE). This code does not | |
53 | * belong in the clock code and will be moved in the medium term to | |
54 | * module-dependent code. No return value. | |
55 | */ | |
56 | static void _omap2_module_wait_ready(struct clk *clk) | |
57 | { | |
58 | void __iomem *companion_reg, *idlest_reg; | |
419cc97d | 59 | u8 other_bit, idlest_bit, idlest_val; |
4b1f76ed PW |
60 | |
61 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
62 | if (clk->ops->find_companion) { | |
63 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
64 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
65 | return; | |
66 | } | |
67 | ||
419cc97d | 68 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
4b1f76ed | 69 | |
419cc97d RL |
70 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
71 | clk->name); | |
4b1f76ed PW |
72 | } |
73 | ||
4b1f76ed PW |
74 | /* Public functions */ |
75 | ||
333943ba PW |
76 | /** |
77 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
78 | * @clk: OMAP clock struct ptr to use | |
79 | * | |
80 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
81 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
82 | * called during clk_register(). No return value. | |
83 | */ | |
84 | void omap2_init_clk_clkdm(struct clk *clk) | |
85 | { | |
86 | struct clockdomain *clkdm; | |
87 | ||
88 | if (!clk->clkdm_name) | |
89 | return; | |
90 | ||
91 | clkdm = clkdm_lookup(clk->clkdm_name); | |
92 | if (clkdm) { | |
93 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
94 | clk->name, clk->clkdm_name); | |
95 | clk->clkdm = clkdm; | |
96 | } else { | |
97 | pr_debug("clock: could not associate clk %s to " | |
98 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
99 | } | |
100 | } | |
101 | ||
543d9378 | 102 | /** |
72350b29 PW |
103 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
104 | * @clk: struct clk * to find the companion clock of | |
105 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
106 | * @other_bit: u8 ** to return the companion clock bit shift in | |
107 | * | |
108 | * Note: We don't need special code here for INVERT_ENABLE for the | |
109 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
110 | * CM_CLKEN_PLL | |
543d9378 | 111 | * |
72350b29 PW |
112 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
113 | * just a matter of XORing the bits. | |
114 | * | |
115 | * Some clocks don't have companion clocks. For example, modules with | |
116 | * only an interface clock (such as MAILBOXES) don't have a companion | |
117 | * clock. Right now, this code relies on the hardware exporting a bit | |
118 | * in the correct companion register that indicates that the | |
119 | * nonexistent 'companion clock' is active. Future patches will | |
120 | * associate this type of code with per-module data structures to | |
121 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 122 | */ |
72350b29 PW |
123 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
124 | u8 *other_bit) | |
543d9378 | 125 | { |
72350b29 | 126 | u32 r; |
543d9378 PW |
127 | |
128 | /* | |
72350b29 PW |
129 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
130 | * it's just a matter of XORing the bits. | |
543d9378 | 131 | */ |
72350b29 | 132 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 133 | |
72350b29 PW |
134 | *other_reg = (__force void __iomem *)r; |
135 | *other_bit = clk->enable_bit; | |
136 | } | |
543d9378 | 137 | |
72350b29 PW |
138 | /** |
139 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
140 | * @clk: struct clk * to find IDLEST info for | |
141 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
142 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
143 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
144 | * |
145 | * Return the CM_IDLEST register address and bit shift corresponding | |
146 | * to the module that "owns" this clock. This default code assumes | |
147 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
148 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
149 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
150 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 151 | */ |
72350b29 | 152 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
419cc97d | 153 | u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 154 | { |
72350b29 | 155 | u32 r; |
543d9378 | 156 | |
72350b29 PW |
157 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
158 | *idlest_reg = (__force void __iomem *)r; | |
159 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
160 | |
161 | /* | |
162 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
163 | * 34xx reverses this, just to keep us on our toes | |
164 | * AM35xx uses both, depending on the module. | |
165 | */ | |
166 | if (cpu_is_omap24xx()) | |
167 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
168 | else if (cpu_is_omap34xx()) | |
169 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
170 | else | |
171 | BUG(); | |
172 | ||
72350b29 | 173 | } |
543d9378 | 174 | |
72350b29 | 175 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 176 | { |
ee1eec36 | 177 | u32 v; |
543d9378 | 178 | |
c0fc18c5 | 179 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 180 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
181 | clk->name); |
182 | return 0; /* REVISIT: -EINVAL */ | |
183 | } | |
184 | ||
ee1eec36 | 185 | v = __raw_readl(clk->enable_reg); |
543d9378 | 186 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 187 | v &= ~(1 << clk->enable_bit); |
543d9378 | 188 | else |
ee1eec36 PW |
189 | v |= (1 << clk->enable_bit); |
190 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 191 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 192 | |
72350b29 | 193 | if (clk->ops->find_idlest) |
4b1f76ed | 194 | _omap2_module_wait_ready(clk); |
543d9378 | 195 | |
72350b29 | 196 | return 0; |
bc51da4e RK |
197 | } |
198 | ||
72350b29 | 199 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 200 | { |
ee1eec36 | 201 | u32 v; |
543d9378 | 202 | |
fecb494b | 203 | if (!clk->enable_reg) { |
543d9378 PW |
204 | /* |
205 | * 'Independent' here refers to a clock which is not | |
206 | * controlled by its parent. | |
207 | */ | |
208 | printk(KERN_ERR "clock: clk_disable called on independent " | |
209 | "clock %s which has no enable_reg\n", clk->name); | |
210 | return; | |
211 | } | |
212 | ||
ee1eec36 | 213 | v = __raw_readl(clk->enable_reg); |
543d9378 | 214 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 215 | v |= (1 << clk->enable_bit); |
543d9378 | 216 | else |
ee1eec36 PW |
217 | v &= ~(1 << clk->enable_bit); |
218 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 219 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
220 | } |
221 | ||
b36ee724 | 222 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 223 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 224 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
225 | .find_companion = omap2_clk_dflt_find_companion, |
226 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
227 | }; |
228 | ||
bc51da4e RK |
229 | const struct clkops clkops_omap2_dflt = { |
230 | .enable = omap2_dflt_clk_enable, | |
231 | .disable = omap2_dflt_clk_disable, | |
232 | }; | |
233 | ||
30962d9d PW |
234 | /** |
235 | * omap2_clk_disable - disable a clock, if the system is not using it | |
236 | * @clk: struct clk * to disable | |
237 | * | |
238 | * Decrements the usecount on struct clk @clk. If there are no users | |
239 | * left, call the clkops-specific clock disable function to disable it | |
240 | * in hardware. If the clock is part of a clockdomain (which they all | |
241 | * should be), request that the clockdomain be disabled. (It too has | |
242 | * a usecount, and so will not be disabled in the hardware until it no | |
243 | * longer has any users.) If the clock has a parent clock (most of | |
244 | * them do), then call ourselves, recursing on the parent clock. This | |
245 | * can cause an entire branch of the clock tree to be powered off by | |
246 | * simply disabling one clock. Intended to be called with the clockfw_lock | |
247 | * spinlock held. No return value. | |
248 | */ | |
543d9378 PW |
249 | void omap2_clk_disable(struct clk *clk) |
250 | { | |
30962d9d PW |
251 | if (clk->usecount == 0) { |
252 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " | |
253 | "already 0?", clk->name); | |
254 | return; | |
543d9378 | 255 | } |
30962d9d PW |
256 | |
257 | pr_debug("clock: %s: decrementing usecount\n", clk->name); | |
258 | ||
259 | clk->usecount--; | |
260 | ||
261 | if (clk->usecount > 0) | |
262 | return; | |
263 | ||
264 | pr_debug("clock: %s: disabling in hardware\n", clk->name); | |
265 | ||
266 | clk->ops->disable(clk); | |
267 | ||
268 | if (clk->clkdm) | |
269 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
270 | ||
271 | if (clk->parent) | |
272 | omap2_clk_disable(clk->parent); | |
543d9378 PW |
273 | } |
274 | ||
30962d9d PW |
275 | /** |
276 | * omap2_clk_enable - request that the system enable a clock | |
277 | * @clk: struct clk * to enable | |
278 | * | |
279 | * Increments the usecount on struct clk @clk. If there were no users | |
280 | * previously, then recurse up the clock tree, enabling all of the | |
281 | * clock's parents and all of the parent clockdomains, and finally, | |
282 | * enabling @clk's clockdomain, and @clk itself. Intended to be | |
283 | * called with the clockfw_lock spinlock held. Returns 0 upon success | |
284 | * or a negative error code upon failure. | |
285 | */ | |
543d9378 PW |
286 | int omap2_clk_enable(struct clk *clk) |
287 | { | |
30962d9d | 288 | int ret; |
543d9378 | 289 | |
30962d9d | 290 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
333943ba | 291 | |
30962d9d PW |
292 | clk->usecount++; |
293 | ||
294 | if (clk->usecount > 1) | |
295 | return 0; | |
333943ba | 296 | |
30962d9d PW |
297 | pr_debug("clock: %s: enabling in hardware\n", clk->name); |
298 | ||
299 | if (clk->parent) { | |
300 | ret = omap2_clk_enable(clk->parent); | |
a7f8c599 | 301 | if (ret) { |
30962d9d PW |
302 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
303 | clk->name, clk->parent->name, ret); | |
304 | goto oce_err1; | |
305 | } | |
306 | } | |
a7f8c599 | 307 | |
30962d9d PW |
308 | if (clk->clkdm) { |
309 | ret = omap2_clkdm_clk_enable(clk->clkdm, clk); | |
310 | if (ret) { | |
311 | WARN(1, "clock: %s: could not enable clockdomain %s: " | |
312 | "%d\n", clk->name, clk->clkdm->name, ret); | |
313 | goto oce_err2; | |
543d9378 PW |
314 | } |
315 | } | |
316 | ||
30962d9d PW |
317 | ret = clk->ops->enable(clk); |
318 | if (ret) { | |
319 | WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); | |
320 | goto oce_err3; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | ||
325 | oce_err3: | |
8263e5b3 RK |
326 | if (clk->clkdm) |
327 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
30962d9d PW |
328 | oce_err2: |
329 | if (clk->parent) | |
330 | omap2_clk_disable(clk->parent); | |
331 | oce_err1: | |
a7f8c599 | 332 | clk->usecount--; |
30962d9d | 333 | |
543d9378 PW |
334 | return ret; |
335 | } | |
336 | ||
435699db PW |
337 | /* Given a clock and a rate apply a clock specific rounding function */ |
338 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |
339 | { | |
340 | if (clk->round_rate) | |
341 | return clk->round_rate(clk, rate); | |
342 | ||
343 | return clk->rate; | |
344 | } | |
345 | ||
543d9378 PW |
346 | /* Set the clock rate for a clock source */ |
347 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
348 | { | |
349 | int ret = -EINVAL; | |
350 | ||
351 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
352 | ||
543d9378 | 353 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
fecb494b | 354 | if (clk->set_rate) |
543d9378 PW |
355 | ret = clk->set_rate(clk, rate); |
356 | ||
543d9378 PW |
357 | return ret; |
358 | } | |
359 | ||
543d9378 PW |
360 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
361 | { | |
543d9378 PW |
362 | if (!clk->clksel) |
363 | return -EINVAL; | |
364 | ||
1a337717 PW |
365 | if (clk->parent == new_parent) |
366 | return 0; | |
367 | ||
df791b3e | 368 | return omap2_clksel_set_parent(clk, new_parent); |
543d9378 PW |
369 | } |
370 | ||
657ebfad PW |
371 | /* OMAP3/4 non-CORE DPLL clkops */ |
372 | ||
373 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | |
374 | ||
375 | const struct clkops clkops_omap3_noncore_dpll_ops = { | |
376 | .enable = omap3_noncore_dpll_enable, | |
377 | .disable = omap3_noncore_dpll_disable, | |
378 | }; | |
379 | ||
380 | #endif | |
381 | ||
382 | ||
30962d9d PW |
383 | /* |
384 | * OMAP2+ clock reset and init functions | |
385 | */ | |
543d9378 PW |
386 | |
387 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
388 | void omap2_clk_disable_unused(struct clk *clk) | |
389 | { | |
390 | u32 regval32, v; | |
391 | ||
392 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
393 | ||
394 | regval32 = __raw_readl(clk->enable_reg); | |
395 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
396 | return; | |
397 | ||
0db4e825 | 398 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
399 | if (cpu_is_omap34xx()) { |
400 | omap2_clk_enable(clk); | |
401 | omap2_clk_disable(clk); | |
30962d9d PW |
402 | } else { |
403 | clk->ops->disable(clk); | |
404 | } | |
fe617af7 PDS |
405 | if (clk->clkdm != NULL) |
406 | pwrdm_clkdm_state_switch(clk->clkdm); | |
543d9378 PW |
407 | } |
408 | #endif | |
69ecefca | 409 | |
4d30e82c PW |
410 | /** |
411 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
412 | * @mpurate_ck_name: clk name of the clock to change rate | |
413 | * | |
414 | * Change the ARM MPU clock rate to the rate specified on the command | |
415 | * line, if one was specified. @mpurate_ck_name should be | |
416 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
417 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
418 | * handled by the virt_prcm_set clock, but this should be handled by | |
419 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
420 | * code in the near future and should be removed from the clock code. | |
421 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
422 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
423 | * cannot be found, or 0 upon success. | |
424 | */ | |
425 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
426 | { | |
427 | struct clk *mpurate_ck; | |
428 | int r; | |
429 | ||
430 | if (!mpurate) | |
431 | return -EINVAL; | |
432 | ||
433 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
434 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
435 | return -ENOENT; | |
436 | ||
437 | r = clk_set_rate(mpurate_ck, mpurate); | |
438 | if (IS_ERR_VALUE(r)) { | |
439 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", | |
440 | mpurate_ck->name, mpurate, r); | |
441 | return -EINVAL; | |
442 | } | |
443 | ||
444 | calibrate_delay(); | |
445 | recalculate_root_clocks(); | |
446 | ||
447 | clk_put(mpurate_ck); | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
454 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
455 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
456 | * @mpu_ck_name: clk name for the ARM MPU clock | |
457 | * | |
458 | * Prints a short message to the console with the HFCLKIN oscillator | |
459 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
460 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
461 | * to be handled by the OPP layer code in the near future and should be | |
462 | * removed from the clock code. No return value. | |
463 | */ | |
464 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
465 | const char *core_ck_name, | |
466 | const char *mpu_ck_name) | |
467 | { | |
468 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
469 | unsigned long hfclkin_rate; | |
470 | ||
471 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
472 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
473 | return; | |
474 | ||
475 | core_ck = clk_get(NULL, core_ck_name); | |
476 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
477 | return; | |
478 | ||
479 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
480 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
481 | return; | |
482 | ||
483 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
484 | ||
485 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " | |
486 | "%ld.%01ld/%ld/%ld MHz\n", | |
487 | (hfclkin_rate / 1000000), | |
488 | ((hfclkin_rate / 100000) % 10), | |
489 | (clk_get_rate(core_ck) / 1000000), | |
490 | (clk_get_rate(mpu_ck) / 1000000)); | |
491 | } | |
492 | ||
69ecefca PW |
493 | /* Common data */ |
494 | ||
495 | struct clk_functions omap2_clk_functions = { | |
496 | .clk_enable = omap2_clk_enable, | |
497 | .clk_disable = omap2_clk_disable, | |
498 | .clk_round_rate = omap2_clk_round_rate, | |
499 | .clk_set_rate = omap2_clk_set_rate, | |
500 | .clk_set_parent = omap2_clk_set_parent, | |
501 | .clk_disable_unused = omap2_clk_disable_unused, | |
502 | #ifdef CONFIG_CPU_FREQ | |
503 | /* These will be removed when the OPP code is integrated */ | |
504 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | |
505 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | |
506 | #endif | |
507 | }; | |
508 |