Commit | Line | Data |
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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
543d9378 | 17 | #include <linux/kernel.h> |
543d9378 PW |
18 | #include <linux/list.h> |
19 | #include <linux/errno.h> | |
4d30e82c PW |
20 | #include <linux/err.h> |
21 | #include <linux/delay.h> | |
543d9378 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
fbd3bdb2 | 24 | #include <linux/bitops.h> |
543d9378 | 25 | |
5e7c58dc | 26 | #include <asm/cpu.h> |
dbc04161 | 27 | |
ce491cf8 | 28 | #include <plat/clock.h> |
ce491cf8 | 29 | #include <plat/prcm.h> |
543d9378 | 30 | |
dbc04161 TL |
31 | #include <trace/events/power.h> |
32 | ||
33 | #include "soc.h" | |
34 | #include "clockdomain.h" | |
543d9378 | 35 | #include "clock.h" |
59fb659b | 36 | #include "cm2xxx_3xxx.h" |
543d9378 PW |
37 | #include "cm-regbits-24xx.h" |
38 | #include "cm-regbits-34xx.h" | |
39 | ||
99541195 | 40 | u16 cpu_mask; |
543d9378 | 41 | |
12706c54 PW |
42 | /* |
43 | * clkdm_control: if true, then when a clock is enabled in the | |
44 | * hardware, its clockdomain will first be enabled; and when a clock | |
45 | * is disabled in the hardware, its clockdomain will be disabled | |
46 | * afterwards. | |
47 | */ | |
48 | static bool clkdm_control = true; | |
49 | ||
30962d9d PW |
50 | /* |
51 | * OMAP2+ specific clock functions | |
52 | */ | |
543d9378 | 53 | |
4b1f76ed PW |
54 | /* Private functions */ |
55 | ||
56 | /** | |
57 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
58 | * @clk: struct clk * belonging to the module | |
59 | * | |
60 | * If the necessary clocks for the OMAP hardware IP block that | |
61 | * corresponds to clock @clk are enabled, then wait for the module to | |
62 | * indicate readiness (i.e., to leave IDLE). This code does not | |
63 | * belong in the clock code and will be moved in the medium term to | |
64 | * module-dependent code. No return value. | |
65 | */ | |
66 | static void _omap2_module_wait_ready(struct clk *clk) | |
67 | { | |
68 | void __iomem *companion_reg, *idlest_reg; | |
419cc97d | 69 | u8 other_bit, idlest_bit, idlest_val; |
4b1f76ed PW |
70 | |
71 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
72 | if (clk->ops->find_companion) { | |
73 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
74 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
75 | return; | |
76 | } | |
77 | ||
419cc97d | 78 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
4b1f76ed | 79 | |
419cc97d | 80 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
5dcc3b97 | 81 | __clk_get_name(clk)); |
4b1f76ed PW |
82 | } |
83 | ||
4b1f76ed PW |
84 | /* Public functions */ |
85 | ||
333943ba PW |
86 | /** |
87 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
88 | * @clk: OMAP clock struct ptr to use | |
89 | * | |
90 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
91 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
92 | * called during clk_register(). No return value. | |
93 | */ | |
94 | void omap2_init_clk_clkdm(struct clk *clk) | |
95 | { | |
96 | struct clockdomain *clkdm; | |
5dcc3b97 | 97 | const char *clk_name; |
333943ba PW |
98 | |
99 | if (!clk->clkdm_name) | |
100 | return; | |
101 | ||
5dcc3b97 RN |
102 | clk_name = __clk_get_name(clk); |
103 | ||
333943ba PW |
104 | clkdm = clkdm_lookup(clk->clkdm_name); |
105 | if (clkdm) { | |
106 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
5dcc3b97 | 107 | clk_name, clk->clkdm_name); |
333943ba PW |
108 | clk->clkdm = clkdm; |
109 | } else { | |
7852ec05 | 110 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
5dcc3b97 | 111 | clk_name, clk->clkdm_name); |
333943ba PW |
112 | } |
113 | } | |
114 | ||
12706c54 PW |
115 | /** |
116 | * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable | |
117 | * | |
118 | * Prevent the OMAP clock code from calling into the clockdomain code | |
119 | * when a hardware clock in that clockdomain is enabled or disabled. | |
120 | * Intended to be called at init time from omap*_clk_init(). No | |
121 | * return value. | |
122 | */ | |
123 | void __init omap2_clk_disable_clkdm_control(void) | |
124 | { | |
125 | clkdm_control = false; | |
126 | } | |
127 | ||
543d9378 | 128 | /** |
72350b29 PW |
129 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
130 | * @clk: struct clk * to find the companion clock of | |
131 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
132 | * @other_bit: u8 ** to return the companion clock bit shift in | |
133 | * | |
134 | * Note: We don't need special code here for INVERT_ENABLE for the | |
135 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
136 | * CM_CLKEN_PLL | |
543d9378 | 137 | * |
72350b29 PW |
138 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
139 | * just a matter of XORing the bits. | |
140 | * | |
141 | * Some clocks don't have companion clocks. For example, modules with | |
142 | * only an interface clock (such as MAILBOXES) don't have a companion | |
143 | * clock. Right now, this code relies on the hardware exporting a bit | |
144 | * in the correct companion register that indicates that the | |
145 | * nonexistent 'companion clock' is active. Future patches will | |
146 | * associate this type of code with per-module data structures to | |
147 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 148 | */ |
72350b29 PW |
149 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
150 | u8 *other_bit) | |
543d9378 | 151 | { |
72350b29 | 152 | u32 r; |
543d9378 PW |
153 | |
154 | /* | |
72350b29 PW |
155 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
156 | * it's just a matter of XORing the bits. | |
543d9378 | 157 | */ |
72350b29 | 158 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 159 | |
72350b29 PW |
160 | *other_reg = (__force void __iomem *)r; |
161 | *other_bit = clk->enable_bit; | |
162 | } | |
543d9378 | 163 | |
72350b29 PW |
164 | /** |
165 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
166 | * @clk: struct clk * to find IDLEST info for | |
167 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
168 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
169 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
170 | * |
171 | * Return the CM_IDLEST register address and bit shift corresponding | |
172 | * to the module that "owns" this clock. This default code assumes | |
173 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
174 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
175 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
176 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 177 | */ |
72350b29 | 178 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
419cc97d | 179 | u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 180 | { |
72350b29 | 181 | u32 r; |
543d9378 | 182 | |
72350b29 PW |
183 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
184 | *idlest_reg = (__force void __iomem *)r; | |
185 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
186 | |
187 | /* | |
188 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
189 | * 34xx reverses this, just to keep us on our toes | |
190 | * AM35xx uses both, depending on the module. | |
191 | */ | |
192 | if (cpu_is_omap24xx()) | |
193 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
194 | else if (cpu_is_omap34xx()) | |
195 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
196 | else | |
197 | BUG(); | |
198 | ||
72350b29 | 199 | } |
543d9378 | 200 | |
72350b29 | 201 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 202 | { |
ee1eec36 | 203 | u32 v; |
543d9378 | 204 | |
c0fc18c5 | 205 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 206 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
207 | clk->name); |
208 | return 0; /* REVISIT: -EINVAL */ | |
209 | } | |
210 | ||
ee1eec36 | 211 | v = __raw_readl(clk->enable_reg); |
543d9378 | 212 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 213 | v &= ~(1 << clk->enable_bit); |
543d9378 | 214 | else |
ee1eec36 PW |
215 | v |= (1 << clk->enable_bit); |
216 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 217 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 218 | |
72350b29 | 219 | if (clk->ops->find_idlest) |
4b1f76ed | 220 | _omap2_module_wait_ready(clk); |
543d9378 | 221 | |
72350b29 | 222 | return 0; |
bc51da4e RK |
223 | } |
224 | ||
72350b29 | 225 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 226 | { |
ee1eec36 | 227 | u32 v; |
543d9378 | 228 | |
fecb494b | 229 | if (!clk->enable_reg) { |
543d9378 PW |
230 | /* |
231 | * 'Independent' here refers to a clock which is not | |
232 | * controlled by its parent. | |
233 | */ | |
7852ec05 | 234 | pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); |
543d9378 PW |
235 | return; |
236 | } | |
237 | ||
ee1eec36 | 238 | v = __raw_readl(clk->enable_reg); |
543d9378 | 239 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 240 | v |= (1 << clk->enable_bit); |
543d9378 | 241 | else |
ee1eec36 PW |
242 | v &= ~(1 << clk->enable_bit); |
243 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 244 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
245 | } |
246 | ||
b36ee724 | 247 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 248 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 249 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
250 | .find_companion = omap2_clk_dflt_find_companion, |
251 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
252 | }; |
253 | ||
bc51da4e RK |
254 | const struct clkops clkops_omap2_dflt = { |
255 | .enable = omap2_dflt_clk_enable, | |
256 | .disable = omap2_dflt_clk_disable, | |
257 | }; | |
258 | ||
30962d9d PW |
259 | /** |
260 | * omap2_clk_disable - disable a clock, if the system is not using it | |
261 | * @clk: struct clk * to disable | |
262 | * | |
263 | * Decrements the usecount on struct clk @clk. If there are no users | |
264 | * left, call the clkops-specific clock disable function to disable it | |
265 | * in hardware. If the clock is part of a clockdomain (which they all | |
266 | * should be), request that the clockdomain be disabled. (It too has | |
267 | * a usecount, and so will not be disabled in the hardware until it no | |
268 | * longer has any users.) If the clock has a parent clock (most of | |
269 | * them do), then call ourselves, recursing on the parent clock. This | |
270 | * can cause an entire branch of the clock tree to be powered off by | |
271 | * simply disabling one clock. Intended to be called with the clockfw_lock | |
272 | * spinlock held. No return value. | |
273 | */ | |
543d9378 PW |
274 | void omap2_clk_disable(struct clk *clk) |
275 | { | |
30962d9d | 276 | if (clk->usecount == 0) { |
7852ec05 | 277 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); |
30962d9d | 278 | return; |
543d9378 | 279 | } |
30962d9d PW |
280 | |
281 | pr_debug("clock: %s: decrementing usecount\n", clk->name); | |
282 | ||
283 | clk->usecount--; | |
284 | ||
285 | if (clk->usecount > 0) | |
286 | return; | |
287 | ||
288 | pr_debug("clock: %s: disabling in hardware\n", clk->name); | |
289 | ||
5e7c58dc JP |
290 | if (clk->ops && clk->ops->disable) { |
291 | trace_clock_disable(clk->name, 0, smp_processor_id()); | |
6c52f32d | 292 | clk->ops->disable(clk); |
5e7c58dc | 293 | } |
30962d9d | 294 | |
12706c54 | 295 | if (clkdm_control && clk->clkdm) |
4da71ae6 | 296 | clkdm_clk_disable(clk->clkdm, clk); |
30962d9d PW |
297 | |
298 | if (clk->parent) | |
299 | omap2_clk_disable(clk->parent); | |
543d9378 PW |
300 | } |
301 | ||
30962d9d PW |
302 | /** |
303 | * omap2_clk_enable - request that the system enable a clock | |
304 | * @clk: struct clk * to enable | |
305 | * | |
306 | * Increments the usecount on struct clk @clk. If there were no users | |
307 | * previously, then recurse up the clock tree, enabling all of the | |
308 | * clock's parents and all of the parent clockdomains, and finally, | |
309 | * enabling @clk's clockdomain, and @clk itself. Intended to be | |
310 | * called with the clockfw_lock spinlock held. Returns 0 upon success | |
311 | * or a negative error code upon failure. | |
312 | */ | |
543d9378 PW |
313 | int omap2_clk_enable(struct clk *clk) |
314 | { | |
30962d9d | 315 | int ret; |
543d9378 | 316 | |
30962d9d | 317 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
333943ba | 318 | |
30962d9d PW |
319 | clk->usecount++; |
320 | ||
321 | if (clk->usecount > 1) | |
322 | return 0; | |
333943ba | 323 | |
30962d9d PW |
324 | pr_debug("clock: %s: enabling in hardware\n", clk->name); |
325 | ||
326 | if (clk->parent) { | |
327 | ret = omap2_clk_enable(clk->parent); | |
a7f8c599 | 328 | if (ret) { |
30962d9d PW |
329 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
330 | clk->name, clk->parent->name, ret); | |
331 | goto oce_err1; | |
332 | } | |
333 | } | |
a7f8c599 | 334 | |
12706c54 | 335 | if (clkdm_control && clk->clkdm) { |
4da71ae6 | 336 | ret = clkdm_clk_enable(clk->clkdm, clk); |
30962d9d | 337 | if (ret) { |
7852ec05 PW |
338 | WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", |
339 | clk->name, clk->clkdm->name, ret); | |
30962d9d | 340 | goto oce_err2; |
543d9378 PW |
341 | } |
342 | } | |
343 | ||
6c52f32d | 344 | if (clk->ops && clk->ops->enable) { |
5e7c58dc | 345 | trace_clock_enable(clk->name, 1, smp_processor_id()); |
6c52f32d RN |
346 | ret = clk->ops->enable(clk); |
347 | if (ret) { | |
348 | WARN(1, "clock: %s: could not enable: %d\n", | |
349 | clk->name, ret); | |
350 | goto oce_err3; | |
351 | } | |
30962d9d PW |
352 | } |
353 | ||
354 | return 0; | |
355 | ||
356 | oce_err3: | |
12706c54 | 357 | if (clkdm_control && clk->clkdm) |
4da71ae6 | 358 | clkdm_clk_disable(clk->clkdm, clk); |
30962d9d PW |
359 | oce_err2: |
360 | if (clk->parent) | |
361 | omap2_clk_disable(clk->parent); | |
362 | oce_err1: | |
a7f8c599 | 363 | clk->usecount--; |
30962d9d | 364 | |
543d9378 PW |
365 | return ret; |
366 | } | |
367 | ||
435699db PW |
368 | /* Given a clock and a rate apply a clock specific rounding function */ |
369 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |
370 | { | |
371 | if (clk->round_rate) | |
372 | return clk->round_rate(clk, rate); | |
373 | ||
374 | return clk->rate; | |
375 | } | |
376 | ||
543d9378 PW |
377 | /* Set the clock rate for a clock source */ |
378 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
379 | { | |
380 | int ret = -EINVAL; | |
381 | ||
382 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
383 | ||
543d9378 | 384 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
5e7c58dc JP |
385 | if (clk->set_rate) { |
386 | trace_clock_set_rate(clk->name, rate, smp_processor_id()); | |
543d9378 | 387 | ret = clk->set_rate(clk, rate); |
5e7c58dc | 388 | } |
543d9378 | 389 | |
543d9378 PW |
390 | return ret; |
391 | } | |
392 | ||
543d9378 PW |
393 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
394 | { | |
543d9378 PW |
395 | if (!clk->clksel) |
396 | return -EINVAL; | |
397 | ||
1a337717 PW |
398 | if (clk->parent == new_parent) |
399 | return 0; | |
400 | ||
df791b3e | 401 | return omap2_clksel_set_parent(clk, new_parent); |
543d9378 PW |
402 | } |
403 | ||
30962d9d PW |
404 | /* |
405 | * OMAP2+ clock reset and init functions | |
406 | */ | |
543d9378 PW |
407 | |
408 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
409 | void omap2_clk_disable_unused(struct clk *clk) | |
410 | { | |
411 | u32 regval32, v; | |
412 | ||
413 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
414 | ||
415 | regval32 = __raw_readl(clk->enable_reg); | |
416 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
417 | return; | |
418 | ||
6041c27f | 419 | pr_debug("Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
420 | if (cpu_is_omap34xx()) { |
421 | omap2_clk_enable(clk); | |
422 | omap2_clk_disable(clk); | |
30962d9d PW |
423 | } else { |
424 | clk->ops->disable(clk); | |
425 | } | |
fe617af7 | 426 | if (clk->clkdm != NULL) |
5a68a736 | 427 | pwrdm_state_switch(clk->clkdm->pwrdm.ptr); |
543d9378 PW |
428 | } |
429 | #endif | |
69ecefca | 430 | |
4d30e82c PW |
431 | /** |
432 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | |
433 | * @mpurate_ck_name: clk name of the clock to change rate | |
434 | * | |
435 | * Change the ARM MPU clock rate to the rate specified on the command | |
436 | * line, if one was specified. @mpurate_ck_name should be | |
437 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. | |
438 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently | |
439 | * handled by the virt_prcm_set clock, but this should be handled by | |
440 | * the OPP layer. XXX This is intended to be handled by the OPP layer | |
441 | * code in the near future and should be removed from the clock code. | |
442 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects | |
443 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name | |
444 | * cannot be found, or 0 upon success. | |
445 | */ | |
446 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |
447 | { | |
448 | struct clk *mpurate_ck; | |
449 | int r; | |
450 | ||
451 | if (!mpurate) | |
452 | return -EINVAL; | |
453 | ||
454 | mpurate_ck = clk_get(NULL, mpurate_ck_name); | |
455 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) | |
456 | return -ENOENT; | |
457 | ||
458 | r = clk_set_rate(mpurate_ck, mpurate); | |
459 | if (IS_ERR_VALUE(r)) { | |
460 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", | |
461 | mpurate_ck->name, mpurate, r); | |
f6281f66 | 462 | clk_put(mpurate_ck); |
4d30e82c PW |
463 | return -EINVAL; |
464 | } | |
465 | ||
466 | calibrate_delay(); | |
467 | recalculate_root_clocks(); | |
468 | ||
469 | clk_put(mpurate_ck); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | /** | |
475 | * omap2_clk_print_new_rates - print summary of current clock tree rates | |
476 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator | |
477 | * @core_ck_name: clk name for the on-chip CORE_CLK | |
478 | * @mpu_ck_name: clk name for the ARM MPU clock | |
479 | * | |
480 | * Prints a short message to the console with the HFCLKIN oscillator | |
481 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. | |
482 | * Called by the boot-time MPU rate switching code. XXX This is intended | |
483 | * to be handled by the OPP layer code in the near future and should be | |
484 | * removed from the clock code. No return value. | |
485 | */ | |
486 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
487 | const char *core_ck_name, | |
488 | const char *mpu_ck_name) | |
489 | { | |
490 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; | |
491 | unsigned long hfclkin_rate; | |
492 | ||
493 | mpu_ck = clk_get(NULL, mpu_ck_name); | |
494 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) | |
495 | return; | |
496 | ||
497 | core_ck = clk_get(NULL, core_ck_name); | |
498 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) | |
499 | return; | |
500 | ||
501 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); | |
502 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) | |
503 | return; | |
504 | ||
505 | hfclkin_rate = clk_get_rate(hfclkin_ck); | |
506 | ||
7852ec05 PW |
507 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
508 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), | |
4d30e82c PW |
509 | (clk_get_rate(core_ck) / 1000000), |
510 | (clk_get_rate(mpu_ck) / 1000000)); | |
511 | } | |
512 | ||
69ecefca PW |
513 | /* Common data */ |
514 | ||
515 | struct clk_functions omap2_clk_functions = { | |
516 | .clk_enable = omap2_clk_enable, | |
517 | .clk_disable = omap2_clk_disable, | |
518 | .clk_round_rate = omap2_clk_round_rate, | |
519 | .clk_set_rate = omap2_clk_set_rate, | |
520 | .clk_set_parent = omap2_clk_set_parent, | |
521 | .clk_disable_unused = omap2_clk_disable_unused, | |
69ecefca PW |
522 | }; |
523 |