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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
543d9378 | 26 | |
ce491cf8 TL |
27 | #include <plat/clock.h> |
28 | #include <plat/clockdomain.h> | |
29 | #include <plat/cpu.h> | |
30 | #include <plat/prcm.h> | |
543d9378 | 31 | |
543d9378 PW |
32 | #include "clock.h" |
33 | #include "prm.h" | |
34 | #include "prm-regbits-24xx.h" | |
35 | #include "cm.h" | |
36 | #include "cm-regbits-24xx.h" | |
37 | #include "cm-regbits-34xx.h" | |
38 | ||
543d9378 PW |
39 | u8 cpu_mask; |
40 | ||
41 | /*------------------------------------------------------------------------- | |
911bd739 | 42 | * OMAP2/3/4 specific clock functions |
543d9378 PW |
43 | *-------------------------------------------------------------------------*/ |
44 | ||
4b1f76ed PW |
45 | /* Private functions */ |
46 | ||
47 | /** | |
48 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
49 | * @clk: struct clk * belonging to the module | |
50 | * | |
51 | * If the necessary clocks for the OMAP hardware IP block that | |
52 | * corresponds to clock @clk are enabled, then wait for the module to | |
53 | * indicate readiness (i.e., to leave IDLE). This code does not | |
54 | * belong in the clock code and will be moved in the medium term to | |
55 | * module-dependent code. No return value. | |
56 | */ | |
57 | static void _omap2_module_wait_ready(struct clk *clk) | |
58 | { | |
59 | void __iomem *companion_reg, *idlest_reg; | |
419cc97d | 60 | u8 other_bit, idlest_bit, idlest_val; |
4b1f76ed PW |
61 | |
62 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
63 | if (clk->ops->find_companion) { | |
64 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
65 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
66 | return; | |
67 | } | |
68 | ||
419cc97d | 69 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
4b1f76ed | 70 | |
419cc97d RL |
71 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
72 | clk->name); | |
4b1f76ed PW |
73 | } |
74 | ||
75 | /* Enables clock without considering parent dependencies or use count | |
76 | * REVISIT: Maybe change this to use clk->enable like on omap1? | |
77 | */ | |
78 | static int _omap2_clk_enable(struct clk *clk) | |
79 | { | |
80 | return clk->ops->enable(clk); | |
81 | } | |
82 | ||
83 | /* Disables clock without considering parent dependencies or use count */ | |
84 | static void _omap2_clk_disable(struct clk *clk) | |
85 | { | |
86 | clk->ops->disable(clk); | |
87 | } | |
88 | ||
89 | /* Public functions */ | |
90 | ||
439764cc | 91 | /** |
df791b3e | 92 | * omap2xxx_clk_commit - commit clock parent/rate changes in hardware |
439764cc PW |
93 | * @clk: struct clk * |
94 | * | |
95 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | |
96 | * don't take effect until the VALID_CONFIG bit is written, write the | |
97 | * VALID_CONFIG bit and wait for the write to complete. No return value. | |
98 | */ | |
df791b3e | 99 | void omap2xxx_clk_commit(struct clk *clk) |
439764cc PW |
100 | { |
101 | if (!cpu_is_omap24xx()) | |
102 | return; | |
103 | ||
104 | if (!(clk->flags & DELAYED_APP)) | |
105 | return; | |
106 | ||
107 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | |
8e3bd351 | 108 | OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc | 109 | /* OCP barrier */ |
8e3bd351 | 110 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc PW |
111 | } |
112 | ||
333943ba PW |
113 | /** |
114 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
115 | * @clk: OMAP clock struct ptr to use | |
116 | * | |
117 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
118 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
119 | * called during clk_register(). No return value. | |
120 | */ | |
121 | void omap2_init_clk_clkdm(struct clk *clk) | |
122 | { | |
123 | struct clockdomain *clkdm; | |
124 | ||
125 | if (!clk->clkdm_name) | |
126 | return; | |
127 | ||
128 | clkdm = clkdm_lookup(clk->clkdm_name); | |
129 | if (clkdm) { | |
130 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
131 | clk->name, clk->clkdm_name); | |
132 | clk->clkdm = clkdm; | |
133 | } else { | |
134 | pr_debug("clock: could not associate clk %s to " | |
135 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
136 | } | |
137 | } | |
138 | ||
543d9378 | 139 | /** |
72350b29 PW |
140 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
141 | * @clk: struct clk * to find the companion clock of | |
142 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
143 | * @other_bit: u8 ** to return the companion clock bit shift in | |
144 | * | |
145 | * Note: We don't need special code here for INVERT_ENABLE for the | |
146 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
147 | * CM_CLKEN_PLL | |
543d9378 | 148 | * |
72350b29 PW |
149 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
150 | * just a matter of XORing the bits. | |
151 | * | |
152 | * Some clocks don't have companion clocks. For example, modules with | |
153 | * only an interface clock (such as MAILBOXES) don't have a companion | |
154 | * clock. Right now, this code relies on the hardware exporting a bit | |
155 | * in the correct companion register that indicates that the | |
156 | * nonexistent 'companion clock' is active. Future patches will | |
157 | * associate this type of code with per-module data structures to | |
158 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 159 | */ |
72350b29 PW |
160 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
161 | u8 *other_bit) | |
543d9378 | 162 | { |
72350b29 | 163 | u32 r; |
543d9378 PW |
164 | |
165 | /* | |
72350b29 PW |
166 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
167 | * it's just a matter of XORing the bits. | |
543d9378 | 168 | */ |
72350b29 | 169 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 170 | |
72350b29 PW |
171 | *other_reg = (__force void __iomem *)r; |
172 | *other_bit = clk->enable_bit; | |
173 | } | |
543d9378 | 174 | |
72350b29 PW |
175 | /** |
176 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
177 | * @clk: struct clk * to find IDLEST info for | |
178 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
419cc97d RL |
179 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
180 | * @idlest_val: u8 * to return the idle status indicator | |
72350b29 PW |
181 | * |
182 | * Return the CM_IDLEST register address and bit shift corresponding | |
183 | * to the module that "owns" this clock. This default code assumes | |
184 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
185 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
186 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
187 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 188 | */ |
72350b29 | 189 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
419cc97d | 190 | u8 *idlest_bit, u8 *idlest_val) |
543d9378 | 191 | { |
72350b29 | 192 | u32 r; |
543d9378 | 193 | |
72350b29 PW |
194 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
195 | *idlest_reg = (__force void __iomem *)r; | |
196 | *idlest_bit = clk->enable_bit; | |
419cc97d RL |
197 | |
198 | /* | |
199 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
200 | * 34xx reverses this, just to keep us on our toes | |
201 | * AM35xx uses both, depending on the module. | |
202 | */ | |
203 | if (cpu_is_omap24xx()) | |
204 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | |
205 | else if (cpu_is_omap34xx()) | |
206 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | |
207 | else | |
208 | BUG(); | |
209 | ||
72350b29 | 210 | } |
543d9378 | 211 | |
72350b29 | 212 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 213 | { |
ee1eec36 | 214 | u32 v; |
543d9378 | 215 | |
c0fc18c5 | 216 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 217 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
218 | clk->name); |
219 | return 0; /* REVISIT: -EINVAL */ | |
220 | } | |
221 | ||
ee1eec36 | 222 | v = __raw_readl(clk->enable_reg); |
543d9378 | 223 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 224 | v &= ~(1 << clk->enable_bit); |
543d9378 | 225 | else |
ee1eec36 PW |
226 | v |= (1 << clk->enable_bit); |
227 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 228 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 229 | |
72350b29 | 230 | if (clk->ops->find_idlest) |
4b1f76ed | 231 | _omap2_module_wait_ready(clk); |
543d9378 | 232 | |
72350b29 | 233 | return 0; |
bc51da4e RK |
234 | } |
235 | ||
72350b29 | 236 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 237 | { |
ee1eec36 | 238 | u32 v; |
543d9378 | 239 | |
fecb494b | 240 | if (!clk->enable_reg) { |
543d9378 PW |
241 | /* |
242 | * 'Independent' here refers to a clock which is not | |
243 | * controlled by its parent. | |
244 | */ | |
245 | printk(KERN_ERR "clock: clk_disable called on independent " | |
246 | "clock %s which has no enable_reg\n", clk->name); | |
247 | return; | |
248 | } | |
249 | ||
ee1eec36 | 250 | v = __raw_readl(clk->enable_reg); |
543d9378 | 251 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 252 | v |= (1 << clk->enable_bit); |
543d9378 | 253 | else |
ee1eec36 PW |
254 | v &= ~(1 << clk->enable_bit); |
255 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 256 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
257 | } |
258 | ||
b36ee724 | 259 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 260 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 261 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
262 | .find_companion = omap2_clk_dflt_find_companion, |
263 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
264 | }; |
265 | ||
bc51da4e RK |
266 | const struct clkops clkops_omap2_dflt = { |
267 | .enable = omap2_dflt_clk_enable, | |
268 | .disable = omap2_dflt_clk_disable, | |
269 | }; | |
270 | ||
543d9378 PW |
271 | void omap2_clk_disable(struct clk *clk) |
272 | { | |
273 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
274 | _omap2_clk_disable(clk); | |
fecb494b | 275 | if (clk->parent) |
543d9378 | 276 | omap2_clk_disable(clk->parent); |
333943ba PW |
277 | if (clk->clkdm) |
278 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
279 | ||
543d9378 PW |
280 | } |
281 | } | |
282 | ||
283 | int omap2_clk_enable(struct clk *clk) | |
284 | { | |
285 | int ret = 0; | |
286 | ||
287 | if (clk->usecount++ == 0) { | |
333943ba PW |
288 | if (clk->clkdm) |
289 | omap2_clkdm_clk_enable(clk->clkdm, clk); | |
290 | ||
a7f8c599 | 291 | if (clk->parent) { |
543d9378 | 292 | ret = omap2_clk_enable(clk->parent); |
a7f8c599 RK |
293 | if (ret) |
294 | goto err; | |
543d9378 | 295 | } |
333943ba | 296 | |
543d9378 | 297 | ret = _omap2_clk_enable(clk); |
a7f8c599 | 298 | if (ret) { |
a7f8c599 | 299 | if (clk->parent) |
333943ba | 300 | omap2_clk_disable(clk->parent); |
a7f8c599 RK |
301 | |
302 | goto err; | |
543d9378 PW |
303 | } |
304 | } | |
a7f8c599 | 305 | return ret; |
543d9378 | 306 | |
a7f8c599 | 307 | err: |
8263e5b3 RK |
308 | if (clk->clkdm) |
309 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
a7f8c599 | 310 | clk->usecount--; |
543d9378 PW |
311 | return ret; |
312 | } | |
313 | ||
543d9378 PW |
314 | /* Set the clock rate for a clock source */ |
315 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
316 | { | |
317 | int ret = -EINVAL; | |
318 | ||
319 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
320 | ||
321 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | |
322 | rate table mechanism, driven by mpu_speed */ | |
323 | if (clk->flags & CONFIG_PARTICIPANT) | |
324 | return -EINVAL; | |
325 | ||
326 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | |
fecb494b | 327 | if (clk->set_rate) |
543d9378 PW |
328 | ret = clk->set_rate(clk, rate); |
329 | ||
543d9378 PW |
330 | return ret; |
331 | } | |
332 | ||
543d9378 PW |
333 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
334 | { | |
fecb494b | 335 | if (clk->flags & CONFIG_PARTICIPANT) |
543d9378 PW |
336 | return -EINVAL; |
337 | ||
338 | if (!clk->clksel) | |
339 | return -EINVAL; | |
340 | ||
df791b3e | 341 | return omap2_clksel_set_parent(clk, new_parent); |
543d9378 PW |
342 | } |
343 | ||
344 | /*------------------------------------------------------------------------- | |
345 | * Omap2 clock reset and init functions | |
346 | *-------------------------------------------------------------------------*/ | |
347 | ||
348 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
349 | void omap2_clk_disable_unused(struct clk *clk) | |
350 | { | |
351 | u32 regval32, v; | |
352 | ||
353 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
354 | ||
355 | regval32 = __raw_readl(clk->enable_reg); | |
356 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
357 | return; | |
358 | ||
0db4e825 | 359 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
360 | if (cpu_is_omap34xx()) { |
361 | omap2_clk_enable(clk); | |
362 | omap2_clk_disable(clk); | |
363 | } else | |
364 | _omap2_clk_disable(clk); | |
fe617af7 PDS |
365 | if (clk->clkdm != NULL) |
366 | pwrdm_clkdm_state_switch(clk->clkdm); | |
543d9378 PW |
367 | } |
368 | #endif | |
69ecefca PW |
369 | |
370 | /* Common data */ | |
371 | ||
372 | struct clk_functions omap2_clk_functions = { | |
373 | .clk_enable = omap2_clk_enable, | |
374 | .clk_disable = omap2_clk_disable, | |
375 | .clk_round_rate = omap2_clk_round_rate, | |
376 | .clk_set_rate = omap2_clk_set_rate, | |
377 | .clk_set_parent = omap2_clk_set_parent, | |
378 | .clk_disable_unused = omap2_clk_disable_unused, | |
379 | #ifdef CONFIG_CPU_FREQ | |
380 | /* These will be removed when the OPP code is integrated */ | |
381 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | |
382 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | |
383 | #endif | |
384 | }; | |
385 |