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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
543d9378 | 26 | |
a09e64fb | 27 | #include <mach/clock.h> |
333943ba | 28 | #include <mach/clockdomain.h> |
a09e64fb RK |
29 | #include <mach/sram.h> |
30 | #include <mach/cpu.h> | |
543d9378 PW |
31 | #include <asm/div64.h> |
32 | ||
33 | #include "memory.h" | |
34 | #include "sdrc.h" | |
35 | #include "clock.h" | |
36 | #include "prm.h" | |
37 | #include "prm-regbits-24xx.h" | |
38 | #include "cm.h" | |
39 | #include "cm-regbits-24xx.h" | |
40 | #include "cm-regbits-34xx.h" | |
41 | ||
42 | #define MAX_CLOCK_ENABLE_WAIT 100000 | |
43 | ||
88b8ba90 PW |
44 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
45 | #define DPLL_MIN_MULTIPLIER 1 | |
46 | #define DPLL_MIN_DIVIDER 1 | |
47 | ||
48 | /* Possible error results from _dpll_test_mult */ | |
49 | #define DPLL_MULT_UNDERFLOW (1 << 0) | |
50 | ||
51 | /* | |
52 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | |
53 | * The higher the scale factor, the greater the risk of arithmetic overflow, | |
54 | * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR | |
55 | * must be a power of DPLL_SCALE_BASE. | |
56 | */ | |
57 | #define DPLL_SCALE_FACTOR 64 | |
58 | #define DPLL_SCALE_BASE 2 | |
59 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | |
60 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | |
61 | ||
543d9378 PW |
62 | u8 cpu_mask; |
63 | ||
64 | /*------------------------------------------------------------------------- | |
333943ba | 65 | * OMAP2/3 specific clock functions |
543d9378 PW |
66 | *-------------------------------------------------------------------------*/ |
67 | ||
333943ba PW |
68 | /** |
69 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
70 | * @clk: OMAP clock struct ptr to use | |
71 | * | |
72 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
73 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
74 | * called during clk_register(). No return value. | |
75 | */ | |
76 | void omap2_init_clk_clkdm(struct clk *clk) | |
77 | { | |
78 | struct clockdomain *clkdm; | |
79 | ||
80 | if (!clk->clkdm_name) | |
81 | return; | |
82 | ||
83 | clkdm = clkdm_lookup(clk->clkdm_name); | |
84 | if (clkdm) { | |
85 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
86 | clk->name, clk->clkdm_name); | |
87 | clk->clkdm = clkdm; | |
88 | } else { | |
89 | pr_debug("clock: could not associate clk %s to " | |
90 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
91 | } | |
92 | } | |
93 | ||
543d9378 PW |
94 | /** |
95 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | |
96 | * @clk: OMAP clock struct ptr to use | |
97 | * | |
98 | * Given a pointer to a source-selectable struct clk, read the hardware | |
99 | * register and determine what its parent is currently set to. Update the | |
100 | * clk->parent field with the appropriate clk ptr. | |
101 | */ | |
102 | void omap2_init_clksel_parent(struct clk *clk) | |
103 | { | |
104 | const struct clksel *clks; | |
105 | const struct clksel_rate *clkr; | |
106 | u32 r, found = 0; | |
107 | ||
108 | if (!clk->clksel) | |
109 | return; | |
110 | ||
111 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | |
112 | r >>= __ffs(clk->clksel_mask); | |
113 | ||
114 | for (clks = clk->clksel; clks->parent && !found; clks++) { | |
115 | for (clkr = clks->rates; clkr->div && !found; clkr++) { | |
116 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { | |
117 | if (clk->parent != clks->parent) { | |
118 | pr_debug("clock: inited %s parent " | |
119 | "to %s (was %s)\n", | |
120 | clk->name, clks->parent->name, | |
121 | ((clk->parent) ? | |
122 | clk->parent->name : "NULL")); | |
123 | clk->parent = clks->parent; | |
124 | }; | |
125 | found = 1; | |
126 | } | |
127 | } | |
128 | } | |
129 | ||
130 | if (!found) | |
131 | printk(KERN_ERR "clock: init parent: could not find " | |
132 | "regval %0x for clock %s\n", r, clk->name); | |
133 | ||
134 | return; | |
135 | } | |
136 | ||
137 | /* Returns the DPLL rate */ | |
138 | u32 omap2_get_dpll_rate(struct clk *clk) | |
139 | { | |
140 | long long dpll_clk; | |
141 | u32 dpll_mult, dpll_div, dpll; | |
88b8ba90 | 142 | struct dpll_data *dd; |
543d9378 PW |
143 | |
144 | dd = clk->dpll_data; | |
145 | /* REVISIT: What do we return on error? */ | |
146 | if (!dd) | |
147 | return 0; | |
148 | ||
149 | dpll = __raw_readl(dd->mult_div1_reg); | |
150 | dpll_mult = dpll & dd->mult_mask; | |
151 | dpll_mult >>= __ffs(dd->mult_mask); | |
152 | dpll_div = dpll & dd->div1_mask; | |
153 | dpll_div >>= __ffs(dd->div1_mask); | |
154 | ||
155 | dpll_clk = (long long)clk->parent->rate * dpll_mult; | |
156 | do_div(dpll_clk, dpll_div + 1); | |
157 | ||
543d9378 PW |
158 | return dpll_clk; |
159 | } | |
160 | ||
161 | /* | |
162 | * Used for clocks that have the same value as the parent clock, | |
163 | * divided by some factor | |
164 | */ | |
165 | void omap2_fixed_divisor_recalc(struct clk *clk) | |
166 | { | |
167 | WARN_ON(!clk->fixed_div); | |
168 | ||
169 | clk->rate = clk->parent->rate / clk->fixed_div; | |
170 | ||
171 | if (clk->flags & RATE_PROPAGATES) | |
172 | propagate_rate(clk); | |
173 | } | |
174 | ||
175 | /** | |
176 | * omap2_wait_clock_ready - wait for clock to enable | |
177 | * @reg: physical address of clock IDLEST register | |
178 | * @mask: value to mask against to determine if the clock is active | |
179 | * @name: name of the clock (for printk) | |
180 | * | |
181 | * Returns 1 if the clock enabled in time, or 0 if it failed to enable | |
182 | * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. | |
183 | */ | |
184 | int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) | |
185 | { | |
186 | int i = 0; | |
187 | int ena = 0; | |
188 | ||
189 | /* | |
190 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
191 | * 34xx reverses this, just to keep us on our toes | |
192 | */ | |
193 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { | |
194 | ena = mask; | |
195 | } else if (cpu_mask & RATE_IN_343X) { | |
196 | ena = 0; | |
197 | } | |
198 | ||
199 | /* Wait for lock */ | |
200 | while (((__raw_readl(reg) & mask) != ena) && | |
201 | (i++ < MAX_CLOCK_ENABLE_WAIT)) { | |
202 | udelay(1); | |
203 | } | |
204 | ||
205 | if (i < MAX_CLOCK_ENABLE_WAIT) | |
206 | pr_debug("Clock %s stable after %d loops\n", name, i); | |
207 | else | |
208 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", | |
209 | name, MAX_CLOCK_ENABLE_WAIT); | |
210 | ||
211 | ||
212 | return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; | |
213 | }; | |
214 | ||
215 | ||
216 | /* | |
217 | * Note: We don't need special code here for INVERT_ENABLE | |
218 | * for the time being since INVERT_ENABLE only applies to clocks enabled by | |
219 | * CM_CLKEN_PLL | |
220 | */ | |
221 | static void omap2_clk_wait_ready(struct clk *clk) | |
222 | { | |
223 | void __iomem *reg, *other_reg, *st_reg; | |
224 | u32 bit; | |
225 | ||
226 | /* | |
227 | * REVISIT: This code is pretty ugly. It would be nice to generalize | |
228 | * it and pull it into struct clk itself somehow. | |
229 | */ | |
230 | reg = clk->enable_reg; | |
231 | if ((((u32)reg & 0xff) >= CM_FCLKEN1) && | |
232 | (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) | |
233 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ | |
234 | else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && | |
235 | (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) | |
236 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ | |
237 | else | |
238 | return; | |
239 | ||
240 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | |
241 | /* No check for DSS or cam clocks */ | |
242 | if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ | |
243 | if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || | |
244 | clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || | |
245 | clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) | |
246 | return; | |
247 | } | |
248 | ||
249 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | |
250 | /* OMAP3: ignore DSS-mod clocks */ | |
251 | if (cpu_is_omap34xx() && | |
1971a390 JH |
252 | (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || |
253 | ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && | |
254 | clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) | |
543d9378 PW |
255 | return; |
256 | ||
257 | /* Check if both functional and interface clocks | |
258 | * are running. */ | |
259 | bit = 1 << clk->enable_bit; | |
260 | if (!(__raw_readl(other_reg) & bit)) | |
261 | return; | |
262 | st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ | |
263 | ||
264 | omap2_wait_clock_ready(st_reg, bit, clk->name); | |
265 | } | |
266 | ||
b36ee724 | 267 | static int omap2_dflt_clk_enable_wait(struct clk *clk) |
543d9378 PW |
268 | { |
269 | u32 regval32; | |
270 | ||
c0fc18c5 | 271 | if (unlikely(clk->enable_reg == NULL)) { |
543d9378 PW |
272 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
273 | clk->name); | |
274 | return 0; /* REVISIT: -EINVAL */ | |
275 | } | |
276 | ||
277 | regval32 = __raw_readl(clk->enable_reg); | |
278 | if (clk->flags & INVERT_ENABLE) | |
279 | regval32 &= ~(1 << clk->enable_bit); | |
280 | else | |
281 | regval32 |= (1 << clk->enable_bit); | |
282 | __raw_writel(regval32, clk->enable_reg); | |
283 | wmb(); | |
284 | ||
285 | omap2_clk_wait_ready(clk); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
b36ee724 | 290 | static void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 PW |
291 | { |
292 | u32 regval32; | |
293 | ||
c0fc18c5 | 294 | if (clk->enable_reg == NULL) { |
543d9378 PW |
295 | /* |
296 | * 'Independent' here refers to a clock which is not | |
297 | * controlled by its parent. | |
298 | */ | |
299 | printk(KERN_ERR "clock: clk_disable called on independent " | |
300 | "clock %s which has no enable_reg\n", clk->name); | |
301 | return; | |
302 | } | |
303 | ||
304 | regval32 = __raw_readl(clk->enable_reg); | |
305 | if (clk->flags & INVERT_ENABLE) | |
306 | regval32 |= (1 << clk->enable_bit); | |
307 | else | |
308 | regval32 &= ~(1 << clk->enable_bit); | |
309 | __raw_writel(regval32, clk->enable_reg); | |
310 | wmb(); | |
311 | } | |
312 | ||
b36ee724 RK |
313 | const struct clkops clkops_omap2_dflt_wait = { |
314 | .enable = omap2_dflt_clk_enable_wait, | |
315 | .disable = omap2_dflt_clk_disable, | |
316 | }; | |
317 | ||
318 | /* Enables clock without considering parent dependencies or use count | |
319 | * REVISIT: Maybe change this to use clk->enable like on omap1? | |
320 | */ | |
321 | static int _omap2_clk_enable(struct clk *clk) | |
322 | { | |
323 | return clk->ops->enable(clk); | |
324 | } | |
325 | ||
326 | /* Disables clock without considering parent dependencies or use count */ | |
327 | static void _omap2_clk_disable(struct clk *clk) | |
328 | { | |
329 | clk->ops->disable(clk); | |
330 | } | |
331 | ||
543d9378 PW |
332 | void omap2_clk_disable(struct clk *clk) |
333 | { | |
334 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
335 | _omap2_clk_disable(clk); | |
336 | if (likely((u32)clk->parent)) | |
337 | omap2_clk_disable(clk->parent); | |
333943ba PW |
338 | if (clk->clkdm) |
339 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
340 | ||
543d9378 PW |
341 | } |
342 | } | |
343 | ||
344 | int omap2_clk_enable(struct clk *clk) | |
345 | { | |
346 | int ret = 0; | |
347 | ||
348 | if (clk->usecount++ == 0) { | |
349 | if (likely((u32)clk->parent)) | |
350 | ret = omap2_clk_enable(clk->parent); | |
351 | ||
352 | if (unlikely(ret != 0)) { | |
353 | clk->usecount--; | |
354 | return ret; | |
355 | } | |
356 | ||
333943ba PW |
357 | if (clk->clkdm) |
358 | omap2_clkdm_clk_enable(clk->clkdm, clk); | |
359 | ||
543d9378 PW |
360 | ret = _omap2_clk_enable(clk); |
361 | ||
333943ba PW |
362 | if (unlikely(ret != 0)) { |
363 | if (clk->clkdm) | |
364 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
365 | ||
366 | if (clk->parent) { | |
367 | omap2_clk_disable(clk->parent); | |
368 | clk->usecount--; | |
369 | } | |
543d9378 PW |
370 | } |
371 | } | |
372 | ||
373 | return ret; | |
374 | } | |
375 | ||
376 | /* | |
377 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | |
378 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | |
379 | */ | |
380 | void omap2_clksel_recalc(struct clk *clk) | |
381 | { | |
382 | u32 div = 0; | |
383 | ||
384 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | |
385 | ||
386 | div = omap2_clksel_get_divisor(clk); | |
387 | if (div == 0) | |
388 | return; | |
389 | ||
390 | if (unlikely(clk->rate == clk->parent->rate / div)) | |
391 | return; | |
392 | clk->rate = clk->parent->rate / div; | |
393 | ||
394 | pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); | |
395 | ||
396 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
397 | propagate_rate(clk); | |
398 | } | |
399 | ||
400 | /** | |
401 | * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent | |
402 | * @clk: OMAP struct clk ptr to inspect | |
403 | * @src_clk: OMAP struct clk ptr of the parent clk to search for | |
404 | * | |
405 | * Scan the struct clksel array associated with the clock to find | |
406 | * the element associated with the supplied parent clock address. | |
407 | * Returns a pointer to the struct clksel on success or NULL on error. | |
408 | */ | |
409 | const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, | |
410 | struct clk *src_clk) | |
411 | { | |
412 | const struct clksel *clks; | |
413 | ||
414 | if (!clk->clksel) | |
415 | return NULL; | |
416 | ||
417 | for (clks = clk->clksel; clks->parent; clks++) { | |
418 | if (clks->parent == src_clk) | |
419 | break; /* Found the requested parent */ | |
420 | } | |
421 | ||
422 | if (!clks->parent) { | |
423 | printk(KERN_ERR "clock: Could not find parent clock %s in " | |
424 | "clksel array of clock %s\n", src_clk->name, | |
425 | clk->name); | |
426 | return NULL; | |
427 | } | |
428 | ||
429 | return clks; | |
430 | } | |
431 | ||
432 | /** | |
433 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate | |
434 | * @clk: OMAP struct clk to use | |
435 | * @target_rate: desired clock rate | |
436 | * @new_div: ptr to where we should store the divisor | |
437 | * | |
438 | * Finds 'best' divider value in an array based on the source and target | |
439 | * rates. The divider array must be sorted with smallest divider first. | |
440 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | |
441 | * they are only settable as part of virtual_prcm set. | |
442 | * | |
443 | * Returns the rounded clock rate or returns 0xffffffff on error. | |
444 | */ | |
445 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |
446 | u32 *new_div) | |
447 | { | |
448 | unsigned long test_rate; | |
449 | const struct clksel *clks; | |
450 | const struct clksel_rate *clkr; | |
451 | u32 last_div = 0; | |
452 | ||
453 | printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", | |
454 | clk->name, target_rate); | |
455 | ||
456 | *new_div = 1; | |
457 | ||
458 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
459 | if (clks == NULL) | |
460 | return ~0; | |
461 | ||
462 | for (clkr = clks->rates; clkr->div; clkr++) { | |
463 | if (!(clkr->flags & cpu_mask)) | |
464 | continue; | |
465 | ||
466 | /* Sanity check */ | |
467 | if (clkr->div <= last_div) | |
468 | printk(KERN_ERR "clock: clksel_rate table not sorted " | |
469 | "for clock %s", clk->name); | |
470 | ||
471 | last_div = clkr->div; | |
472 | ||
473 | test_rate = clk->parent->rate / clkr->div; | |
474 | ||
475 | if (test_rate <= target_rate) | |
476 | break; /* found it */ | |
477 | } | |
478 | ||
479 | if (!clkr->div) { | |
480 | printk(KERN_ERR "clock: Could not find divisor for target " | |
481 | "rate %ld for clock %s parent %s\n", target_rate, | |
482 | clk->name, clk->parent->name); | |
483 | return ~0; | |
484 | } | |
485 | ||
486 | *new_div = clkr->div; | |
487 | ||
488 | printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, | |
489 | (clk->parent->rate / clkr->div)); | |
490 | ||
491 | return (clk->parent->rate / clkr->div); | |
492 | } | |
493 | ||
494 | /** | |
495 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate | |
496 | * @clk: OMAP struct clk to use | |
497 | * @target_rate: desired clock rate | |
498 | * | |
499 | * Compatibility wrapper for OMAP clock framework | |
500 | * Finds best target rate based on the source clock and possible dividers. | |
501 | * rates. The divider array must be sorted with smallest divider first. | |
502 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | |
503 | * they are only settable as part of virtual_prcm set. | |
504 | * | |
505 | * Returns the rounded clock rate or returns 0xffffffff on error. | |
506 | */ | |
507 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | |
508 | { | |
509 | u32 new_div; | |
510 | ||
511 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); | |
512 | } | |
513 | ||
514 | ||
515 | /* Given a clock and a rate apply a clock specific rounding function */ | |
516 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | |
517 | { | |
c0fc18c5 | 518 | if (clk->round_rate != NULL) |
543d9378 PW |
519 | return clk->round_rate(clk, rate); |
520 | ||
521 | if (clk->flags & RATE_FIXED) | |
522 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " | |
523 | "on fixed-rate clock %s\n", clk->name); | |
524 | ||
525 | return clk->rate; | |
526 | } | |
527 | ||
528 | /** | |
529 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider | |
530 | * @clk: OMAP struct clk to use | |
531 | * @field_val: register field value to find | |
532 | * | |
533 | * Given a struct clk of a rate-selectable clksel clock, and a register field | |
534 | * value to search for, find the corresponding clock divisor. The register | |
535 | * field value should be pre-masked and shifted down so the LSB is at bit 0 | |
536 | * before calling. Returns 0 on error | |
537 | */ | |
538 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | |
539 | { | |
540 | const struct clksel *clks; | |
541 | const struct clksel_rate *clkr; | |
542 | ||
543 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
544 | if (clks == NULL) | |
545 | return 0; | |
546 | ||
547 | for (clkr = clks->rates; clkr->div; clkr++) { | |
548 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) | |
549 | break; | |
550 | } | |
551 | ||
552 | if (!clkr->div) { | |
553 | printk(KERN_ERR "clock: Could not find fieldval %d for " | |
554 | "clock %s parent %s\n", field_val, clk->name, | |
555 | clk->parent->name); | |
556 | return 0; | |
557 | } | |
558 | ||
559 | return clkr->div; | |
560 | } | |
561 | ||
562 | /** | |
563 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value | |
564 | * @clk: OMAP struct clk to use | |
565 | * @div: integer divisor to search for | |
566 | * | |
567 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, | |
568 | * find the corresponding register field value. The return register value is | |
569 | * the value before left-shifting. Returns 0xffffffff on error | |
570 | */ | |
571 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |
572 | { | |
573 | const struct clksel *clks; | |
574 | const struct clksel_rate *clkr; | |
575 | ||
576 | /* should never happen */ | |
577 | WARN_ON(div == 0); | |
578 | ||
579 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | |
580 | if (clks == NULL) | |
581 | return 0; | |
582 | ||
583 | for (clkr = clks->rates; clkr->div; clkr++) { | |
584 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) | |
585 | break; | |
586 | } | |
587 | ||
588 | if (!clkr->div) { | |
589 | printk(KERN_ERR "clock: Could not find divisor %d for " | |
590 | "clock %s parent %s\n", div, clk->name, | |
591 | clk->parent->name); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | return clkr->val; | |
596 | } | |
597 | ||
598 | /** | |
599 | * omap2_get_clksel - find clksel register addr & field mask for a clk | |
600 | * @clk: struct clk to use | |
601 | * @field_mask: ptr to u32 to store the register field mask | |
602 | * | |
603 | * Returns the address of the clksel register upon success or NULL on error. | |
604 | */ | |
605 | void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) | |
606 | { | |
c0fc18c5 | 607 | if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) |
543d9378 PW |
608 | return NULL; |
609 | ||
610 | *field_mask = clk->clksel_mask; | |
611 | ||
612 | return clk->clksel_reg; | |
613 | } | |
614 | ||
615 | /** | |
616 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | |
617 | * @clk: OMAP struct clk to use. | |
618 | * | |
619 | * Returns the integer divisor upon success or 0 on error. | |
620 | */ | |
621 | u32 omap2_clksel_get_divisor(struct clk *clk) | |
622 | { | |
623 | u32 field_mask, field_val; | |
624 | void __iomem *div_addr; | |
625 | ||
626 | div_addr = omap2_get_clksel(clk, &field_mask); | |
c0fc18c5 | 627 | if (div_addr == NULL) |
543d9378 PW |
628 | return 0; |
629 | ||
630 | field_val = __raw_readl(div_addr) & field_mask; | |
631 | field_val >>= __ffs(field_mask); | |
632 | ||
633 | return omap2_clksel_to_divisor(clk, field_val); | |
634 | } | |
635 | ||
636 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | |
637 | { | |
638 | u32 field_mask, field_val, reg_val, validrate, new_div = 0; | |
639 | void __iomem *div_addr; | |
640 | ||
641 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | |
642 | if (validrate != rate) | |
643 | return -EINVAL; | |
644 | ||
645 | div_addr = omap2_get_clksel(clk, &field_mask); | |
c0fc18c5 | 646 | if (div_addr == NULL) |
543d9378 PW |
647 | return -EINVAL; |
648 | ||
649 | field_val = omap2_divisor_to_clksel(clk, new_div); | |
650 | if (field_val == ~0) | |
651 | return -EINVAL; | |
652 | ||
653 | reg_val = __raw_readl(div_addr); | |
654 | reg_val &= ~field_mask; | |
655 | reg_val |= (field_val << __ffs(field_mask)); | |
656 | __raw_writel(reg_val, div_addr); | |
657 | wmb(); | |
658 | ||
659 | clk->rate = clk->parent->rate / new_div; | |
660 | ||
661 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | |
c2d43e39 TL |
662 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, |
663 | OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | |
543d9378 PW |
664 | wmb(); |
665 | } | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | ||
671 | /* Set the clock rate for a clock source */ | |
672 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
673 | { | |
674 | int ret = -EINVAL; | |
675 | ||
676 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
677 | ||
678 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | |
679 | rate table mechanism, driven by mpu_speed */ | |
680 | if (clk->flags & CONFIG_PARTICIPANT) | |
681 | return -EINVAL; | |
682 | ||
683 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | |
c0fc18c5 | 684 | if (clk->set_rate != NULL) |
543d9378 PW |
685 | ret = clk->set_rate(clk, rate); |
686 | ||
687 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | |
688 | propagate_rate(clk); | |
689 | ||
690 | return ret; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Converts encoded control register address into a full address | |
695 | * On error, *src_addr will be returned as 0. | |
696 | */ | |
697 | static u32 omap2_clksel_get_src_field(void __iomem **src_addr, | |
698 | struct clk *src_clk, u32 *field_mask, | |
699 | struct clk *clk, u32 *parent_div) | |
700 | { | |
701 | const struct clksel *clks; | |
702 | const struct clksel_rate *clkr; | |
703 | ||
704 | *parent_div = 0; | |
c0fc18c5 | 705 | *src_addr = NULL; |
543d9378 PW |
706 | |
707 | clks = omap2_get_clksel_by_parent(clk, src_clk); | |
708 | if (clks == NULL) | |
709 | return 0; | |
710 | ||
711 | for (clkr = clks->rates; clkr->div; clkr++) { | |
712 | if (clkr->flags & (cpu_mask | DEFAULT_RATE)) | |
713 | break; /* Found the default rate for this platform */ | |
714 | } | |
715 | ||
716 | if (!clkr->div) { | |
717 | printk(KERN_ERR "clock: Could not find default rate for " | |
718 | "clock %s parent %s\n", clk->name, | |
719 | src_clk->parent->name); | |
720 | return 0; | |
721 | } | |
722 | ||
723 | /* Should never happen. Add a clksel mask to the struct clk. */ | |
724 | WARN_ON(clk->clksel_mask == 0); | |
725 | ||
726 | *field_mask = clk->clksel_mask; | |
727 | *src_addr = clk->clksel_reg; | |
728 | *parent_div = clkr->div; | |
729 | ||
730 | return clkr->val; | |
731 | } | |
732 | ||
733 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |
734 | { | |
735 | void __iomem *src_addr; | |
736 | u32 field_val, field_mask, reg_val, parent_div; | |
737 | ||
738 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) | |
739 | return -EINVAL; | |
740 | ||
741 | if (!clk->clksel) | |
742 | return -EINVAL; | |
743 | ||
744 | field_val = omap2_clksel_get_src_field(&src_addr, new_parent, | |
745 | &field_mask, clk, &parent_div); | |
c0fc18c5 | 746 | if (src_addr == NULL) |
543d9378 PW |
747 | return -EINVAL; |
748 | ||
749 | if (clk->usecount > 0) | |
750 | _omap2_clk_disable(clk); | |
751 | ||
752 | /* Set new source value (previous dividers if any in effect) */ | |
753 | reg_val = __raw_readl(src_addr) & ~field_mask; | |
754 | reg_val |= (field_val << __ffs(field_mask)); | |
755 | __raw_writel(reg_val, src_addr); | |
756 | wmb(); | |
757 | ||
758 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | |
759 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); | |
760 | wmb(); | |
761 | } | |
762 | ||
763 | if (clk->usecount > 0) | |
764 | _omap2_clk_enable(clk); | |
765 | ||
766 | clk->parent = new_parent; | |
767 | ||
768 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | |
769 | clk->rate = new_parent->rate; | |
770 | ||
771 | if (parent_div > 0) | |
772 | clk->rate /= parent_div; | |
773 | ||
774 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | |
775 | clk->name, clk->parent->name, clk->rate); | |
776 | ||
777 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
778 | propagate_rate(clk); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
88b8ba90 PW |
783 | /* DPLL rate rounding code */ |
784 | ||
785 | /** | |
786 | * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding | |
787 | * @clk: struct clk * of the DPLL | |
788 | * @tolerance: maximum rate error tolerance | |
789 | * | |
790 | * Set the maximum DPLL rate error tolerance for the rate rounding | |
791 | * algorithm. The rate tolerance is an attempt to balance DPLL power | |
792 | * saving (the least divider value "n") vs. rate fidelity (the least | |
793 | * difference between the desired DPLL target rate and the rounded | |
794 | * rate out of the algorithm). So, increasing the tolerance is likely | |
795 | * to decrease DPLL power consumption and increase DPLL rate error. | |
796 | * Returns -EINVAL if provided a null clock ptr or a clk that is not a | |
797 | * DPLL; or 0 upon success. | |
798 | */ | |
799 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | |
800 | { | |
801 | if (!clk || !clk->dpll_data) | |
802 | return -EINVAL; | |
803 | ||
804 | clk->dpll_data->rate_tolerance = tolerance; | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) | |
810 | { | |
811 | unsigned long long num; | |
812 | ||
813 | num = (unsigned long long)parent_rate * m; | |
814 | do_div(num, n); | |
815 | return num; | |
816 | } | |
817 | ||
818 | /* | |
819 | * _dpll_test_mult - test a DPLL multiplier value | |
820 | * @m: pointer to the DPLL m (multiplier) value under test | |
821 | * @n: current DPLL n (divider) value under test | |
822 | * @new_rate: pointer to storage for the resulting rounded rate | |
823 | * @target_rate: the desired DPLL rate | |
824 | * @parent_rate: the DPLL's parent clock rate | |
825 | * | |
826 | * This code tests a DPLL multiplier value, ensuring that the | |
827 | * resulting rate will not be higher than the target_rate, and that | |
828 | * the multiplier value itself is valid for the DPLL. Initially, the | |
829 | * integer pointed to by the m argument should be prescaled by | |
830 | * multiplying by DPLL_SCALE_FACTOR. The code will replace this with | |
831 | * a non-scaled m upon return. This non-scaled m will result in a | |
832 | * new_rate as close as possible to target_rate (but not greater than | |
833 | * target_rate) given the current (parent_rate, n, prescaled m) | |
834 | * triple. Returns DPLL_MULT_UNDERFLOW in the event that the | |
835 | * non-scaled m attempted to underflow, which can allow the calling | |
836 | * function to bail out early; or 0 upon success. | |
837 | */ | |
838 | static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |
839 | unsigned long target_rate, | |
840 | unsigned long parent_rate) | |
841 | { | |
842 | int flags = 0, carry = 0; | |
843 | ||
844 | /* Unscale m and round if necessary */ | |
845 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | |
846 | carry = 1; | |
847 | *m = (*m / DPLL_SCALE_FACTOR) + carry; | |
848 | ||
849 | /* | |
850 | * The new rate must be <= the target rate to avoid programming | |
851 | * a rate that is impossible for the hardware to handle | |
852 | */ | |
853 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | |
854 | if (*new_rate > target_rate) { | |
855 | (*m)--; | |
856 | *new_rate = 0; | |
857 | } | |
858 | ||
859 | /* Guard against m underflow */ | |
860 | if (*m < DPLL_MIN_MULTIPLIER) { | |
861 | *m = DPLL_MIN_MULTIPLIER; | |
862 | *new_rate = 0; | |
863 | flags = DPLL_MULT_UNDERFLOW; | |
864 | } | |
865 | ||
866 | if (*new_rate == 0) | |
867 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | |
868 | ||
869 | return flags; | |
870 | } | |
871 | ||
872 | /** | |
873 | * omap2_dpll_round_rate - round a target rate for an OMAP DPLL | |
874 | * @clk: struct clk * for a DPLL | |
875 | * @target_rate: desired DPLL clock rate | |
876 | * | |
877 | * Given a DPLL, a desired target rate, and a rate tolerance, round | |
878 | * the target rate to a possible, programmable rate for this DPLL. | |
879 | * Rate tolerance is assumed to be set by the caller before this | |
880 | * function is called. Attempts to select the minimum possible n | |
881 | * within the tolerance to reduce power consumption. Stores the | |
882 | * computed (m, n) in the DPLL's dpll_data structure so set_rate() | |
883 | * will not need to call this (expensive) function again. Returns ~0 | |
884 | * if the target rate cannot be rounded, either because the rate is | |
885 | * too low or because the rate tolerance is set too tightly; or the | |
886 | * rounded rate upon success. | |
887 | */ | |
888 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |
889 | { | |
890 | int m, n, r, e, scaled_max_m; | |
891 | unsigned long scaled_rt_rp, new_rate; | |
892 | int min_e = -1, min_e_m = -1, min_e_n = -1; | |
893 | ||
894 | if (!clk || !clk->dpll_data) | |
895 | return ~0; | |
896 | ||
897 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " | |
898 | "%ld\n", clk->name, target_rate); | |
899 | ||
900 | scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); | |
901 | scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; | |
902 | ||
903 | clk->dpll_data->last_rounded_rate = 0; | |
904 | ||
905 | for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { | |
906 | ||
907 | /* Compute the scaled DPLL multiplier, based on the divider */ | |
908 | m = scaled_rt_rp * n; | |
909 | ||
910 | /* | |
911 | * Since we're counting n down, a m overflow means we can | |
912 | * can immediately skip to the next n | |
913 | */ | |
914 | if (m > scaled_max_m) | |
915 | continue; | |
916 | ||
917 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | |
918 | clk->parent->rate); | |
919 | ||
920 | e = target_rate - new_rate; | |
921 | pr_debug("clock: n = %d: m = %d: rate error is %d " | |
922 | "(new_rate = %ld)\n", n, m, e, new_rate); | |
923 | ||
924 | if (min_e == -1 || | |
925 | min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { | |
926 | min_e = e; | |
927 | min_e_m = m; | |
928 | min_e_n = n; | |
929 | ||
930 | pr_debug("clock: found new least error %d\n", min_e); | |
931 | } | |
932 | ||
933 | /* | |
934 | * Since we're counting n down, a m underflow means we | |
935 | * can bail out completely (since as n decreases in | |
936 | * the next iteration, there's no way that m can | |
937 | * increase beyond the current m) | |
938 | */ | |
939 | if (r & DPLL_MULT_UNDERFLOW) | |
940 | break; | |
941 | } | |
942 | ||
943 | if (min_e < 0) { | |
944 | pr_debug("clock: error: target rate or tolerance too low\n"); | |
945 | return ~0; | |
946 | } | |
947 | ||
948 | clk->dpll_data->last_rounded_m = min_e_m; | |
949 | clk->dpll_data->last_rounded_n = min_e_n; | |
950 | clk->dpll_data->last_rounded_rate = | |
951 | _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); | |
952 | ||
953 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | |
954 | min_e, min_e_m, min_e_n); | |
955 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | |
956 | clk->dpll_data->last_rounded_rate, target_rate); | |
957 | ||
958 | return clk->dpll_data->last_rounded_rate; | |
959 | } | |
960 | ||
543d9378 PW |
961 | /*------------------------------------------------------------------------- |
962 | * Omap2 clock reset and init functions | |
963 | *-------------------------------------------------------------------------*/ | |
964 | ||
965 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
966 | void omap2_clk_disable_unused(struct clk *clk) | |
967 | { | |
968 | u32 regval32, v; | |
969 | ||
970 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
971 | ||
972 | regval32 = __raw_readl(clk->enable_reg); | |
973 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
974 | return; | |
975 | ||
976 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); | |
977 | _omap2_clk_disable(clk); | |
978 | } | |
979 | #endif |