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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
543d9378 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fbd3bdb2 | 25 | #include <linux/bitops.h> |
543d9378 | 26 | |
ce491cf8 TL |
27 | #include <plat/clock.h> |
28 | #include <plat/clockdomain.h> | |
29 | #include <plat/cpu.h> | |
30 | #include <plat/prcm.h> | |
543d9378 | 31 | |
543d9378 PW |
32 | #include "clock.h" |
33 | #include "prm.h" | |
34 | #include "prm-regbits-24xx.h" | |
35 | #include "cm.h" | |
36 | #include "cm-regbits-24xx.h" | |
37 | #include "cm-regbits-34xx.h" | |
38 | ||
543d9378 PW |
39 | u8 cpu_mask; |
40 | ||
41 | /*------------------------------------------------------------------------- | |
911bd739 | 42 | * OMAP2/3/4 specific clock functions |
543d9378 PW |
43 | *-------------------------------------------------------------------------*/ |
44 | ||
4b1f76ed PW |
45 | /* Private functions */ |
46 | ||
47 | /** | |
48 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE | |
49 | * @clk: struct clk * belonging to the module | |
50 | * | |
51 | * If the necessary clocks for the OMAP hardware IP block that | |
52 | * corresponds to clock @clk are enabled, then wait for the module to | |
53 | * indicate readiness (i.e., to leave IDLE). This code does not | |
54 | * belong in the clock code and will be moved in the medium term to | |
55 | * module-dependent code. No return value. | |
56 | */ | |
57 | static void _omap2_module_wait_ready(struct clk *clk) | |
58 | { | |
59 | void __iomem *companion_reg, *idlest_reg; | |
60 | u8 other_bit, idlest_bit; | |
61 | ||
62 | /* Not all modules have multiple clocks that their IDLEST depends on */ | |
63 | if (clk->ops->find_companion) { | |
64 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | |
65 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | |
66 | return; | |
67 | } | |
68 | ||
69 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); | |
70 | ||
71 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); | |
72 | } | |
73 | ||
74 | /* Enables clock without considering parent dependencies or use count | |
75 | * REVISIT: Maybe change this to use clk->enable like on omap1? | |
76 | */ | |
77 | static int _omap2_clk_enable(struct clk *clk) | |
78 | { | |
79 | return clk->ops->enable(clk); | |
80 | } | |
81 | ||
82 | /* Disables clock without considering parent dependencies or use count */ | |
83 | static void _omap2_clk_disable(struct clk *clk) | |
84 | { | |
85 | clk->ops->disable(clk); | |
86 | } | |
87 | ||
88 | /* Public functions */ | |
89 | ||
439764cc | 90 | /** |
df791b3e | 91 | * omap2xxx_clk_commit - commit clock parent/rate changes in hardware |
439764cc PW |
92 | * @clk: struct clk * |
93 | * | |
94 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | |
95 | * don't take effect until the VALID_CONFIG bit is written, write the | |
96 | * VALID_CONFIG bit and wait for the write to complete. No return value. | |
97 | */ | |
df791b3e | 98 | void omap2xxx_clk_commit(struct clk *clk) |
439764cc PW |
99 | { |
100 | if (!cpu_is_omap24xx()) | |
101 | return; | |
102 | ||
103 | if (!(clk->flags & DELAYED_APP)) | |
104 | return; | |
105 | ||
106 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | |
8e3bd351 | 107 | OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc | 108 | /* OCP barrier */ |
8e3bd351 | 109 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); |
439764cc PW |
110 | } |
111 | ||
333943ba PW |
112 | /** |
113 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | |
114 | * @clk: OMAP clock struct ptr to use | |
115 | * | |
116 | * Convert a clockdomain name stored in a struct clk 'clk' into a | |
117 | * clockdomain pointer, and save it into the struct clk. Intended to be | |
118 | * called during clk_register(). No return value. | |
119 | */ | |
120 | void omap2_init_clk_clkdm(struct clk *clk) | |
121 | { | |
122 | struct clockdomain *clkdm; | |
123 | ||
124 | if (!clk->clkdm_name) | |
125 | return; | |
126 | ||
127 | clkdm = clkdm_lookup(clk->clkdm_name); | |
128 | if (clkdm) { | |
129 | pr_debug("clock: associated clk %s to clkdm %s\n", | |
130 | clk->name, clk->clkdm_name); | |
131 | clk->clkdm = clkdm; | |
132 | } else { | |
133 | pr_debug("clock: could not associate clk %s to " | |
134 | "clkdm %s\n", clk->name, clk->clkdm_name); | |
135 | } | |
136 | } | |
137 | ||
543d9378 | 138 | /** |
72350b29 PW |
139 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
140 | * @clk: struct clk * to find the companion clock of | |
141 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | |
142 | * @other_bit: u8 ** to return the companion clock bit shift in | |
143 | * | |
144 | * Note: We don't need special code here for INVERT_ENABLE for the | |
145 | * time being since INVERT_ENABLE only applies to clocks enabled by | |
146 | * CM_CLKEN_PLL | |
543d9378 | 147 | * |
72350b29 PW |
148 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
149 | * just a matter of XORing the bits. | |
150 | * | |
151 | * Some clocks don't have companion clocks. For example, modules with | |
152 | * only an interface clock (such as MAILBOXES) don't have a companion | |
153 | * clock. Right now, this code relies on the hardware exporting a bit | |
154 | * in the correct companion register that indicates that the | |
155 | * nonexistent 'companion clock' is active. Future patches will | |
156 | * associate this type of code with per-module data structures to | |
157 | * avoid this issue, and remove the casts. No return value. | |
543d9378 | 158 | */ |
72350b29 PW |
159 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
160 | u8 *other_bit) | |
543d9378 | 161 | { |
72350b29 | 162 | u32 r; |
543d9378 PW |
163 | |
164 | /* | |
72350b29 PW |
165 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
166 | * it's just a matter of XORing the bits. | |
543d9378 | 167 | */ |
72350b29 | 168 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
543d9378 | 169 | |
72350b29 PW |
170 | *other_reg = (__force void __iomem *)r; |
171 | *other_bit = clk->enable_bit; | |
172 | } | |
543d9378 | 173 | |
72350b29 PW |
174 | /** |
175 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk | |
176 | * @clk: struct clk * to find IDLEST info for | |
177 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in | |
178 | * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in | |
179 | * | |
180 | * Return the CM_IDLEST register address and bit shift corresponding | |
181 | * to the module that "owns" this clock. This default code assumes | |
182 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | |
183 | * the IDLEST register address ID corresponds to the CM_*CLKEN | |
184 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | |
185 | * CM_IDLEST2). This is not true for all modules. No return value. | |
543d9378 | 186 | */ |
72350b29 PW |
187 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
188 | u8 *idlest_bit) | |
543d9378 | 189 | { |
72350b29 | 190 | u32 r; |
543d9378 | 191 | |
72350b29 PW |
192 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
193 | *idlest_reg = (__force void __iomem *)r; | |
194 | *idlest_bit = clk->enable_bit; | |
195 | } | |
543d9378 | 196 | |
72350b29 | 197 | int omap2_dflt_clk_enable(struct clk *clk) |
543d9378 | 198 | { |
ee1eec36 | 199 | u32 v; |
543d9378 | 200 | |
c0fc18c5 | 201 | if (unlikely(clk->enable_reg == NULL)) { |
72350b29 | 202 | pr_err("clock.c: Enable for %s without enable code\n", |
543d9378 PW |
203 | clk->name); |
204 | return 0; /* REVISIT: -EINVAL */ | |
205 | } | |
206 | ||
ee1eec36 | 207 | v = __raw_readl(clk->enable_reg); |
543d9378 | 208 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 209 | v &= ~(1 << clk->enable_bit); |
543d9378 | 210 | else |
ee1eec36 PW |
211 | v |= (1 << clk->enable_bit); |
212 | __raw_writel(v, clk->enable_reg); | |
f11fda6a | 213 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
543d9378 | 214 | |
72350b29 | 215 | if (clk->ops->find_idlest) |
4b1f76ed | 216 | _omap2_module_wait_ready(clk); |
543d9378 | 217 | |
72350b29 | 218 | return 0; |
bc51da4e RK |
219 | } |
220 | ||
72350b29 | 221 | void omap2_dflt_clk_disable(struct clk *clk) |
543d9378 | 222 | { |
ee1eec36 | 223 | u32 v; |
543d9378 | 224 | |
fecb494b | 225 | if (!clk->enable_reg) { |
543d9378 PW |
226 | /* |
227 | * 'Independent' here refers to a clock which is not | |
228 | * controlled by its parent. | |
229 | */ | |
230 | printk(KERN_ERR "clock: clk_disable called on independent " | |
231 | "clock %s which has no enable_reg\n", clk->name); | |
232 | return; | |
233 | } | |
234 | ||
ee1eec36 | 235 | v = __raw_readl(clk->enable_reg); |
543d9378 | 236 | if (clk->flags & INVERT_ENABLE) |
ee1eec36 | 237 | v |= (1 << clk->enable_bit); |
543d9378 | 238 | else |
ee1eec36 PW |
239 | v &= ~(1 << clk->enable_bit); |
240 | __raw_writel(v, clk->enable_reg); | |
de07fedd | 241 | /* No OCP barrier needed here since it is a disable operation */ |
543d9378 PW |
242 | } |
243 | ||
b36ee724 | 244 | const struct clkops clkops_omap2_dflt_wait = { |
72350b29 | 245 | .enable = omap2_dflt_clk_enable, |
b36ee724 | 246 | .disable = omap2_dflt_clk_disable, |
72350b29 PW |
247 | .find_companion = omap2_clk_dflt_find_companion, |
248 | .find_idlest = omap2_clk_dflt_find_idlest, | |
b36ee724 RK |
249 | }; |
250 | ||
bc51da4e RK |
251 | const struct clkops clkops_omap2_dflt = { |
252 | .enable = omap2_dflt_clk_enable, | |
253 | .disable = omap2_dflt_clk_disable, | |
254 | }; | |
255 | ||
543d9378 PW |
256 | void omap2_clk_disable(struct clk *clk) |
257 | { | |
258 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
259 | _omap2_clk_disable(clk); | |
fecb494b | 260 | if (clk->parent) |
543d9378 | 261 | omap2_clk_disable(clk->parent); |
333943ba PW |
262 | if (clk->clkdm) |
263 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
264 | ||
543d9378 PW |
265 | } |
266 | } | |
267 | ||
268 | int omap2_clk_enable(struct clk *clk) | |
269 | { | |
270 | int ret = 0; | |
271 | ||
272 | if (clk->usecount++ == 0) { | |
333943ba PW |
273 | if (clk->clkdm) |
274 | omap2_clkdm_clk_enable(clk->clkdm, clk); | |
275 | ||
a7f8c599 | 276 | if (clk->parent) { |
543d9378 | 277 | ret = omap2_clk_enable(clk->parent); |
a7f8c599 RK |
278 | if (ret) |
279 | goto err; | |
543d9378 | 280 | } |
333943ba | 281 | |
543d9378 | 282 | ret = _omap2_clk_enable(clk); |
a7f8c599 | 283 | if (ret) { |
a7f8c599 | 284 | if (clk->parent) |
333943ba | 285 | omap2_clk_disable(clk->parent); |
a7f8c599 RK |
286 | |
287 | goto err; | |
543d9378 PW |
288 | } |
289 | } | |
a7f8c599 | 290 | return ret; |
543d9378 | 291 | |
a7f8c599 | 292 | err: |
8263e5b3 RK |
293 | if (clk->clkdm) |
294 | omap2_clkdm_clk_disable(clk->clkdm, clk); | |
a7f8c599 | 295 | clk->usecount--; |
543d9378 PW |
296 | return ret; |
297 | } | |
298 | ||
543d9378 PW |
299 | /* Set the clock rate for a clock source */ |
300 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |
301 | { | |
302 | int ret = -EINVAL; | |
303 | ||
304 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); | |
305 | ||
306 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the | |
307 | rate table mechanism, driven by mpu_speed */ | |
308 | if (clk->flags & CONFIG_PARTICIPANT) | |
309 | return -EINVAL; | |
310 | ||
311 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | |
fecb494b | 312 | if (clk->set_rate) |
543d9378 PW |
313 | ret = clk->set_rate(clk, rate); |
314 | ||
543d9378 PW |
315 | return ret; |
316 | } | |
317 | ||
543d9378 PW |
318 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
319 | { | |
fecb494b | 320 | if (clk->flags & CONFIG_PARTICIPANT) |
543d9378 PW |
321 | return -EINVAL; |
322 | ||
323 | if (!clk->clksel) | |
324 | return -EINVAL; | |
325 | ||
df791b3e | 326 | return omap2_clksel_set_parent(clk, new_parent); |
543d9378 PW |
327 | } |
328 | ||
329 | /*------------------------------------------------------------------------- | |
330 | * Omap2 clock reset and init functions | |
331 | *-------------------------------------------------------------------------*/ | |
332 | ||
333 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
334 | void omap2_clk_disable_unused(struct clk *clk) | |
335 | { | |
336 | u32 regval32, v; | |
337 | ||
338 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | |
339 | ||
340 | regval32 = __raw_readl(clk->enable_reg); | |
341 | if ((regval32 & (1 << clk->enable_bit)) == v) | |
342 | return; | |
343 | ||
0db4e825 | 344 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
8463e20a TK |
345 | if (cpu_is_omap34xx()) { |
346 | omap2_clk_enable(clk); | |
347 | omap2_clk_disable(clk); | |
348 | } else | |
349 | _omap2_clk_disable(clk); | |
fe617af7 PDS |
350 | if (clk->clkdm != NULL) |
351 | pwrdm_clkdm_state_switch(clk->clkdm); | |
543d9378 PW |
352 | } |
353 | #endif | |
69ecefca PW |
354 | |
355 | /* Common data */ | |
356 | ||
357 | struct clk_functions omap2_clk_functions = { | |
358 | .clk_enable = omap2_clk_enable, | |
359 | .clk_disable = omap2_clk_disable, | |
360 | .clk_round_rate = omap2_clk_round_rate, | |
361 | .clk_set_rate = omap2_clk_set_rate, | |
362 | .clk_set_parent = omap2_clk_set_parent, | |
363 | .clk_disable_unused = omap2_clk_disable_unused, | |
364 | #ifdef CONFIG_CPU_FREQ | |
365 | /* These will be removed when the OPP code is integrated */ | |
366 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | |
367 | .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, | |
368 | #endif | |
369 | }; | |
370 |