[deliverable/linux.git] / arch / arm / mach-omap2 / clock.h

/*
 *  linux/arch/arm/mach-omap2/clock.h
 *
 *  Copyright (C) 2005-2009 Texas Instruments, Inc.
 *  Copyright (C) 2004-2011 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H

#include <linux/kernel.h>
#include <linux/list.h>

#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>

struct omap_clk {
	u16				cpu;
	struct clk_lookup		lk;
};

#define CLK(dev, con, ck)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
			.clk = ck,	\
		},			\
	}

struct clockdomain;

#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\
	static struct clk _name = {				\
		.name = #_name,					\
		.hw = &_name##_hw.hw,				\
		.parent_names = _parent_array_name,		\
		.num_parents = ARRAY_SIZE(_parent_array_name),	\
		.ops = &_clkops_name,				\
	};

#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name,	\
				_clkops_name, _flags)		\
	static struct clk _name = {				\
		.name = #_name,					\
		.hw = &_name##_hw.hw,				\
		.parent_names = _parent_array_name,		\
		.num_parents = ARRAY_SIZE(_parent_array_name),	\
		.ops = &_clkops_name,				\
		.flags = _flags,				\
	};

#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name)		\
	static struct clk_hw_omap _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.clkdm_name = _clkdm_name,			\
	};

#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel,	\
			    _clksel_reg, _clksel_mask,		\
			    _parent_names, _ops)		\
	static struct clk _name;				\
	static struct clk_hw_omap _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.clksel		= _clksel,			\
		.clksel_reg	= _clksel_reg,			\
		.clksel_mask	= _clksel_mask,			\
		.clkdm_name	= _clkdm_name,			\
	};							\
	DEFINE_STRUCT_CLK(_name, _parent_names, _ops);

#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel,	\
				 _clksel_reg, _clksel_mask,	\
				 _enable_reg, _enable_bit,	\
				 _hwops, _parent_names, _ops)	\
	static struct clk _name;				\
	static struct clk_hw_omap _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.ops		= _hwops,			\
		.enable_reg	= _enable_reg,			\
		.enable_bit	= _enable_bit,			\
		.clksel		= _clksel,			\
		.clksel_reg	= _clksel_reg,			\
		.clksel_mask	= _clksel_mask,			\
		.clkdm_name	= _clkdm_name,			\
	};							\
	DEFINE_STRUCT_CLK(_name, _parent_names, _ops);

/* struct clksel_rate.flags possibilities */
#define RATE_IN_242X		(1 << 0)
#define RATE_IN_243X		(1 << 1)
#define RATE_IN_3430ES1		(1 << 2)	/* 3430ES1 rates only */
#define RATE_IN_3430ES2PLUS	(1 << 3)	/* 3430 ES >= 2 rates only */
#define RATE_IN_36XX		(1 << 4)
#define RATE_IN_4430		(1 << 5)
#define RATE_IN_TI816X		(1 << 6)
#define RATE_IN_4460		(1 << 7)
#define RATE_IN_AM33XX		(1 << 8)
#define RATE_IN_TI814X		(1 << 9)

#define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
#define RATE_IN_3XXX		(RATE_IN_34XX | RATE_IN_36XX)
#define RATE_IN_44XX		(RATE_IN_4430 | RATE_IN_4460)

/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
#define RATE_IN_3430ES2PLUS_36XX	(RATE_IN_3430ES2PLUS | RATE_IN_36XX)


/**
 * struct clksel_rate - register bitfield values corresponding to clk divisors
 * @val: register bitfield value (shifted to bit 0)
 * @div: clock divisor corresponding to @val
 * @flags: (see "struct clksel_rate.flags possibilities" above)
 *
 * @val should match the value of a read from struct clk.clksel_reg
 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
 *
 * @div is the divisor that should be applied to the parent clock's rate
 * to produce the current clock's rate.
 */
struct clksel_rate {
	u32			val;
	u8			div;
	u16			flags;
};

/**
 * struct clksel - available parent clocks, and a pointer to their divisors
 * @parent: struct clk * to a possible parent clock
 * @rates: available divisors for this parent clock
 *
 * A struct clksel is always associated with one or more struct clks
 * and one or more struct clksel_rates.
 */
struct clksel {
	struct clk		 *parent;
	const struct clksel_rate *rates;
};

/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K		0x0
#define CORE_CLK_SRC_DPLL		0x1
#define CORE_CLK_SRC_DPLL_X2		0x2

/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
#define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
#define OMAP2XXX_EN_DPLL_LOCKED			0x3

/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP3XXX_EN_DPLL_LOCKED			0x7

/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
#define OMAP4XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP4XXX_EN_DPLL_LOCKED			0x7

u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);

void __init omap2_clk_disable_clkdm_control(void);

/* clkt_clksel.c public functions */
u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
				unsigned long target_rate,
				u32 *new_div);
u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
				unsigned long *parent_rate);
int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate);
int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);

/* clkt_iclk.c public functions */
extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);

void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
				   void __iomem **other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
				void __iomem **idlest_reg,
				u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_allow_idle(struct clk *clk);
int omap2_clk_deny_idle(struct clk *clk);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
			       const char *core_ck_name,
			       const char *mpu_ck_name);

u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);

extern u16 cpu_mask;

/*
 * Clock features setup. Used instead of CPU type checks.
 */
struct ti_clk_features {
	u32 flags;
	long fint_min;
	long fint_max;
	long fint_band1_max;
	long fint_band2_min;
	u8 dpll_bypass_vals;
	u8 cm_idlest_val;
};

#define TI_CLK_DPLL_HAS_FREQSEL		(1 << 0)

extern struct ti_clk_features ti_clk_features;

extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
extern const struct clkops clkops_omap2_dflt;

extern struct clk_functions omap2_clk_functions;

extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;

extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_apll54;
extern const struct clk_hw_omap_ops clkhwops_apll96;

/* clksel_rate blocks shared between OMAP44xx and AM33xx */
extern const struct clksel_rate div_1_0_rates[];
extern const struct clksel_rate div3_1to4_rates[];
extern const struct clksel_rate div_1_1_rates[];
extern const struct clksel_rate div_1_2_rates[];
extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];

extern void __iomem *clk_memmaps[];

extern int am33xx_clk_init(void);

extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);

extern void omap_clocks_register(struct omap_clk *oclks, int cnt);

void __init ti_clk_init_features(void);
#endif
Commit	Line	Data
543d9378 PW	1	/*
	2	* linux/arch/arm/mach-omap2/clock.h
	3	*
d8a94458	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
530e544f	5	* Copyright (C) 2004-2011 Nokia Corporation
543d9378	6	*
a16e9703 TL	7	* Contacts:
a16e9703 TL	8	* Richard Woodruff <r-woodruff2@ti.com>
543d9378 PW	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
	17	#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
	18
12706c54	19	#include <linux/kernel.h>
a135eaae PW	20	#include <linux/list.h>
a135eaae PW	21
e10dd62f	22	#include <linux/clkdev.h>
f9ae32a7	23	#include <linux/clk-provider.h>
f38b0dd6	24	#include <linux/clk/ti.h>
e10dd62f PW	25
	26	struct omap_clk {
	27	u16 cpu;
	28	struct clk_lookup lk;
	29	};
	30
78e52e02	31	#define CLK(dev, con, ck) \
e10dd62f	32	{ \
e10dd62f PW	33	.lk = { \
	34	.dev_id = dev, \
	35	.con_id = con, \
	36	.clk = ck, \
	37	}, \
	38	}
	39
b5a2366c	40	struct clockdomain;
b5a2366c	41
8c725dcd PW	42	#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
	43	static struct clk _name = { \
	44	.name = #_name, \
	45	.hw = &_name##_hw.hw, \
	46	.parent_names = _parent_array_name, \
	47	.num_parents = ARRAY_SIZE(_parent_array_name), \
	48	.ops = &_clkops_name, \
	49	};
	50
601155b0 AM	51	#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
	52	_clkops_name, _flags) \
	53	static struct clk _name = { \
	54	.name = #_name, \
	55	.hw = &_name##_hw.hw, \
	56	.parent_names = _parent_array_name, \
	57	.num_parents = ARRAY_SIZE(_parent_array_name), \
	58	.ops = &_clkops_name, \
	59	.flags = _flags, \
	60	};
	61
8c725dcd PW	62	#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
	63	static struct clk_hw_omap _name##_hw = { \
	64	.hw = { \
	65	.clk = &_name, \
	66	}, \
	67	.clkdm_name = _clkdm_name, \
	68	};
	69
	70	#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
	71	_clksel_reg, _clksel_mask, \
	72	_parent_names, _ops) \
	73	static struct clk _name; \
	74	static struct clk_hw_omap _name##_hw = { \
	75	.hw = { \
	76	.clk = &_name, \
	77	}, \
	78	.clksel = _clksel, \
	79	.clksel_reg = _clksel_reg, \
	80	.clksel_mask = _clksel_mask, \
	81	.clkdm_name = _clkdm_name, \
	82	}; \
	83	DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
	84
	85	#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
	86	_clksel_reg, _clksel_mask, \
	87	_enable_reg, _enable_bit, \
	88	_hwops, _parent_names, _ops) \
	89	static struct clk _name; \
	90	static struct clk_hw_omap _name##_hw = { \
	91	.hw = { \
	92	.clk = &_name, \
	93	}, \
	94	.ops = _hwops, \
	95	.enable_reg = _enable_reg, \
	96	.enable_bit = _enable_bit, \
	97	.clksel = _clksel, \
	98	.clksel_reg = _clksel_reg, \
	99	.clksel_mask = _clksel_mask, \
	100	.clkdm_name = _clkdm_name, \
	101	}; \
	102	DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
	103
a135eaae PW	104	/* struct clksel_rate.flags possibilities */
	105	#define RATE_IN_242X (1 << 0)
	106	#define RATE_IN_243X (1 << 1)
	107	#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
	108	#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
	109	#define RATE_IN_36XX (1 << 4)
	110	#define RATE_IN_4430 (1 << 5)
	111	#define RATE_IN_TI816X (1 << 6)
	112	#define RATE_IN_4460 (1 << 7)
	113	#define RATE_IN_AM33XX (1 << 8)
	114	#define RATE_IN_TI814X (1 << 9)
	115
	116	#define RATE_IN_24XX (RATE_IN_242X \| RATE_IN_243X)
	117	#define RATE_IN_34XX (RATE_IN_3430ES1 \| RATE_IN_3430ES2PLUS)
	118	#define RATE_IN_3XXX (RATE_IN_34XX \| RATE_IN_36XX)
	119	#define RATE_IN_44XX (RATE_IN_4430 \| RATE_IN_4460)
	120
	121	/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
	122	#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS \| RATE_IN_36XX)
	123
	124
	125	/**
	126	* struct clksel_rate - register bitfield values corresponding to clk divisors
	127	* @val: register bitfield value (shifted to bit 0)
	128	* @div: clock divisor corresponding to @val
	129	* @flags: (see "struct clksel_rate.flags possibilities" above)
	130	*
	131	* @val should match the value of a read from struct clk.clksel_reg
	132	* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
	133	*
	134	* @div is the divisor that should be applied to the parent clock's rate
	135	* to produce the current clock's rate.
	136	*/
	137	struct clksel_rate {
	138	u32 val;
	139	u8 div;
	140	u16 flags;
	141	};
	142
	143	/**
	144	* struct clksel - available parent clocks, and a pointer to their divisors
	145	* @parent: struct clk * to a possible parent clock
	146	* @rates: available divisors for this parent clock
	147	*
	148	* A struct clksel is always associated with one or more struct clks
	149	* and one or more struct clksel_rates.
	150	*/
	151	struct clksel {
	152	struct clk *parent;
	153	const struct clksel_rate *rates;
	154	};
	155
c0bf3132 RK	156	/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
	157	#define CORE_CLK_SRC_32K 0x0
	158	#define CORE_CLK_SRC_DPLL 0x1
	159	#define CORE_CLK_SRC_DPLL_X2 0x2
	160
	161	/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
	162	#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
	163	#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
	164	#define OMAP2XXX_EN_DPLL_LOCKED 0x3
	165
	166	/* OMAP3xxx CM_CLKEN_PLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	167	#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
	168	#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
	169	#define OMAP3XXX_EN_DPLL_LOCKED 0x7
	170
16975a79 RN	171	/* OMAP4xxx CM_CLKMODE_DPLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	172	#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
	173	#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
	174	#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
	175	#define OMAP4XXX_EN_DPLL_LOCKED 0x7
	176
32cc0021 MT	177	u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
	178	void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
	179	void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
32cc0021 MT	180	int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
	181	void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
	182	void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
543d9378	183
12706c54	184	void __init omap2_clk_disable_clkdm_control(void);
435699db PW	185
435699db PW	186	/* clkt_clksel.c public functions */
32cc0021 MT	187	u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
	188	unsigned long target_rate,
	189	u32 *new_div);
	190	u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
	191	unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
	192	long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
	193	unsigned long *parent_rate);
	194	int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
	195	unsigned long parent_rate);
	196	int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
435699db	197
530e544f	198	/* clkt_iclk.c public functions */
b4777a21 RN	199	extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
b4777a21 RN	200	extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
530e544f	201
32cc0021	202	unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
435699db	203
32cc0021 MT	204	void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
	205	void __iomem **other_reg,
	206	u8 *other_bit);
	207	void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
	208	void __iomem **idlest_reg,
	209	u8 idlest_bit, u8 idlest_val);
23fb8ba3	210	int omap2_clk_enable_autoidle_all(void);
818b40e5 TK	211	int omap2_clk_allow_idle(struct clk *clk);
818b40e5 TK	212	int omap2_clk_deny_idle(struct clk *clk);
4d30e82c PW	213	int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
	214	void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
	215	const char *core_ck_name,
	216	const char *mpu_ck_name);
543d9378	217
3ada6b10 TK	218	u32 omap2_clk_readl(struct clk_hw_omap clk, void __iomem reg);
	219	void omap2_clk_writel(u32 val, struct clk_hw_omap clk, void __iomem reg);
	220
99541195	221	extern u16 cpu_mask;
d8a94458	222
8111e010 TK	223	/*
	224	* Clock features setup. Used instead of CPU type checks.
	225	*/
	226	struct ti_clk_features {
	227	u32 flags;
a24886e2 TK	228	long fint_min;
	229	long fint_max;
	230	long fint_band1_max;
	231	long fint_band2_min;
512d91cb	232	u8 dpll_bypass_vals;
066edb2d	233	u8 cm_idlest_val;
8111e010	234	};
2337c5b5 TK	235
	236	#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
	237
8111e010 TK	238	extern struct ti_clk_features ti_clk_features;
8111e010 TK	239
b36ee724	240	extern const struct clkops clkops_omap2_dflt_wait;
7c43d547	241	extern const struct clkops clkops_dummy;
bc51da4e	242	extern const struct clkops clkops_omap2_dflt;
b36ee724	243
82e9bd58 PW	244	extern struct clk_functions omap2_clk_functions;
82e9bd58 PW	245
d8a94458 PW	246	extern const struct clksel_rate gpt_32k_rates[];
	247	extern const struct clksel_rate gpt_sys_rates[];
	248	extern const struct clksel_rate gfx_l3_rates[];
22411396	249	extern const struct clksel_rate dsp_ick_rates[];
cb26867e	250	extern struct clk dummy_ck;
543d9378	251
32cc0021 MT	252	extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
32cc0021 MT	253	extern const struct clk_hw_omap_ops clkhwops_wait;
b4777a21	254	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
b4777a21	255	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
b4777a21 RN	256	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
b4777a21 RN	257	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
b4777a21 RN	258	extern const struct clk_hw_omap_ops clkhwops_apll54;
b4777a21 RN	259	extern const struct clk_hw_omap_ops clkhwops_apll96;
657ebfad	260
571efa0d PW	261	/* clksel_rate blocks shared between OMAP44xx and AM33xx */
571efa0d PW	262	extern const struct clksel_rate div_1_0_rates[];
cb26867e	263	extern const struct clksel_rate div3_1to4_rates[];
571efa0d PW	264	extern const struct clksel_rate div_1_1_rates[];
	265	extern const struct clksel_rate div_1_2_rates[];
	266	extern const struct clksel_rate div_1_3_rates[];
	267	extern const struct clksel_rate div_1_4_rates[];
	268	extern const struct clksel_rate div31_1to31_rates[];
	269
3ada6b10 TK	270	extern void __iomem *clk_memmaps[];
3ada6b10 TK	271
e30384ab VH	272	extern int am33xx_clk_init(void);
e30384ab VH	273
32cc0021 MT	274	extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
32cc0021 MT	275	extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
32cc0021	276
78e52e02	277	extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
8111e010 TK	278
8111e010 TK	279	void __init ti_clk_init_features(void);
543d9378	280	#endif