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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | |
3 | * | |
d8a94458 | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
530e544f | 5 | * Copyright (C) 2004-2011 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
18 | ||
12706c54 PW |
19 | #include <linux/kernel.h> |
20 | ||
ce491cf8 | 21 | #include <plat/clock.h> |
543d9378 | 22 | |
c0bf3132 RK |
23 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
24 | #define CORE_CLK_SRC_32K 0x0 | |
25 | #define CORE_CLK_SRC_DPLL 0x1 | |
26 | #define CORE_CLK_SRC_DPLL_X2 0x2 | |
27 | ||
28 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | |
29 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | |
30 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | |
31 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | |
32 | ||
33 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | |
34 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | |
35 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | |
36 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | |
37 | ||
16975a79 RN |
38 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
39 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | |
40 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | |
41 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | |
42 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | |
43 | ||
a1391d27 RN |
44 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
45 | #define DPLL_LOW_POWER_STOP 0x1 | |
46 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
47 | #define DPLL_LOCKED 0x7 | |
48 | ||
358965d7 RW |
49 | /* DPLL Type and DCO Selection Flags */ |
50 | #define DPLL_J_TYPE 0x1 | |
358965d7 | 51 | |
543d9378 PW |
52 | int omap2_clk_enable(struct clk *clk); |
53 | void omap2_clk_disable(struct clk *clk); | |
54 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | |
55 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |
56 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | |
88b8ba90 | 57 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
a1391d27 RN |
58 | unsigned long omap3_dpll_recalc(struct clk *clk); |
59 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | |
60 | void omap3_dpll_allow_idle(struct clk *clk); | |
61 | void omap3_dpll_deny_idle(struct clk *clk); | |
62 | u32 omap3_dpll_autoidle_read(struct clk *clk); | |
63 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | |
64 | int omap3_noncore_dpll_enable(struct clk *clk); | |
65 | void omap3_noncore_dpll_disable(struct clk *clk); | |
97f67898 RN |
66 | int omap4_dpllmx_gatectrl_read(struct clk *clk); |
67 | void omap4_dpllmx_allow_gatectrl(struct clk *clk); | |
68 | void omap4_dpllmx_deny_gatectrl(struct clk *clk); | |
a1900f2e MT |
69 | long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); |
70 | unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); | |
543d9378 PW |
71 | |
72 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
73 | void omap2_clk_disable_unused(struct clk *clk); | |
74 | #else | |
75 | #define omap2_clk_disable_unused NULL | |
76 | #endif | |
77 | ||
333943ba | 78 | void omap2_init_clk_clkdm(struct clk *clk); |
12706c54 | 79 | void __init omap2_clk_disable_clkdm_control(void); |
435699db PW |
80 | |
81 | /* clkt_clksel.c public functions */ | |
543d9378 PW |
82 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
83 | u32 *new_div); | |
435699db PW |
84 | void omap2_init_clksel_parent(struct clk *clk); |
85 | unsigned long omap2_clksel_recalc(struct clk *clk); | |
543d9378 PW |
86 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
87 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | |
df791b3e | 88 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); |
435699db | 89 | |
530e544f PW |
90 | /* clkt_iclk.c public functions */ |
91 | extern void omap2_clkt_iclk_allow_idle(struct clk *clk); | |
92 | extern void omap2_clkt_iclk_deny_idle(struct clk *clk); | |
93 | ||
543d9378 | 94 | u32 omap2_get_dpll_rate(struct clk *clk); |
911bd739 | 95 | void omap2_init_dpll_parent(struct clk *clk); |
435699db | 96 | |
543d9378 | 97 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
56213ca4 TL |
98 | |
99 | ||
100 | #ifdef CONFIG_ARCH_OMAP2 | |
101 | void omap2xxx_clk_prepare_for_reboot(void); | |
102 | #else | |
103 | static inline void omap2xxx_clk_prepare_for_reboot(void) | |
104 | { | |
105 | } | |
106 | #endif | |
107 | ||
108 | #ifdef CONFIG_ARCH_OMAP3 | |
109 | void omap3_clk_prepare_for_reboot(void); | |
110 | #else | |
111 | static inline void omap3_clk_prepare_for_reboot(void) | |
112 | { | |
113 | } | |
114 | #endif | |
115 | ||
116 | #ifdef CONFIG_ARCH_OMAP4 | |
117 | void omap4_clk_prepare_for_reboot(void); | |
118 | #else | |
119 | static inline void omap4_clk_prepare_for_reboot(void) | |
120 | { | |
121 | } | |
122 | #endif | |
123 | ||
72350b29 PW |
124 | int omap2_dflt_clk_enable(struct clk *clk); |
125 | void omap2_dflt_clk_disable(struct clk *clk); | |
126 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |
127 | u8 *other_bit); | |
128 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | |
419cc97d | 129 | u8 *idlest_bit, u8 *idlest_val); |
4d30e82c PW |
130 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); |
131 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
132 | const char *core_ck_name, | |
133 | const char *mpu_ck_name); | |
543d9378 | 134 | |
99541195 | 135 | extern u16 cpu_mask; |
d8a94458 | 136 | |
b36ee724 | 137 | extern const struct clkops clkops_omap2_dflt_wait; |
7c43d547 | 138 | extern const struct clkops clkops_dummy; |
bc51da4e | 139 | extern const struct clkops clkops_omap2_dflt; |
b36ee724 | 140 | |
82e9bd58 | 141 | extern struct clk_functions omap2_clk_functions; |
d8a94458 | 142 | extern struct clk *vclk, *sclk; |
82e9bd58 | 143 | |
d8a94458 PW |
144 | extern const struct clksel_rate gpt_32k_rates[]; |
145 | extern const struct clksel_rate gpt_sys_rates[]; | |
146 | extern const struct clksel_rate gfx_l3_rates[]; | |
22411396 | 147 | extern const struct clksel_rate dsp_ick_rates[]; |
543d9378 | 148 | |
530e544f PW |
149 | extern const struct clkops clkops_omap2_iclk_dflt_wait; |
150 | extern const struct clkops clkops_omap2_iclk_dflt; | |
151 | extern const struct clkops clkops_omap2_iclk_idle_only; | |
e892b252 | 152 | extern const struct clkops clkops_omap2_mdmclk_dflt_wait; |
0fd0c21b | 153 | extern const struct clkops clkops_omap2xxx_dpll_ops; |
657ebfad | 154 | extern const struct clkops clkops_omap3_noncore_dpll_ops; |
6c6f5a74 | 155 | extern const struct clkops clkops_omap3_core_dpll_ops; |
70db8a62 | 156 | extern const struct clkops clkops_omap4_dpllmx_ops; |
657ebfad | 157 | |
571efa0d PW |
158 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ |
159 | extern const struct clksel_rate div_1_0_rates[]; | |
160 | extern const struct clksel_rate div_1_1_rates[]; | |
161 | extern const struct clksel_rate div_1_2_rates[]; | |
162 | extern const struct clksel_rate div_1_3_rates[]; | |
163 | extern const struct clksel_rate div_1_4_rates[]; | |
164 | extern const struct clksel_rate div31_1to31_rates[]; | |
165 | ||
166 | /* clocks shared between various OMAP SoCs */ | |
167 | extern struct clk virt_19200000_ck; | |
168 | extern struct clk virt_26000000_ck; | |
169 | ||
e30384ab VH |
170 | extern int am33xx_clk_init(void); |
171 | ||
543d9378 | 172 | #endif |