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1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
18 | ||
a09e64fb | 19 | #include <mach/clock.h> |
543d9378 | 20 | |
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21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | |
23 | ||
646e3ed1 | 24 | int omap2_clk_init(void); |
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25 | int omap2_clk_enable(struct clk *clk); |
26 | void omap2_clk_disable(struct clk *clk); | |
27 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | |
28 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |
29 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | |
fecb494b | 30 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
88b8ba90 | 31 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
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32 | |
33 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
34 | void omap2_clk_disable_unused(struct clk *clk); | |
35 | #else | |
36 | #define omap2_clk_disable_unused NULL | |
37 | #endif | |
38 | ||
8b9dbc16 | 39 | unsigned long omap2_clksel_recalc(struct clk *clk); |
333943ba | 40 | void omap2_init_clk_clkdm(struct clk *clk); |
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41 | void omap2_init_clksel_parent(struct clk *clk); |
42 | u32 omap2_clksel_get_divisor(struct clk *clk); | |
43 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |
44 | u32 *new_div); | |
45 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | |
46 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | |
8b9dbc16 | 47 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); |
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48 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
49 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | |
50 | u32 omap2_get_dpll_rate(struct clk *clk); | |
51 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | |
ff00fcc9 | 52 | void omap2_clk_prepare_for_reboot(void); |
543d9378 | 53 | |
b36ee724 | 54 | extern const struct clkops clkops_omap2_dflt_wait; |
bc51da4e | 55 | extern const struct clkops clkops_omap2_dflt; |
b36ee724 | 56 | |
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57 | extern u8 cpu_mask; |
58 | ||
59 | /* clksel_rate data common to 24xx/343x */ | |
60 | static const struct clksel_rate gpt_32k_rates[] = { | |
61 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | |
62 | { .div = 0 } | |
63 | }; | |
64 | ||
65 | static const struct clksel_rate gpt_sys_rates[] = { | |
66 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | |
67 | { .div = 0 } | |
68 | }; | |
69 | ||
70 | static const struct clksel_rate gfx_l3_rates[] = { | |
71 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, | |
72 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, | |
73 | { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, | |
74 | { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, | |
75 | { .div = 0 } | |
76 | }; | |
77 | ||
78 | ||
79 | #endif |