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543d9378 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | |
3 | * | |
d8a94458 | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
530e544f | 5 | * Copyright (C) 2004-2011 Nokia Corporation |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 PW |
9 | * Paul Walmsley |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
18 | ||
12706c54 | 19 | #include <linux/kernel.h> |
a135eaae PW |
20 | #include <linux/list.h> |
21 | ||
22 | struct module; | |
23 | struct clk; | |
24 | struct clockdomain; | |
25 | ||
26 | /* Temporary, needed during the common clock framework conversion */ | |
27 | #define __clk_get_name(clk) (clk->name) | |
28 | #define __clk_get_parent(clk) (clk->parent) | |
29 | #define __clk_get_rate(clk) (clk->rate) | |
30 | ||
31 | /** | |
32 | * struct clkops - some clock function pointers | |
33 | * @enable: fn ptr that enables the current clock in hardware | |
34 | * @disable: fn ptr that enables the current clock in hardware | |
35 | * @find_idlest: function returning the IDLEST register for the clock's IP blk | |
36 | * @find_companion: function returning the "companion" clk reg for the clock | |
37 | * @allow_idle: fn ptr that enables autoidle for the current clock in hardware | |
38 | * @deny_idle: fn ptr that disables autoidle for the current clock in hardware | |
39 | * | |
40 | * A "companion" clk is an accompanying clock to the one being queried | |
41 | * that must be enabled for the IP module connected to the clock to | |
42 | * become accessible by the hardware. Neither @find_idlest nor | |
43 | * @find_companion should be needed; that information is IP | |
44 | * block-specific; the hwmod code has been created to handle this, but | |
45 | * until hwmod data is ready and drivers have been converted to use PM | |
46 | * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and | |
47 | * @find_companion must, unfortunately, remain. | |
48 | */ | |
49 | struct clkops { | |
50 | int (*enable)(struct clk *); | |
51 | void (*disable)(struct clk *); | |
52 | void (*find_idlest)(struct clk *, void __iomem **, | |
53 | u8 *, u8 *); | |
54 | void (*find_companion)(struct clk *, void __iomem **, | |
55 | u8 *); | |
56 | void (*allow_idle)(struct clk *); | |
57 | void (*deny_idle)(struct clk *); | |
58 | }; | |
59 | ||
60 | /* struct clksel_rate.flags possibilities */ | |
61 | #define RATE_IN_242X (1 << 0) | |
62 | #define RATE_IN_243X (1 << 1) | |
63 | #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ | |
64 | #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ | |
65 | #define RATE_IN_36XX (1 << 4) | |
66 | #define RATE_IN_4430 (1 << 5) | |
67 | #define RATE_IN_TI816X (1 << 6) | |
68 | #define RATE_IN_4460 (1 << 7) | |
69 | #define RATE_IN_AM33XX (1 << 8) | |
70 | #define RATE_IN_TI814X (1 << 9) | |
71 | ||
72 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | |
73 | #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) | |
74 | #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) | |
75 | #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) | |
76 | ||
77 | /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ | |
78 | #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) | |
79 | ||
80 | ||
81 | /** | |
82 | * struct clksel_rate - register bitfield values corresponding to clk divisors | |
83 | * @val: register bitfield value (shifted to bit 0) | |
84 | * @div: clock divisor corresponding to @val | |
85 | * @flags: (see "struct clksel_rate.flags possibilities" above) | |
86 | * | |
87 | * @val should match the value of a read from struct clk.clksel_reg | |
88 | * AND'ed with struct clk.clksel_mask, shifted right to bit 0. | |
89 | * | |
90 | * @div is the divisor that should be applied to the parent clock's rate | |
91 | * to produce the current clock's rate. | |
92 | */ | |
93 | struct clksel_rate { | |
94 | u32 val; | |
95 | u8 div; | |
96 | u16 flags; | |
97 | }; | |
98 | ||
99 | /** | |
100 | * struct clksel - available parent clocks, and a pointer to their divisors | |
101 | * @parent: struct clk * to a possible parent clock | |
102 | * @rates: available divisors for this parent clock | |
103 | * | |
104 | * A struct clksel is always associated with one or more struct clks | |
105 | * and one or more struct clksel_rates. | |
106 | */ | |
107 | struct clksel { | |
108 | struct clk *parent; | |
109 | const struct clksel_rate *rates; | |
110 | }; | |
111 | ||
112 | /** | |
113 | * struct dpll_data - DPLL registers and integration data | |
114 | * @mult_div1_reg: register containing the DPLL M and N bitfields | |
115 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg | |
116 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg | |
117 | * @clk_bypass: struct clk pointer to the clock's bypass clock input | |
118 | * @clk_ref: struct clk pointer to the clock's reference clock input | |
119 | * @control_reg: register containing the DPLL mode bitfield | |
120 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg | |
121 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() | |
122 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() | |
123 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) | |
124 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() | |
125 | * @min_divider: minimum valid non-bypass divider value (actual) | |
126 | * @max_divider: maximum valid non-bypass divider value (actual) | |
127 | * @modes: possible values of @enable_mask | |
128 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield | |
129 | * @idlest_reg: register containing the DPLL idle status bitfield | |
130 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg | |
131 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg | |
132 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg | |
133 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg | |
134 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs | |
135 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs | |
136 | * @flags: DPLL type/features (see below) | |
137 | * | |
138 | * Possible values for @flags: | |
139 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) | |
140 | * | |
141 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. | |
142 | * | |
143 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically | |
144 | * correct to only have one @clk_bypass pointer. | |
145 | * | |
146 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, | |
147 | * @last_rounded_n) should be separated from the runtime-fixed fields | |
148 | * and placed into a different structure, so that the runtime-fixed data | |
149 | * can be placed into read-only space. | |
150 | */ | |
151 | struct dpll_data { | |
152 | void __iomem *mult_div1_reg; | |
153 | u32 mult_mask; | |
154 | u32 div1_mask; | |
155 | struct clk *clk_bypass; | |
156 | struct clk *clk_ref; | |
157 | void __iomem *control_reg; | |
158 | u32 enable_mask; | |
159 | unsigned long last_rounded_rate; | |
160 | u16 last_rounded_m; | |
161 | u16 max_multiplier; | |
162 | u8 last_rounded_n; | |
163 | u8 min_divider; | |
164 | u16 max_divider; | |
165 | u8 modes; | |
166 | void __iomem *autoidle_reg; | |
167 | void __iomem *idlest_reg; | |
168 | u32 autoidle_mask; | |
169 | u32 freqsel_mask; | |
170 | u32 idlest_mask; | |
171 | u32 dco_mask; | |
172 | u32 sddiv_mask; | |
173 | u8 auto_recal_bit; | |
174 | u8 recal_en_bit; | |
175 | u8 recal_st_bit; | |
176 | u8 flags; | |
177 | }; | |
178 | ||
179 | /* | |
180 | * struct clk.flags possibilities | |
181 | * | |
182 | * XXX document the rest of the clock flags here | |
183 | * | |
184 | * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL | |
185 | * bits share the same register. This flag allows the | |
186 | * omap4_dpllmx*() code to determine which GATE_CTRL bit field | |
187 | * should be used. This is a temporary solution - a better approach | |
188 | * would be to associate clock type-specific data with the clock, | |
189 | * similar to the struct dpll_data approach. | |
190 | */ | |
191 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ | |
192 | #define CLOCK_IDLE_CONTROL (1 << 1) | |
193 | #define CLOCK_NO_IDLE_PARENT (1 << 2) | |
194 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ | |
195 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ | |
196 | #define CLOCK_CLKOUTX2 (1 << 5) | |
197 | ||
198 | /** | |
199 | * struct clk - OMAP struct clk | |
200 | * @node: list_head connecting this clock into the full clock list | |
201 | * @ops: struct clkops * for this clock | |
202 | * @name: the name of the clock in the hardware (used in hwmod data and debug) | |
203 | * @parent: pointer to this clock's parent struct clk | |
204 | * @children: list_head connecting to the child clks' @sibling list_heads | |
205 | * @sibling: list_head connecting this clk to its parent clk's @children | |
206 | * @rate: current clock rate | |
207 | * @enable_reg: register to write to enable the clock (see @enable_bit) | |
208 | * @recalc: fn ptr that returns the clock's current rate | |
209 | * @set_rate: fn ptr that can change the clock's current rate | |
210 | * @round_rate: fn ptr that can round the clock's current rate | |
211 | * @init: fn ptr to do clock-specific initialization | |
212 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) | |
213 | * @usecount: number of users that have requested this clock to be enabled | |
214 | * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div | |
215 | * @flags: see "struct clk.flags possibilities" above | |
216 | * @clksel_reg: for clksel clks, register va containing src/divisor select | |
217 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector | |
218 | * @clksel: for clksel clks, pointer to struct clksel for this clock | |
219 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock | |
220 | * @clkdm_name: clockdomain name that this clock is contained in | |
221 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime | |
222 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) | |
223 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) | |
224 | * | |
225 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 | |
226 | * clock code converted to use clksel. | |
227 | * | |
228 | * XXX @usecount is poorly named. It should be "enable_count" or | |
229 | * something similar. "users" in the description refers to kernel | |
230 | * code (core code or drivers) that have called clk_enable() and not | |
231 | * yet called clk_disable(); the usecount of parent clocks is also | |
232 | * incremented by the clock code when clk_enable() is called on child | |
233 | * clocks and decremented by the clock code when clk_disable() is | |
234 | * called on child clocks. | |
235 | * | |
236 | * XXX @clkdm, @usecount, @children, @sibling should be marked for | |
237 | * internal use only. | |
238 | * | |
239 | * @children and @sibling are used to optimize parent-to-child clock | |
240 | * tree traversals. (child-to-parent traversals use @parent.) | |
241 | * | |
242 | * XXX The notion of the clock's current rate probably needs to be | |
243 | * separated from the clock's target rate. | |
244 | */ | |
245 | struct clk { | |
246 | struct list_head node; | |
247 | const struct clkops *ops; | |
248 | const char *name; | |
249 | struct clk *parent; | |
250 | struct list_head children; | |
251 | struct list_head sibling; /* node for children */ | |
252 | unsigned long rate; | |
253 | void __iomem *enable_reg; | |
254 | unsigned long (*recalc)(struct clk *); | |
255 | int (*set_rate)(struct clk *, unsigned long); | |
256 | long (*round_rate)(struct clk *, unsigned long); | |
257 | void (*init)(struct clk *); | |
258 | u8 enable_bit; | |
259 | s8 usecount; | |
260 | u8 fixed_div; | |
261 | u8 flags; | |
262 | void __iomem *clksel_reg; | |
263 | u32 clksel_mask; | |
264 | const struct clksel *clksel; | |
265 | struct dpll_data *dpll_data; | |
266 | const char *clkdm_name; | |
267 | struct clockdomain *clkdm; | |
268 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | |
269 | struct dentry *dent; /* For visible tree hierarchy */ | |
270 | #endif | |
271 | }; | |
272 | ||
273 | struct clk_functions { | |
274 | int (*clk_enable)(struct clk *clk); | |
275 | void (*clk_disable)(struct clk *clk); | |
276 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); | |
277 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | |
278 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | |
279 | void (*clk_allow_idle)(struct clk *clk); | |
280 | void (*clk_deny_idle)(struct clk *clk); | |
281 | void (*clk_disable_unused)(struct clk *clk); | |
282 | }; | |
283 | ||
284 | extern int mpurate; | |
285 | ||
286 | extern int clk_init(struct clk_functions *custom_clocks); | |
287 | extern void clk_preinit(struct clk *clk); | |
288 | extern int clk_register(struct clk *clk); | |
289 | extern void clk_reparent(struct clk *child, struct clk *parent); | |
290 | extern void clk_unregister(struct clk *clk); | |
291 | extern void propagate_rate(struct clk *clk); | |
292 | extern void recalculate_root_clocks(void); | |
293 | extern unsigned long followparent_recalc(struct clk *clk); | |
294 | extern void clk_enable_init_clocks(void); | |
295 | unsigned long omap_fixed_divisor_recalc(struct clk *clk); | |
296 | extern struct clk *omap_clk_get_by_name(const char *name); | |
297 | extern int omap_clk_enable_autoidle_all(void); | |
298 | extern int omap_clk_disable_autoidle_all(void); | |
299 | ||
300 | extern const struct clkops clkops_null; | |
301 | ||
302 | extern struct clk dummy_ck; | |
12706c54 | 303 | |
543d9378 | 304 | |
c0bf3132 RK |
305 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
306 | #define CORE_CLK_SRC_32K 0x0 | |
307 | #define CORE_CLK_SRC_DPLL 0x1 | |
308 | #define CORE_CLK_SRC_DPLL_X2 0x2 | |
309 | ||
310 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | |
311 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | |
312 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | |
313 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | |
314 | ||
315 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | |
316 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | |
317 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | |
318 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | |
319 | ||
16975a79 RN |
320 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
321 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | |
322 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | |
323 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | |
324 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | |
325 | ||
a1391d27 RN |
326 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
327 | #define DPLL_LOW_POWER_STOP 0x1 | |
328 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
329 | #define DPLL_LOCKED 0x7 | |
330 | ||
358965d7 RW |
331 | /* DPLL Type and DCO Selection Flags */ |
332 | #define DPLL_J_TYPE 0x1 | |
358965d7 | 333 | |
543d9378 PW |
334 | int omap2_clk_enable(struct clk *clk); |
335 | void omap2_clk_disable(struct clk *clk); | |
336 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | |
337 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |
338 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | |
88b8ba90 | 339 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
a1391d27 RN |
340 | unsigned long omap3_dpll_recalc(struct clk *clk); |
341 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | |
342 | void omap3_dpll_allow_idle(struct clk *clk); | |
343 | void omap3_dpll_deny_idle(struct clk *clk); | |
344 | u32 omap3_dpll_autoidle_read(struct clk *clk); | |
345 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | |
346 | int omap3_noncore_dpll_enable(struct clk *clk); | |
347 | void omap3_noncore_dpll_disable(struct clk *clk); | |
97f67898 RN |
348 | int omap4_dpllmx_gatectrl_read(struct clk *clk); |
349 | void omap4_dpllmx_allow_gatectrl(struct clk *clk); | |
350 | void omap4_dpllmx_deny_gatectrl(struct clk *clk); | |
a1900f2e MT |
351 | long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); |
352 | unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); | |
543d9378 PW |
353 | |
354 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
355 | void omap2_clk_disable_unused(struct clk *clk); | |
356 | #else | |
357 | #define omap2_clk_disable_unused NULL | |
358 | #endif | |
359 | ||
333943ba | 360 | void omap2_init_clk_clkdm(struct clk *clk); |
12706c54 | 361 | void __init omap2_clk_disable_clkdm_control(void); |
435699db PW |
362 | |
363 | /* clkt_clksel.c public functions */ | |
543d9378 PW |
364 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
365 | u32 *new_div); | |
435699db PW |
366 | void omap2_init_clksel_parent(struct clk *clk); |
367 | unsigned long omap2_clksel_recalc(struct clk *clk); | |
543d9378 PW |
368 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
369 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | |
df791b3e | 370 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); |
435699db | 371 | |
530e544f PW |
372 | /* clkt_iclk.c public functions */ |
373 | extern void omap2_clkt_iclk_allow_idle(struct clk *clk); | |
374 | extern void omap2_clkt_iclk_deny_idle(struct clk *clk); | |
375 | ||
543d9378 | 376 | u32 omap2_get_dpll_rate(struct clk *clk); |
911bd739 | 377 | void omap2_init_dpll_parent(struct clk *clk); |
435699db | 378 | |
543d9378 | 379 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
56213ca4 TL |
380 | |
381 | ||
382 | #ifdef CONFIG_ARCH_OMAP2 | |
383 | void omap2xxx_clk_prepare_for_reboot(void); | |
384 | #else | |
385 | static inline void omap2xxx_clk_prepare_for_reboot(void) | |
386 | { | |
387 | } | |
388 | #endif | |
389 | ||
390 | #ifdef CONFIG_ARCH_OMAP3 | |
391 | void omap3_clk_prepare_for_reboot(void); | |
392 | #else | |
393 | static inline void omap3_clk_prepare_for_reboot(void) | |
394 | { | |
395 | } | |
396 | #endif | |
397 | ||
398 | #ifdef CONFIG_ARCH_OMAP4 | |
399 | void omap4_clk_prepare_for_reboot(void); | |
400 | #else | |
401 | static inline void omap4_clk_prepare_for_reboot(void) | |
402 | { | |
403 | } | |
404 | #endif | |
405 | ||
72350b29 PW |
406 | int omap2_dflt_clk_enable(struct clk *clk); |
407 | void omap2_dflt_clk_disable(struct clk *clk); | |
408 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |
409 | u8 *other_bit); | |
410 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | |
419cc97d | 411 | u8 *idlest_bit, u8 *idlest_val); |
4d30e82c PW |
412 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); |
413 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |
414 | const char *core_ck_name, | |
415 | const char *mpu_ck_name); | |
543d9378 | 416 | |
99541195 | 417 | extern u16 cpu_mask; |
d8a94458 | 418 | |
b36ee724 | 419 | extern const struct clkops clkops_omap2_dflt_wait; |
7c43d547 | 420 | extern const struct clkops clkops_dummy; |
bc51da4e | 421 | extern const struct clkops clkops_omap2_dflt; |
b36ee724 | 422 | |
82e9bd58 | 423 | extern struct clk_functions omap2_clk_functions; |
d8a94458 | 424 | extern struct clk *vclk, *sclk; |
82e9bd58 | 425 | |
d8a94458 PW |
426 | extern const struct clksel_rate gpt_32k_rates[]; |
427 | extern const struct clksel_rate gpt_sys_rates[]; | |
428 | extern const struct clksel_rate gfx_l3_rates[]; | |
22411396 | 429 | extern const struct clksel_rate dsp_ick_rates[]; |
543d9378 | 430 | |
530e544f PW |
431 | extern const struct clkops clkops_omap2_iclk_dflt_wait; |
432 | extern const struct clkops clkops_omap2_iclk_dflt; | |
433 | extern const struct clkops clkops_omap2_iclk_idle_only; | |
e892b252 | 434 | extern const struct clkops clkops_omap2_mdmclk_dflt_wait; |
0fd0c21b | 435 | extern const struct clkops clkops_omap2xxx_dpll_ops; |
657ebfad | 436 | extern const struct clkops clkops_omap3_noncore_dpll_ops; |
6c6f5a74 | 437 | extern const struct clkops clkops_omap3_core_dpll_ops; |
70db8a62 | 438 | extern const struct clkops clkops_omap4_dpllmx_ops; |
657ebfad | 439 | |
571efa0d PW |
440 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ |
441 | extern const struct clksel_rate div_1_0_rates[]; | |
442 | extern const struct clksel_rate div_1_1_rates[]; | |
443 | extern const struct clksel_rate div_1_2_rates[]; | |
444 | extern const struct clksel_rate div_1_3_rates[]; | |
445 | extern const struct clksel_rate div_1_4_rates[]; | |
446 | extern const struct clksel_rate div31_1to31_rates[]; | |
447 | ||
448 | /* clocks shared between various OMAP SoCs */ | |
449 | extern struct clk virt_19200000_ck; | |
450 | extern struct clk virt_26000000_ck; | |
451 | ||
e30384ab VH |
452 | extern int am33xx_clk_init(void); |
453 | ||
543d9378 | 454 | #endif |