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ARM: OMAP: clock: Get rid of some clkdm assocations within clks
[deliverable/linux.git] / arch / arm / mach-omap2 / clock.h
CommitLineData
543d9378
PW		 1/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
d8a94458 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
530e544f 5 * Copyright (C) 2004-2011 Nokia Corporation
543d9378 6 *
a16e9703
TL		 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
543d9378
PW		 9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
12706c54 19#include <linux/kernel.h>
a135eaae
PW		 20#include <linux/list.h>
21
e10dd62f
PW		 22#include <linux/clkdev.h>
23
24struct omap_clk {
25 u16 cpu;
26 struct clk_lookup lk;
27};
28
29#define CLK(dev, con, ck, cp) \
30 { \
31 .cpu = cp, \
32 .lk = { \
33 .dev_id = dev, \
34 .con_id = con, \
35 .clk = ck, \
36 }, \
37 }
38
39/* Platform flags for the clkdev-OMAP integration code */
40#define CK_242X (1 << 0)
41#define CK_243X (1 << 1) /* 243x, 253x */
42#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
43#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
44#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
45#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
46#define CK_443X (1 << 6)
47#define CK_TI816X (1 << 7)
48#define CK_446X (1 << 8)
49#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
50
51
52#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
53#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
54
b5a2366c
RN		 55#ifdef CONFIG_COMMON_CLK
56#include <linux/clk-provider.h>
57
58struct clockdomain;
59#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
60
61#else
62
a135eaae
PW		 63struct module;
64struct clk;
65struct clockdomain;
66
67/* Temporary, needed during the common clock framework conversion */
68#define __clk_get_name(clk) (clk->name)
69#define __clk_get_parent(clk) (clk->parent)
70#define __clk_get_rate(clk) (clk->rate)
71
72/**
73 * struct clkops - some clock function pointers
74 * @enable: fn ptr that enables the current clock in hardware
75 * @disable: fn ptr that enables the current clock in hardware
76 * @find_idlest: function returning the IDLEST register for the clock's IP blk
77 * @find_companion: function returning the "companion" clk reg for the clock
78 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
79 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
80 *
81 * A "companion" clk is an accompanying clock to the one being queried
82 * that must be enabled for the IP module connected to the clock to
83 * become accessible by the hardware. Neither @find_idlest nor
84 * @find_companion should be needed; that information is IP
85 * block-specific; the hwmod code has been created to handle this, but
86 * until hwmod data is ready and drivers have been converted to use PM
87 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
88 * @find_companion must, unfortunately, remain.
89 */
90struct clkops {
91 int (*enable)(struct clk *);
92 void (*disable)(struct clk *);
93 void (*find_idlest)(struct clk *, void __iomem **,
94 u8 *, u8 *);
95 void (*find_companion)(struct clk *, void __iomem **,
96 u8 *);
97 void (*allow_idle)(struct clk *);
98 void (*deny_idle)(struct clk *);
99};
b5a2366c 100#endif
a135eaae
PW		 101
102/* struct clksel_rate.flags possibilities */
103#define RATE_IN_242X (1 << 0)
104#define RATE_IN_243X (1 << 1)
105#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
106#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
107#define RATE_IN_36XX (1 << 4)
108#define RATE_IN_4430 (1 << 5)
109#define RATE_IN_TI816X (1 << 6)
110#define RATE_IN_4460 (1 << 7)
111#define RATE_IN_AM33XX (1 << 8)
112#define RATE_IN_TI814X (1 << 9)
113
114#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
115#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
116#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
117#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
118
119/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
120#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
121
122
123/**
124 * struct clksel_rate - register bitfield values corresponding to clk divisors
125 * @val: register bitfield value (shifted to bit 0)
126 * @div: clock divisor corresponding to @val
127 * @flags: (see "struct clksel_rate.flags possibilities" above)
128 *
129 * @val should match the value of a read from struct clk.clksel_reg
130 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
131 *
132 * @div is the divisor that should be applied to the parent clock's rate
133 * to produce the current clock's rate.
134 */
135struct clksel_rate {
136 u32 val;
137 u8 div;
138 u16 flags;
139};
140
141/**
142 * struct clksel - available parent clocks, and a pointer to their divisors
143 * @parent: struct clk * to a possible parent clock
144 * @rates: available divisors for this parent clock
145 *
146 * A struct clksel is always associated with one or more struct clks
147 * and one or more struct clksel_rates.
148 */
149struct clksel {
150 struct clk *parent;
151 const struct clksel_rate *rates;
152};
153
154/**
155 * struct dpll_data - DPLL registers and integration data
156 * @mult_div1_reg: register containing the DPLL M and N bitfields
157 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
158 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
159 * @clk_bypass: struct clk pointer to the clock's bypass clock input
160 * @clk_ref: struct clk pointer to the clock's reference clock input
161 * @control_reg: register containing the DPLL mode bitfield
162 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
163 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
164 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
165 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
166 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
167 * @min_divider: minimum valid non-bypass divider value (actual)
168 * @max_divider: maximum valid non-bypass divider value (actual)
169 * @modes: possible values of @enable_mask
170 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
171 * @idlest_reg: register containing the DPLL idle status bitfield
172 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
173 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
174 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
175 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
176 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
177 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
178 * @flags: DPLL type/features (see below)
179 *
180 * Possible values for @flags:
181 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
182 *
183 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
184 *
185 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
186 * correct to only have one @clk_bypass pointer.
187 *
188 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
189 * @last_rounded_n) should be separated from the runtime-fixed fields
190 * and placed into a different structure, so that the runtime-fixed data
191 * can be placed into read-only space.
192 */
193struct dpll_data {
194 void __iomem *mult_div1_reg;
195 u32 mult_mask;
196 u32 div1_mask;
197 struct clk *clk_bypass;
198 struct clk *clk_ref;
199 void __iomem *control_reg;
200 u32 enable_mask;
201 unsigned long last_rounded_rate;
202 u16 last_rounded_m;
203 u16 max_multiplier;
204 u8 last_rounded_n;
205 u8 min_divider;
206 u16 max_divider;
207 u8 modes;
208 void __iomem *autoidle_reg;
209 void __iomem *idlest_reg;
210 u32 autoidle_mask;
211 u32 freqsel_mask;
212 u32 idlest_mask;
213 u32 dco_mask;
214 u32 sddiv_mask;
215 u8 auto_recal_bit;
216 u8 recal_en_bit;
217 u8 recal_st_bit;
218 u8 flags;
219};
220
221/*
222 * struct clk.flags possibilities
223 *
224 * XXX document the rest of the clock flags here
225 *
226 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
227 * bits share the same register. This flag allows the
228 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
229 * should be used. This is a temporary solution - a better approach
230 * would be to associate clock type-specific data with the clock,
231 * similar to the struct dpll_data approach.
232 */
233#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
234#define CLOCK_IDLE_CONTROL (1 << 1)
235#define CLOCK_NO_IDLE_PARENT (1 << 2)
236#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
237#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
238#define CLOCK_CLKOUTX2 (1 << 5)
239
b5a2366c
RN		 240#ifdef CONFIG_COMMON_CLK
241/**
242 * struct clk_hw_omap - OMAP struct clk
243 * @node: list_head connecting this clock into the full clock list
244 * @enable_reg: register to write to enable the clock (see @enable_bit)
245 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
246 * @flags: see "struct clk.flags possibilities" above
247 * @clksel_reg: for clksel clks, register va containing src/divisor select
248 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
249 * @clksel: for clksel clks, pointer to struct clksel for this clock
250 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
251 * @clkdm_name: clockdomain name that this clock is contained in
252 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
253 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
254 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
255 *
256 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
257 * clock code converted to use clksel.
258 *
259 */
260
261struct clk_hw_omap_ops;
262
263struct clk_hw_omap {
264 struct clk_hw hw;
265 struct list_head node;
266 unsigned long fixed_rate;
267 u8 fixed_div;
268 void __iomem *enable_reg;
269 u8 enable_bit;
270 u8 flags;
271 void __iomem *clksel_reg;
272 u32 clksel_mask;
273 const struct clksel *clksel;
274 struct dpll_data *dpll_data;
275 const char *clkdm_name;
276 struct clockdomain *clkdm;
277 const struct clk_hw_omap_ops *ops;
278};
279
280struct clk_hw_omap_ops {
281 void (*find_idlest)(struct clk_hw_omap *oclk,
282 void __iomem **idlest_reg,
283 u8 *idlest_bit, u8 *idlest_val);
284 void (*find_companion)(struct clk_hw_omap *oclk,
285 void __iomem **other_reg,
286 u8 *other_bit);
287 void (*allow_idle)(struct clk_hw_omap *oclk);
288 void (*deny_idle)(struct clk_hw_omap *oclk);
289};
290
291unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
292 unsigned long parent_rate);
293#else
a135eaae
PW		 294/**
295 * struct clk - OMAP struct clk
296 * @node: list_head connecting this clock into the full clock list
297 * @ops: struct clkops * for this clock
298 * @name: the name of the clock in the hardware (used in hwmod data and debug)
299 * @parent: pointer to this clock's parent struct clk
300 * @children: list_head connecting to the child clks' @sibling list_heads
301 * @sibling: list_head connecting this clk to its parent clk's @children
302 * @rate: current clock rate
303 * @enable_reg: register to write to enable the clock (see @enable_bit)
304 * @recalc: fn ptr that returns the clock's current rate
305 * @set_rate: fn ptr that can change the clock's current rate
306 * @round_rate: fn ptr that can round the clock's current rate
307 * @init: fn ptr to do clock-specific initialization
308 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
309 * @usecount: number of users that have requested this clock to be enabled
310 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
311 * @flags: see "struct clk.flags possibilities" above
312 * @clksel_reg: for clksel clks, register va containing src/divisor select
313 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
314 * @clksel: for clksel clks, pointer to struct clksel for this clock
315 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
316 * @clkdm_name: clockdomain name that this clock is contained in
317 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
318 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
319 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
320 *
321 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
322 * clock code converted to use clksel.
323 *
324 * XXX @usecount is poorly named. It should be "enable_count" or
325 * something similar. "users" in the description refers to kernel
326 * code (core code or drivers) that have called clk_enable() and not
327 * yet called clk_disable(); the usecount of parent clocks is also
328 * incremented by the clock code when clk_enable() is called on child
329 * clocks and decremented by the clock code when clk_disable() is
330 * called on child clocks.
331 *
332 * XXX @clkdm, @usecount, @children, @sibling should be marked for
333 * internal use only.
334 *
335 * @children and @sibling are used to optimize parent-to-child clock
336 * tree traversals. (child-to-parent traversals use @parent.)
337 *
338 * XXX The notion of the clock's current rate probably needs to be
339 * separated from the clock's target rate.
340 */
341struct clk {
342 struct list_head node;
343 const struct clkops *ops;
344 const char *name;
345 struct clk *parent;
346 struct list_head children;
347 struct list_head sibling; /* node for children */
348 unsigned long rate;
349 void __iomem *enable_reg;
350 unsigned long (*recalc)(struct clk *);
351 int (*set_rate)(struct clk *, unsigned long);
352 long (*round_rate)(struct clk *, unsigned long);
353 void (*init)(struct clk *);
354 u8 enable_bit;
355 s8 usecount;
356 u8 fixed_div;
357 u8 flags;
358 void __iomem *clksel_reg;
359 u32 clksel_mask;
360 const struct clksel *clksel;
361 struct dpll_data *dpll_data;
362 const char *clkdm_name;
363 struct clockdomain *clkdm;
364#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
365 struct dentry *dent; /* For visible tree hierarchy */
366#endif
367};
368
369struct clk_functions {
370 int (*clk_enable)(struct clk *clk);
371 void (*clk_disable)(struct clk *clk);
372 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
373 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
374 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
375 void (*clk_allow_idle)(struct clk *clk);
376 void (*clk_deny_idle)(struct clk *clk);
377 void (*clk_disable_unused)(struct clk *clk);
378};
379
380extern int mpurate;
381
382extern int clk_init(struct clk_functions *custom_clocks);
383extern void clk_preinit(struct clk *clk);
384extern int clk_register(struct clk *clk);
385extern void clk_reparent(struct clk *child, struct clk *parent);
386extern void clk_unregister(struct clk *clk);
387extern void propagate_rate(struct clk *clk);
388extern void recalculate_root_clocks(void);
389extern unsigned long followparent_recalc(struct clk *clk);
390extern void clk_enable_init_clocks(void);
391unsigned long omap_fixed_divisor_recalc(struct clk *clk);
392extern struct clk *omap_clk_get_by_name(const char *name);
393extern int omap_clk_enable_autoidle_all(void);
394extern int omap_clk_disable_autoidle_all(void);
395
396extern const struct clkops clkops_null;
397
398extern struct clk dummy_ck;
12706c54 399
32cc0021 400#endif /* CONFIG_COMMON_CLK */
543d9378 401
c0bf3132
RK		 402/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
403#define CORE_CLK_SRC_32K 0x0
404#define CORE_CLK_SRC_DPLL 0x1
405#define CORE_CLK_SRC_DPLL_X2 0x2
406
407/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
408#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
409#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
410#define OMAP2XXX_EN_DPLL_LOCKED 0x3
411
412/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
413#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
414#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
415#define OMAP3XXX_EN_DPLL_LOCKED 0x7
416
16975a79
RN		 417/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
418#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
419#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
420#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
421#define OMAP4XXX_EN_DPLL_LOCKED 0x7
422
a1391d27
RN		 423/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
424#define DPLL_LOW_POWER_STOP 0x1
425#define DPLL_LOW_POWER_BYPASS 0x5
426#define DPLL_LOCKED 0x7
427
358965d7
RW		 428/* DPLL Type and DCO Selection Flags */
429#define DPLL_J_TYPE 0x1
358965d7 430
32cc0021 431#ifndef CONFIG_COMMON_CLK
543d9378
PW		 432int omap2_clk_enable(struct clk *clk);
433void omap2_clk_disable(struct clk *clk);
434long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
435int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
436int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
32cc0021
MT		 437#endif /* CONFIG_COMMON_CLK */
438
439#ifdef CONFIG_COMMON_CLK
440long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
441 unsigned long *parent_rate);
442unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
443int omap3_noncore_dpll_enable(struct clk_hw *hw);
444void omap3_noncore_dpll_disable(struct clk_hw *hw);
445int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
446 unsigned long parent_rate);
447u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
448void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
449void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
450unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
451 unsigned long parent_rate);
452int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
453void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
454void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
455unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
456 unsigned long parent_rate);
457long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
458 unsigned long target_rate,
459 unsigned long *parent_rate);
460#else
88b8ba90 461long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
a1391d27
RN		 462unsigned long omap3_dpll_recalc(struct clk *clk);
463unsigned long omap3_clkoutx2_recalc(struct clk *clk);
464void omap3_dpll_allow_idle(struct clk *clk);
465void omap3_dpll_deny_idle(struct clk *clk);
466u32 omap3_dpll_autoidle_read(struct clk *clk);
467int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
468int omap3_noncore_dpll_enable(struct clk *clk);
469void omap3_noncore_dpll_disable(struct clk *clk);
97f67898
RN		 470int omap4_dpllmx_gatectrl_read(struct clk *clk);
471void omap4_dpllmx_allow_gatectrl(struct clk *clk);
472void omap4_dpllmx_deny_gatectrl(struct clk *clk);
a1900f2e
MT		 473long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
474unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
32cc0021 475#endif
543d9378
PW		 476
477#ifdef CONFIG_OMAP_RESET_CLOCKS
478void omap2_clk_disable_unused(struct clk *clk);
479#else
480#define omap2_clk_disable_unused NULL
481#endif
32cc0021
MT		 482#ifdef CONFIG_COMMON_CLK
483void omap2_init_clk_clkdm(struct clk_hw *clk);
484#else
333943ba 485void omap2_init_clk_clkdm(struct clk *clk);
32cc0021 486#endif
12706c54 487void __init omap2_clk_disable_clkdm_control(void);
435699db
PW		 488
489/* clkt_clksel.c public functions */
32cc0021
MT		 490#ifdef CONFIG_COMMON_CLK
491u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
492 unsigned long target_rate,
493 u32 *new_div);
494u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
495unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
496long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
497 unsigned long *parent_rate);
498int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
499 unsigned long parent_rate);
500int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
501#else
543d9378
PW		 502u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
503 u32 *new_div);
435699db
PW		 504void omap2_init_clksel_parent(struct clk *clk);
505unsigned long omap2_clksel_recalc(struct clk *clk);
543d9378
PW		 506long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
507int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
df791b3e 508int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
32cc0021 509#endif
435699db 510
530e544f 511/* clkt_iclk.c public functions */
b4777a21
RN		 512#ifdef CONFIG_COMMON_CLK
513extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
514extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
515#else
530e544f
PW		 516extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
517extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
b4777a21 518#endif
530e544f 519
32cc0021
MT		 520#ifdef CONFIG_COMMON_CLK
521u8 omap2_init_dpll_parent(struct clk_hw *hw);
522unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
523#else
543d9378 524u32 omap2_get_dpll_rate(struct clk *clk);
911bd739 525void omap2_init_dpll_parent(struct clk *clk);
32cc0021 526#endif
435699db 527
32cc0021
MT		 528#ifdef CONFIG_COMMON_CLK
529int omap2_dflt_clk_enable(struct clk_hw *hw);
530void omap2_dflt_clk_disable(struct clk_hw *hw);
531int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
532void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
533 void __iomem **other_reg,
534 u8 *other_bit);
535void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
536 void __iomem **idlest_reg,
537 u8 *idlest_bit, u8 *idlest_val);
23fb8ba3
RN		 538void omap2_init_clk_hw_omap_clocks(struct clk *clk);
539int omap2_clk_enable_autoidle_all(void);
540int omap2_clk_disable_autoidle_all(void);
8577413c 541void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
32cc0021 542#else
72350b29
PW		 543int omap2_dflt_clk_enable(struct clk *clk);
544void omap2_dflt_clk_disable(struct clk *clk);
545void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
546 u8 *other_bit);
547void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
419cc97d 548 u8 *idlest_bit, u8 *idlest_val);
32cc0021 549#endif
4d30e82c
PW		 550int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
551void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
552 const char *core_ck_name,
553 const char *mpu_ck_name);
543d9378 554
99541195 555extern u16 cpu_mask;
d8a94458 556
b36ee724 557extern const struct clkops clkops_omap2_dflt_wait;
7c43d547 558extern const struct clkops clkops_dummy;
bc51da4e 559extern const struct clkops clkops_omap2_dflt;
b36ee724 560
82e9bd58
PW		 561extern struct clk_functions omap2_clk_functions;
562
d8a94458
PW		 563extern const struct clksel_rate gpt_32k_rates[];
564extern const struct clksel_rate gpt_sys_rates[];
565extern const struct clksel_rate gfx_l3_rates[];
22411396 566extern const struct clksel_rate dsp_ick_rates[];
543d9378 567
32cc0021
MT		 568#ifdef CONFIG_COMMON_CLK
569extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
570extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
571extern const struct clk_hw_omap_ops clkhwops_wait;
572extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
b4777a21
RN		 573extern const struct clk_hw_omap_ops clkhwops_iclk;
574extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
575extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
576extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
577extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
578extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
579extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
580extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
581extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
582extern const struct clk_hw_omap_ops clkhwops_apll54;
583extern const struct clk_hw_omap_ops clkhwops_apll96;
584extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
585extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
586#else
530e544f
PW		 587extern const struct clkops clkops_omap2_iclk_dflt_wait;
588extern const struct clkops clkops_omap2_iclk_dflt;
589extern const struct clkops clkops_omap2_iclk_idle_only;
e892b252 590extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
0fd0c21b 591extern const struct clkops clkops_omap2xxx_dpll_ops;
657ebfad 592extern const struct clkops clkops_omap3_noncore_dpll_ops;
6c6f5a74 593extern const struct clkops clkops_omap3_core_dpll_ops;
70db8a62 594extern const struct clkops clkops_omap4_dpllmx_ops;
b4777a21 595#endif /* CONFIG_COMMON_CLK */
657ebfad 596
571efa0d
PW		 597/* clksel_rate blocks shared between OMAP44xx and AM33xx */
598extern const struct clksel_rate div_1_0_rates[];
599extern const struct clksel_rate div_1_1_rates[];
600extern const struct clksel_rate div_1_2_rates[];
601extern const struct clksel_rate div_1_3_rates[];
602extern const struct clksel_rate div_1_4_rates[];
603extern const struct clksel_rate div31_1to31_rates[];
604
32cc0021 605#ifndef CONFIG_COMMON_CLK
571efa0d
PW		 606/* clocks shared between various OMAP SoCs */
607extern struct clk virt_19200000_ck;
608extern struct clk virt_26000000_ck;
32cc0021 609#endif
571efa0d 610
e30384ab
VH		 611extern int am33xx_clk_init(void);
612
32cc0021
MT		 613#ifdef CONFIG_COMMON_CLK
614extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
615extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
616#endif
617
543d9378 618#endif
Linux kernel - Deliverables
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