[deliverable/linux.git] / arch / arm / mach-omap2 / clock.h

/*
 *  linux/arch/arm/mach-omap2/clock.h
 *
 *  Copyright (C) 2005-2009 Texas Instruments, Inc.
 *  Copyright (C) 2004-2009 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H

#include <plat/clock.h>

/* The maximum error between a target DPLL rate and the rounded rate in Hz */
#define DEFAULT_DPLL_RATE_TOLERANCE	50000

/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K		0x0
#define CORE_CLK_SRC_DPLL		0x1
#define CORE_CLK_SRC_DPLL_X2		0x2

/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP2XXX_EN_DPLL_LPBYPASS		0x1
#define OMAP2XXX_EN_DPLL_FRBYPASS		0x2
#define OMAP2XXX_EN_DPLL_LOCKED			0x3

/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP3XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP3XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP3XXX_EN_DPLL_LOCKED			0x7

/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS		0x4
#define OMAP4XXX_EN_DPLL_LPBYPASS		0x5
#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6
#define OMAP4XXX_EN_DPLL_LOCKED			0x7

/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP	0x1
#define DPLL_LOW_POWER_BYPASS	0x5
#define DPLL_LOCKED		0x7

/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE		0x1

int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap3_dpll_recalc(struct clk *clk);
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
void omap3_dpll_allow_idle(struct clk *clk);
void omap3_dpll_deny_idle(struct clk *clk);
u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
int omap4_dpllmx_gatectrl_read(struct clk *clk);
void omap4_dpllmx_allow_gatectrl(struct clk *clk);
void omap4_dpllmx_deny_gatectrl(struct clk *clk);

#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
#else
#define omap2_clk_disable_unused	NULL
#endif

void omap2_init_clk_clkdm(struct clk *clk);

/* clkt_clksel.c public functions */
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
				u32 *new_div);
void omap2_init_clksel_parent(struct clk *clk);
unsigned long omap2_clksel_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);

u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);

int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);


#ifdef CONFIG_ARCH_OMAP2
void omap2xxx_clk_prepare_for_reboot(void);
#else
static inline void omap2xxx_clk_prepare_for_reboot(void)
{
}
#endif

#ifdef CONFIG_ARCH_OMAP3
void omap3_clk_prepare_for_reboot(void);
#else
static inline void omap3_clk_prepare_for_reboot(void)
{
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void omap4_clk_prepare_for_reboot(void);
#else
static inline void omap4_clk_prepare_for_reboot(void)
{
}
#endif

int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
				u8 *idlest_bit, u8 *idlest_val);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
			       const char *core_ck_name,
			       const char *mpu_ck_name);

extern u8 cpu_mask;

extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
extern const struct clkops clkops_omap2_dflt;

extern struct clk_functions omap2_clk_functions;
extern struct clk *vclk, *sclk;

extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];

#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#else
#define omap2_clk_init_cpufreq_table	0
#define omap2_clk_exit_cpufreq_table	0
#endif

extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops;
extern const struct clkops clkops_omap4_dpllmx_ops;

#endif
Commit	Line	Data
543d9378 PW	1	/*
	2	* linux/arch/arm/mach-omap2/clock.h
	3	*
d8a94458 PW	4	* Copyright (C) 2005-2009 Texas Instruments, Inc.
d8a94458 PW	5	* Copyright (C) 2004-2009 Nokia Corporation
543d9378	6	*
a16e9703 TL	7	* Contacts:
a16e9703 TL	8	* Richard Woodruff <r-woodruff2@ti.com>
543d9378 PW	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
	17	#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
	18
ce491cf8	19	#include <plat/clock.h>
543d9378	20
88b8ba90 PW	21	/* The maximum error between a target DPLL rate and the rounded rate in Hz */
	22	#define DEFAULT_DPLL_RATE_TOLERANCE 50000
	23
c0bf3132 RK	24	/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
	25	#define CORE_CLK_SRC_32K 0x0
	26	#define CORE_CLK_SRC_DPLL 0x1
	27	#define CORE_CLK_SRC_DPLL_X2 0x2
	28
	29	/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
	30	#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
	31	#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
	32	#define OMAP2XXX_EN_DPLL_LOCKED 0x3
	33
	34	/* OMAP3xxx CM_CLKEN_PLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	35	#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
	36	#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
	37	#define OMAP3XXX_EN_DPLL_LOCKED 0x7
	38
16975a79 RN	39	/* OMAP4xxx CM_CLKMODE_DPLL.EN__DPLL bits - for omap2_get_dpll_rate() */
	40	#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
	41	#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
	42	#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
	43	#define OMAP4XXX_EN_DPLL_LOCKED 0x7
	44
a1391d27 RN	45	/* CM_CLKEN_PLL.EN bit values - not all are available for every DPLL */
	46	#define DPLL_LOW_POWER_STOP 0x1
	47	#define DPLL_LOW_POWER_BYPASS 0x5
	48	#define DPLL_LOCKED 0x7
	49
358965d7 RW	50	/* DPLL Type and DCO Selection Flags */
358965d7 RW	51	#define DPLL_J_TYPE 0x1
358965d7	52
543d9378 PW	53	int omap2_clk_enable(struct clk *clk);
	54	void omap2_clk_disable(struct clk *clk);
	55	long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
	56	int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
	57	int omap2_clk_set_parent(struct clk clk, struct clk new_parent);
fecb494b	58	int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
88b8ba90	59	long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
a1391d27 RN	60	unsigned long omap3_dpll_recalc(struct clk *clk);
	61	unsigned long omap3_clkoutx2_recalc(struct clk *clk);
	62	void omap3_dpll_allow_idle(struct clk *clk);
	63	void omap3_dpll_deny_idle(struct clk *clk);
	64	u32 omap3_dpll_autoidle_read(struct clk *clk);
	65	int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
	66	int omap3_noncore_dpll_enable(struct clk *clk);
	67	void omap3_noncore_dpll_disable(struct clk *clk);
97f67898 RN	68	int omap4_dpllmx_gatectrl_read(struct clk *clk);
	69	void omap4_dpllmx_allow_gatectrl(struct clk *clk);
	70	void omap4_dpllmx_deny_gatectrl(struct clk *clk);
543d9378 PW	71
	72	#ifdef CONFIG_OMAP_RESET_CLOCKS
	73	void omap2_clk_disable_unused(struct clk *clk);
	74	#else
	75	#define omap2_clk_disable_unused NULL
	76	#endif
	77
333943ba	78	void omap2_init_clk_clkdm(struct clk *clk);
435699db PW	79
435699db PW	80	/* clkt_clksel.c public functions */
543d9378 PW	81	u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
543d9378 PW	82	u32 *new_div);
435699db PW	83	void omap2_init_clksel_parent(struct clk *clk);
435699db PW	84	unsigned long omap2_clksel_recalc(struct clk *clk);
543d9378 PW	85	long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
543d9378 PW	86	int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
df791b3e	87	int omap2_clksel_set_parent(struct clk clk, struct clk new_parent);
435699db	88
543d9378	89	u32 omap2_get_dpll_rate(struct clk *clk);
911bd739	90	void omap2_init_dpll_parent(struct clk *clk);
435699db	91
543d9378	92	int omap2_wait_clock_ready(void __iomem reg, u32 cval, const char name);
56213ca4 TL	93
	94
	95	#ifdef CONFIG_ARCH_OMAP2
	96	void omap2xxx_clk_prepare_for_reboot(void);
	97	#else
	98	static inline void omap2xxx_clk_prepare_for_reboot(void)
	99	{
	100	}
	101	#endif
	102
	103	#ifdef CONFIG_ARCH_OMAP3
	104	void omap3_clk_prepare_for_reboot(void);
	105	#else
	106	static inline void omap3_clk_prepare_for_reboot(void)
	107	{
	108	}
	109	#endif
	110
	111	#ifdef CONFIG_ARCH_OMAP4
	112	void omap4_clk_prepare_for_reboot(void);
	113	#else
	114	static inline void omap4_clk_prepare_for_reboot(void)
	115	{
	116	}
	117	#endif
	118
72350b29 PW	119	int omap2_dflt_clk_enable(struct clk *clk);
	120	void omap2_dflt_clk_disable(struct clk *clk);
	121	void omap2_clk_dflt_find_companion(struct clk clk, void __iomem *other_reg,
	122	u8 *other_bit);
	123	void omap2_clk_dflt_find_idlest(struct clk clk, void __iomem *idlest_reg,
419cc97d	124	u8 idlest_bit, u8 idlest_val);
4d30e82c PW	125	int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
	126	void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
	127	const char *core_ck_name,
	128	const char *mpu_ck_name);
543d9378	129
d8a94458 PW	130	extern u8 cpu_mask;
d8a94458 PW	131
b36ee724	132	extern const struct clkops clkops_omap2_dflt_wait;
7c43d547	133	extern const struct clkops clkops_dummy;
bc51da4e	134	extern const struct clkops clkops_omap2_dflt;
b36ee724	135
82e9bd58	136	extern struct clk_functions omap2_clk_functions;
d8a94458	137	extern struct clk vclk, sclk;
82e9bd58	138
d8a94458 PW	139	extern const struct clksel_rate gpt_32k_rates[];
	140	extern const struct clksel_rate gpt_sys_rates[];
	141	extern const struct clksel_rate gfx_l3_rates[];
543d9378	142
088ef950	143	#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
69ecefca PW	144	extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
	145	extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
	146	#else
	147	#define omap2_clk_init_cpufreq_table 0
	148	#define omap2_clk_exit_cpufreq_table 0
	149	#endif
543d9378	150
657ebfad	151	extern const struct clkops clkops_omap3_noncore_dpll_ops;
6c6f5a74	152	extern const struct clkops clkops_omap3_core_dpll_ops;
70db8a62	153	extern const struct clkops clkops_omap4_dpllmx_ops;
657ebfad	154
543d9378	155	#endif