Commit | Line | Data |
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046d6b28 | 1 | /* |
81b34fbe | 2 | * linux/arch/arm/mach-omap2/clock2420_data.c |
046d6b28 | 3 | * |
d8a94458 | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
93340a22 | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
046d6b28 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 TL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
d8a94458 PW |
16 | #include <linux/kernel.h> |
17 | #include <linux/clk.h> | |
93340a22 | 18 | #include <linux/list.h> |
046d6b28 | 19 | |
d8a94458 | 20 | #include <plat/clkdev_omap.h> |
6b8858a9 | 21 | |
d8a94458 PW |
22 | #include "clock.h" |
23 | #include "clock2xxx.h" | |
24 | #include "opp2xxx.h" | |
6b8858a9 PW |
25 | #include "prm.h" |
26 | #include "cm.h" | |
27 | #include "prm-regbits-24xx.h" | |
28 | #include "cm-regbits-24xx.h" | |
29 | #include "sdrc.h" | |
30 | ||
81b34fbe PW |
31 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR |
32 | ||
33 | /* | |
34 | * 2420 clock tree. | |
046d6b28 TL |
35 | * |
36 | * NOTE:In many cases here we are assigning a 'default' parent. In many | |
37 | * cases the parent is selectable. The get/set parent calls will also | |
38 | * switch sources. | |
39 | * | |
40 | * Many some clocks say always_enabled, but they can be auto idled for | |
41 | * power savings. They will always be available upon clock request. | |
42 | * | |
43 | * Several sources are given initial rates which may be wrong, this will | |
44 | * be fixed up in the init func. | |
45 | * | |
46 | * Things are broadly separated below by clock domains. It is | |
47 | * noteworthy that most periferals have dependencies on multiple clock | |
48 | * domains. Many get their interface clocks from the L4 domain, but get | |
49 | * functional clocks from fixed sources or other core domain derived | |
50 | * clocks. | |
81b34fbe | 51 | */ |
046d6b28 TL |
52 | |
53 | /* Base external input clocks */ | |
54 | static struct clk func_32k_ck = { | |
55 | .name = "func_32k_ck", | |
897dcded | 56 | .ops = &clkops_null, |
046d6b28 | 57 | .rate = 32000, |
d1b03f61 | 58 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 59 | }; |
e32744b0 | 60 | |
f248076c PW |
61 | static struct clk secure_32k_ck = { |
62 | .name = "secure_32k_ck", | |
63 | .ops = &clkops_null, | |
64 | .rate = 32768, | |
f248076c PW |
65 | .clkdm_name = "wkup_clkdm", |
66 | }; | |
67 | ||
046d6b28 TL |
68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |
70 | .name = "osc_ck", | |
548d8495 | 71 | .ops = &clkops_oscck, |
d1b03f61 | 72 | .clkdm_name = "wkup_clkdm", |
e32744b0 | 73 | .recalc = &omap2_osc_clk_recalc, |
046d6b28 TL |
74 | }; |
75 | ||
d1b03f61 | 76 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
046d6b28 TL |
77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
78 | .name = "sys_ck", /* ~ ref_clk also */ | |
897dcded | 79 | .ops = &clkops_null, |
046d6b28 | 80 | .parent = &osc_ck, |
d1b03f61 | 81 | .clkdm_name = "wkup_clkdm", |
44da0a51 | 82 | .recalc = &omap2xxx_sys_clk_recalc, |
046d6b28 | 83 | }; |
e32744b0 | 84 | |
046d6b28 TL |
85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
86 | .name = "alt_ck", | |
897dcded | 87 | .ops = &clkops_null, |
046d6b28 | 88 | .rate = 54000000, |
d1b03f61 | 89 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 90 | }; |
e32744b0 | 91 | |
046d6b28 TL |
92 | /* |
93 | * Analog domain root source clocks | |
94 | */ | |
95 | ||
96 | /* dpll_ck, is broken out in to special cases through clksel */ | |
6b8858a9 PW |
97 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
98 | * deal with this | |
99 | */ | |
100 | ||
88b8ba90 | 101 | static struct dpll_data dpll_dd = { |
6b8858a9 PW |
102 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
103 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
104 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
c0bf3132 RK |
105 | .clk_bypass = &sys_ck, |
106 | .clk_ref = &sys_ck, | |
107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
93340a22 | 109 | .max_multiplier = 1023, |
95f538ac | 110 | .min_divider = 1, |
88b8ba90 PW |
111 | .max_divider = 16, |
112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
6b8858a9 PW |
113 | }; |
114 | ||
88b8ba90 PW |
115 | /* |
116 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | |
117 | * not just a DPLL | |
118 | */ | |
046d6b28 TL |
119 | static struct clk dpll_ck = { |
120 | .name = "dpll_ck", | |
897dcded | 121 | .ops = &clkops_null, |
046d6b28 | 122 | .parent = &sys_ck, /* Can be func_32k also */ |
6b8858a9 | 123 | .dpll_data = &dpll_dd, |
d1b03f61 | 124 | .clkdm_name = "wkup_clkdm", |
88b8ba90 PW |
125 | .recalc = &omap2_dpllcore_recalc, |
126 | .set_rate = &omap2_reprogram_dpllcore, | |
046d6b28 TL |
127 | }; |
128 | ||
129 | static struct clk apll96_ck = { | |
130 | .name = "apll96_ck", | |
06b16939 | 131 | .ops = &clkops_apll96, |
046d6b28 TL |
132 | .parent = &sys_ck, |
133 | .rate = 96000000, | |
51c19541 | 134 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 135 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
046d6b28 TL |
138 | }; |
139 | ||
140 | static struct clk apll54_ck = { | |
141 | .name = "apll54_ck", | |
06b16939 | 142 | .ops = &clkops_apll54, |
046d6b28 TL |
143 | .parent = &sys_ck, |
144 | .rate = 54000000, | |
51c19541 | 145 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 146 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
046d6b28 TL |
149 | }; |
150 | ||
151 | /* | |
152 | * PRCM digital base sources | |
153 | */ | |
e32744b0 PW |
154 | |
155 | /* func_54m_ck */ | |
156 | ||
157 | static const struct clksel_rate func_54m_apll54_rates[] = { | |
d74b4949 | 158 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
159 | { .div = 0 }, |
160 | }; | |
161 | ||
162 | static const struct clksel_rate func_54m_alt_rates[] = { | |
d74b4949 | 163 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
164 | { .div = 0 }, |
165 | }; | |
166 | ||
167 | static const struct clksel func_54m_clksel[] = { | |
168 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | |
169 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | |
170 | { .parent = NULL }, | |
171 | }; | |
172 | ||
046d6b28 TL |
173 | static struct clk func_54m_ck = { |
174 | .name = "func_54m_ck", | |
57137181 | 175 | .ops = &clkops_null, |
046d6b28 | 176 | .parent = &apll54_ck, /* can also be alt_clk */ |
d1b03f61 | 177 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
178 | .init = &omap2_init_clksel_parent, |
179 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 180 | .clksel_mask = OMAP24XX_54M_SOURCE_MASK, |
e32744b0 PW |
181 | .clksel = func_54m_clksel, |
182 | .recalc = &omap2_clksel_recalc, | |
046d6b28 | 183 | }; |
e32744b0 | 184 | |
046d6b28 TL |
185 | static struct clk core_ck = { |
186 | .name = "core_ck", | |
897dcded | 187 | .ops = &clkops_null, |
046d6b28 | 188 | .parent = &dpll_ck, /* can also be 32k */ |
d1b03f61 | 189 | .clkdm_name = "wkup_clkdm", |
6b8858a9 | 190 | .recalc = &followparent_recalc, |
046d6b28 | 191 | }; |
e32744b0 | 192 | |
046d6b28 TL |
193 | static struct clk func_96m_ck = { |
194 | .name = "func_96m_ck", | |
57137181 | 195 | .ops = &clkops_null, |
046d6b28 | 196 | .parent = &apll96_ck, |
d1b03f61 | 197 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 198 | .recalc = &followparent_recalc, |
e32744b0 PW |
199 | }; |
200 | ||
201 | /* func_48m_ck */ | |
202 | ||
203 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
d74b4949 | 204 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
205 | { .div = 0 }, |
206 | }; | |
207 | ||
208 | static const struct clksel_rate func_48m_alt_rates[] = { | |
d74b4949 | 209 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
210 | { .div = 0 }, |
211 | }; | |
212 | ||
213 | static const struct clksel func_48m_clksel[] = { | |
214 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
215 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
216 | { .parent = NULL } | |
046d6b28 TL |
217 | }; |
218 | ||
219 | static struct clk func_48m_ck = { | |
220 | .name = "func_48m_ck", | |
57137181 | 221 | .ops = &clkops_null, |
046d6b28 | 222 | .parent = &apll96_ck, /* 96M or Alt */ |
d1b03f61 | 223 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
224 | .init = &omap2_init_clksel_parent, |
225 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 226 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, |
e32744b0 PW |
227 | .clksel = func_48m_clksel, |
228 | .recalc = &omap2_clksel_recalc, | |
229 | .round_rate = &omap2_clksel_round_rate, | |
230 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
231 | }; |
232 | ||
233 | static struct clk func_12m_ck = { | |
234 | .name = "func_12m_ck", | |
57137181 | 235 | .ops = &clkops_null, |
046d6b28 | 236 | .parent = &func_48m_ck, |
e32744b0 | 237 | .fixed_div = 4, |
d1b03f61 | 238 | .clkdm_name = "wkup_clkdm", |
e9b98f60 | 239 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
240 | }; |
241 | ||
242 | /* Secure timer, only available in secure mode */ | |
243 | static struct clk wdt1_osc_ck = { | |
244 | .name = "ck_wdt1_osc", | |
897dcded | 245 | .ops = &clkops_null, /* RMK: missing? */ |
046d6b28 | 246 | .parent = &osc_ck, |
e32744b0 PW |
247 | .recalc = &followparent_recalc, |
248 | }; | |
249 | ||
250 | /* | |
251 | * The common_clkout* clksel_rate structs are common to | |
252 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | |
253 | * sys_clkout2_* are 2420-only, so the | |
254 | * clksel_rate flags fields are inaccurate for those clocks. This is | |
255 | * harmless since access to those clocks are gated by the struct clk | |
256 | * flags fields, which mark them as 2420-only. | |
257 | */ | |
258 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
d74b4949 | 259 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
260 | { .div = 0 } |
261 | }; | |
262 | ||
263 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
d74b4949 | 264 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
265 | { .div = 0 } |
266 | }; | |
267 | ||
268 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
d74b4949 | 269 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
270 | { .div = 0 } |
271 | }; | |
272 | ||
273 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
d74b4949 | 274 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, |
e32744b0 PW |
275 | { .div = 0 } |
276 | }; | |
277 | ||
278 | static const struct clksel common_clkout_src_clksel[] = { | |
279 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
280 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
281 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
282 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
283 | { .parent = NULL } | |
284 | }; | |
285 | ||
286 | static struct clk sys_clkout_src = { | |
287 | .name = "sys_clkout_src", | |
c1168dc3 | 288 | .ops = &clkops_omap2_dflt, |
e32744b0 | 289 | .parent = &func_54m_ck, |
d1b03f61 | 290 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 291 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
292 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
293 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 294 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
295 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
296 | .clksel = common_clkout_src_clksel, | |
297 | .recalc = &omap2_clksel_recalc, | |
298 | .round_rate = &omap2_clksel_round_rate, | |
299 | .set_rate = &omap2_clksel_set_rate | |
300 | }; | |
301 | ||
302 | static const struct clksel_rate common_clkout_rates[] = { | |
d74b4949 | 303 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
304 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
305 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | |
306 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | |
307 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | |
308 | { .div = 0 }, | |
309 | }; | |
310 | ||
311 | static const struct clksel sys_clkout_clksel[] = { | |
312 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | |
313 | { .parent = NULL } | |
046d6b28 TL |
314 | }; |
315 | ||
316 | static struct clk sys_clkout = { | |
317 | .name = "sys_clkout", | |
57137181 | 318 | .ops = &clkops_null, |
e32744b0 | 319 | .parent = &sys_clkout_src, |
d1b03f61 | 320 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 321 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
322 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
323 | .clksel = sys_clkout_clksel, | |
324 | .recalc = &omap2_clksel_recalc, | |
325 | .round_rate = &omap2_clksel_round_rate, | |
326 | .set_rate = &omap2_clksel_set_rate | |
327 | }; | |
328 | ||
329 | /* In 2430, new in 2420 ES2 */ | |
330 | static struct clk sys_clkout2_src = { | |
331 | .name = "sys_clkout2_src", | |
c1168dc3 | 332 | .ops = &clkops_omap2_dflt, |
e32744b0 | 333 | .parent = &func_54m_ck, |
d1b03f61 | 334 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 335 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
336 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
337 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 338 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
339 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, |
340 | .clksel = common_clkout_src_clksel, | |
046d6b28 | 341 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
342 | .round_rate = &omap2_clksel_round_rate, |
343 | .set_rate = &omap2_clksel_set_rate | |
344 | }; | |
345 | ||
346 | static const struct clksel sys_clkout2_clksel[] = { | |
347 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | |
348 | { .parent = NULL } | |
046d6b28 TL |
349 | }; |
350 | ||
351 | /* In 2430, new in 2420 ES2 */ | |
352 | static struct clk sys_clkout2 = { | |
353 | .name = "sys_clkout2", | |
57137181 | 354 | .ops = &clkops_null, |
e32744b0 | 355 | .parent = &sys_clkout2_src, |
d1b03f61 | 356 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 357 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
358 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
359 | .clksel = sys_clkout2_clksel, | |
046d6b28 | 360 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
361 | .round_rate = &omap2_clksel_round_rate, |
362 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
363 | }; |
364 | ||
b824efae TL |
365 | static struct clk emul_ck = { |
366 | .name = "emul_ck", | |
c1168dc3 | 367 | .ops = &clkops_omap2_dflt, |
b824efae | 368 | .parent = &func_54m_ck, |
d1b03f61 | 369 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 370 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, |
e32744b0 PW |
371 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
372 | .recalc = &followparent_recalc, | |
b824efae TL |
373 | |
374 | }; | |
e32744b0 | 375 | |
046d6b28 TL |
376 | /* |
377 | * MPU clock domain | |
378 | * Clocks: | |
379 | * MPU_FCLK, MPU_ICLK | |
380 | * INT_M_FCLK, INT_M_I_CLK | |
381 | * | |
382 | * - Individual clocks are hardware managed. | |
383 | * - Base divider comes from: CM_CLKSEL_MPU | |
384 | * | |
385 | */ | |
e32744b0 | 386 | static const struct clksel_rate mpu_core_rates[] = { |
d74b4949 | 387 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
388 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
389 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
390 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
391 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
392 | { .div = 0 }, | |
393 | }; | |
394 | ||
395 | static const struct clksel mpu_clksel[] = { | |
396 | { .parent = &core_ck, .rates = mpu_core_rates }, | |
397 | { .parent = NULL } | |
398 | }; | |
399 | ||
046d6b28 TL |
400 | static struct clk mpu_ck = { /* Control cpu */ |
401 | .name = "mpu_ck", | |
897dcded | 402 | .ops = &clkops_null, |
046d6b28 | 403 | .parent = &core_ck, |
d1b03f61 | 404 | .clkdm_name = "mpu_clkdm", |
6b8858a9 PW |
405 | .init = &omap2_init_clksel_parent, |
406 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
407 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | |
e32744b0 | 408 | .clksel = mpu_clksel, |
046d6b28 TL |
409 | .recalc = &omap2_clksel_recalc, |
410 | }; | |
e32744b0 | 411 | |
046d6b28 | 412 | /* |
81b34fbe | 413 | * DSP (2420-UMA+IVA1) clock domain |
046d6b28 | 414 | * Clocks: |
046d6b28 | 415 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
e32744b0 PW |
416 | * |
417 | * Won't be too specific here. The core clock comes into this block | |
418 | * it is divided then tee'ed. One branch goes directly to xyz enable | |
419 | * controls. The other branch gets further divided by 2 then possibly | |
420 | * routed into a synchronizer and out of clocks abc. | |
046d6b28 | 421 | */ |
e32744b0 | 422 | static const struct clksel_rate dsp_fck_core_rates[] = { |
d74b4949 | 423 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
424 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
425 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
426 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
427 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
428 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
429 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
430 | { .div = 0 }, | |
431 | }; | |
432 | ||
433 | static const struct clksel dsp_fck_clksel[] = { | |
434 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
435 | { .parent = NULL } | |
436 | }; | |
437 | ||
438 | static struct clk dsp_fck = { | |
439 | .name = "dsp_fck", | |
b36ee724 | 440 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 441 | .parent = &core_ck, |
d1b03f61 | 442 | .clkdm_name = "dsp_clkdm", |
e32744b0 PW |
443 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
444 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
445 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
446 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | |
447 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
448 | .recalc = &omap2_clksel_recalc, |
449 | }; | |
450 | ||
e32744b0 PW |
451 | /* DSP interface clock */ |
452 | static const struct clksel_rate dsp_irate_ick_rates[] = { | |
d74b4949 | 453 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 | 454 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
455 | { .div = 0 }, |
456 | }; | |
457 | ||
458 | static const struct clksel dsp_irate_ick_clksel[] = { | |
459 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | |
460 | { .parent = NULL } | |
046d6b28 TL |
461 | }; |
462 | ||
d1b03f61 | 463 | /* This clock does not exist as such in the TRM. */ |
e32744b0 PW |
464 | static struct clk dsp_irate_ick = { |
465 | .name = "dsp_irate_ick", | |
57137181 | 466 | .ops = &clkops_null, |
e32744b0 | 467 | .parent = &dsp_fck, |
e32744b0 PW |
468 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
469 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | |
470 | .clksel = dsp_irate_ick_clksel, | |
046d6b28 TL |
471 | .recalc = &omap2_clksel_recalc, |
472 | }; | |
473 | ||
e32744b0 | 474 | /* 2420 only */ |
046d6b28 TL |
475 | static struct clk dsp_ick = { |
476 | .name = "dsp_ick", /* apparently ipi and isp */ | |
b36ee724 | 477 | .ops = &clkops_omap2_dflt_wait, |
e32744b0 | 478 | .parent = &dsp_irate_ick, |
e32744b0 PW |
479 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
480 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | |
481 | }; | |
482 | ||
d1b03f61 PW |
483 | /* |
484 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | |
485 | * the C54x, but which is contained in the DSP powerdomain. Does not | |
486 | * exist on later OMAPs. | |
487 | */ | |
046d6b28 TL |
488 | static struct clk iva1_ifck = { |
489 | .name = "iva1_ifck", | |
b36ee724 | 490 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 491 | .parent = &core_ck, |
d1b03f61 | 492 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
493 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
494 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | |
495 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
496 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | |
497 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
498 | .recalc = &omap2_clksel_recalc, |
499 | }; | |
500 | ||
501 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | |
502 | static struct clk iva1_mpu_int_ifck = { | |
503 | .name = "iva1_mpu_int_ifck", | |
b36ee724 | 504 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 505 | .parent = &iva1_ifck, |
d1b03f61 | 506 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
507 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
508 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | |
509 | .fixed_div = 2, | |
e9b98f60 | 510 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
511 | }; |
512 | ||
513 | /* | |
514 | * L3 clock domain | |
515 | * L3 clocks are used for both interface and functional clocks to | |
516 | * multiple entities. Some of these clocks are completely managed | |
517 | * by hardware, and some others allow software control. Hardware | |
518 | * managed ones general are based on directly CLK_REQ signals and | |
519 | * various auto idle settings. The functional spec sets many of these | |
520 | * as 'tie-high' for their enables. | |
521 | * | |
522 | * I-CLOCKS: | |
523 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | |
524 | * CAM, HS-USB. | |
525 | * F-CLOCK | |
526 | * SSI. | |
527 | * | |
528 | * GPMC memories and SDRC have timing and clock sensitive registers which | |
529 | * may very well need notification when the clock changes. Currently for low | |
530 | * operating points, these are taken care of in sleep.S. | |
531 | */ | |
e32744b0 PW |
532 | static const struct clksel_rate core_l3_core_rates[] = { |
533 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
534 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
d74b4949 | 535 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
e32744b0 PW |
536 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
537 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
538 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
539 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | |
540 | { .div = 0 } | |
541 | }; | |
542 | ||
543 | static const struct clksel core_l3_clksel[] = { | |
544 | { .parent = &core_ck, .rates = core_l3_core_rates }, | |
545 | { .parent = NULL } | |
546 | }; | |
547 | ||
046d6b28 TL |
548 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
549 | .name = "core_l3_ck", | |
897dcded | 550 | .ops = &clkops_null, |
046d6b28 | 551 | .parent = &core_ck, |
d1b03f61 | 552 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
553 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
554 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | |
555 | .clksel = core_l3_clksel, | |
046d6b28 | 556 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
557 | }; |
558 | ||
559 | /* usb_l4_ick */ | |
560 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
561 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 562 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
563 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
564 | { .div = 0 } | |
565 | }; | |
566 | ||
567 | static const struct clksel usb_l4_ick_clksel[] = { | |
568 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
569 | { .parent = NULL }, | |
046d6b28 TL |
570 | }; |
571 | ||
d1b03f61 | 572 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
046d6b28 TL |
573 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
574 | .name = "usb_l4_ick", | |
b36ee724 | 575 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 576 | .parent = &core_l3_ck, |
d1b03f61 | 577 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
578 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
579 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
580 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
581 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | |
582 | .clksel = usb_l4_ick_clksel, | |
046d6b28 TL |
583 | .recalc = &omap2_clksel_recalc, |
584 | }; | |
585 | ||
d1b03f61 PW |
586 | /* |
587 | * L4 clock management domain | |
588 | * | |
589 | * This domain contains lots of interface clocks from the L4 interface, some | |
590 | * functional clocks. Fixed APLL functional source clocks are managed in | |
591 | * this domain. | |
592 | */ | |
593 | static const struct clksel_rate l4_core_l3_rates[] = { | |
d74b4949 | 594 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
d1b03f61 PW |
595 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
596 | { .div = 0 } | |
597 | }; | |
598 | ||
599 | static const struct clksel l4_clksel[] = { | |
600 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | |
601 | { .parent = NULL } | |
602 | }; | |
603 | ||
604 | static struct clk l4_ck = { /* used both as an ick and fck */ | |
605 | .name = "l4_ck", | |
897dcded | 606 | .ops = &clkops_null, |
d1b03f61 | 607 | .parent = &core_l3_ck, |
d1b03f61 PW |
608 | .clkdm_name = "core_l4_clkdm", |
609 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
610 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | |
611 | .clksel = l4_clksel, | |
612 | .recalc = &omap2_clksel_recalc, | |
d1b03f61 PW |
613 | }; |
614 | ||
046d6b28 TL |
615 | /* |
616 | * SSI is in L3 management domain, its direct parent is core not l3, | |
617 | * many core power domain entities are grouped into the L3 clock | |
618 | * domain. | |
d1b03f61 | 619 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
046d6b28 TL |
620 | * |
621 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | |
622 | */ | |
e32744b0 PW |
623 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
624 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 625 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
626 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
627 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
e32744b0 PW |
628 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
629 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
630 | { .div = 0 } | |
631 | }; | |
632 | ||
633 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
634 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
635 | { .parent = NULL } | |
636 | }; | |
637 | ||
046d6b28 TL |
638 | static struct clk ssi_ssr_sst_fck = { |
639 | .name = "ssi_fck", | |
b36ee724 | 640 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 641 | .parent = &core_ck, |
d1b03f61 | 642 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
644 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
645 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
646 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | |
647 | .clksel = ssi_ssr_sst_fck_clksel, | |
046d6b28 TL |
648 | .recalc = &omap2_clksel_recalc, |
649 | }; | |
650 | ||
9299fd85 PW |
651 | /* |
652 | * Presumably this is the same as SSI_ICLK. | |
653 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | |
654 | */ | |
655 | static struct clk ssi_l4_ick = { | |
656 | .name = "ssi_l4_ick", | |
657 | .ops = &clkops_omap2_dflt_wait, | |
658 | .parent = &l4_ck, | |
659 | .clkdm_name = "core_l4_clkdm", | |
660 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
661 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
662 | .recalc = &followparent_recalc, | |
663 | }; | |
664 | ||
d1b03f61 | 665 | |
046d6b28 TL |
666 | /* |
667 | * GFX clock domain | |
668 | * Clocks: | |
669 | * GFX_FCLK, GFX_ICLK | |
670 | * GFX_CG1(2d), GFX_CG2(3d) | |
671 | * | |
672 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | |
673 | * The 2d and 3d clocks run at a hardware determined | |
674 | * divided value of fclk. | |
675 | * | |
676 | */ | |
e32744b0 PW |
677 | |
678 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | |
679 | static const struct clksel gfx_fck_clksel[] = { | |
680 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
681 | { .parent = NULL }, | |
682 | }; | |
683 | ||
046d6b28 TL |
684 | static struct clk gfx_3d_fck = { |
685 | .name = "gfx_3d_fck", | |
b36ee724 | 686 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 687 | .parent = &core_l3_ck, |
d1b03f61 | 688 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
689 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
690 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | |
691 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
692 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
693 | .clksel = gfx_fck_clksel, | |
046d6b28 | 694 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
695 | .round_rate = &omap2_clksel_round_rate, |
696 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
697 | }; |
698 | ||
699 | static struct clk gfx_2d_fck = { | |
700 | .name = "gfx_2d_fck", | |
b36ee724 | 701 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 702 | .parent = &core_l3_ck, |
d1b03f61 | 703 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
704 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
705 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | |
706 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
707 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
708 | .clksel = gfx_fck_clksel, | |
046d6b28 TL |
709 | .recalc = &omap2_clksel_recalc, |
710 | }; | |
711 | ||
712 | static struct clk gfx_ick = { | |
713 | .name = "gfx_ick", /* From l3 */ | |
b36ee724 | 714 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 715 | .parent = &core_l3_ck, |
d1b03f61 | 716 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
717 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
718 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
719 | .recalc = &followparent_recalc, | |
046d6b28 TL |
720 | }; |
721 | ||
046d6b28 TL |
722 | /* |
723 | * DSS clock domain | |
724 | * CLOCKs: | |
725 | * DSS_L4_ICLK, DSS_L3_ICLK, | |
726 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | |
727 | * | |
728 | * DSS is both initiator and target. | |
729 | */ | |
e32744b0 PW |
730 | /* XXX Add RATE_NOT_VALIDATED */ |
731 | ||
732 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
d74b4949 | 733 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
734 | { .div = 0 } |
735 | }; | |
736 | ||
737 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
738 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
739 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
740 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
741 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
742 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
743 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
744 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
745 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
746 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
d74b4949 | 747 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, |
e32744b0 PW |
748 | { .div = 0 } |
749 | }; | |
750 | ||
751 | static const struct clksel dss1_fck_clksel[] = { | |
752 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
753 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
754 | { .parent = NULL }, | |
755 | }; | |
756 | ||
046d6b28 TL |
757 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
758 | .name = "dss_ick", | |
bc51da4e | 759 | .ops = &clkops_omap2_dflt, |
046d6b28 | 760 | .parent = &l4_ck, /* really both l3 and l4 */ |
d1b03f61 | 761 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
762 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
763 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
764 | .recalc = &followparent_recalc, | |
046d6b28 TL |
765 | }; |
766 | ||
767 | static struct clk dss1_fck = { | |
768 | .name = "dss1_fck", | |
bc51da4e | 769 | .ops = &clkops_omap2_dflt, |
046d6b28 | 770 | .parent = &core_ck, /* Core or sys */ |
d1b03f61 | 771 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
773 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
774 | .init = &omap2_init_clksel_parent, | |
775 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
776 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | |
777 | .clksel = dss1_fck_clksel, | |
046d6b28 | 778 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
779 | }; |
780 | ||
781 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
d74b4949 | 782 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
783 | { .div = 0 } |
784 | }; | |
785 | ||
786 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
d74b4949 | 787 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
788 | { .div = 0 } |
789 | }; | |
790 | ||
791 | static const struct clksel dss2_fck_clksel[] = { | |
792 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
793 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
794 | { .parent = NULL } | |
046d6b28 TL |
795 | }; |
796 | ||
797 | static struct clk dss2_fck = { /* Alt clk used in power management */ | |
798 | .name = "dss2_fck", | |
bc51da4e | 799 | .ops = &clkops_omap2_dflt, |
046d6b28 | 800 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
d1b03f61 | 801 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
802 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
803 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | |
804 | .init = &omap2_init_clksel_parent, | |
805 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
806 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | |
807 | .clksel = dss2_fck_clksel, | |
808 | .recalc = &followparent_recalc, | |
046d6b28 TL |
809 | }; |
810 | ||
811 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |
812 | .name = "dss_54m_fck", /* 54m tv clk */ | |
b36ee724 | 813 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 814 | .parent = &func_54m_ck, |
d1b03f61 | 815 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
817 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
818 | .recalc = &followparent_recalc, | |
046d6b28 TL |
819 | }; |
820 | ||
821 | /* | |
822 | * CORE power domain ICLK & FCLK defines. | |
823 | * Many of the these can have more than one possible parent. Entries | |
824 | * here will likely have an L4 interface parent, and may have multiple | |
825 | * functional clock parents. | |
826 | */ | |
e32744b0 | 827 | static const struct clksel_rate gpt_alt_rates[] = { |
d74b4949 | 828 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
829 | { .div = 0 } |
830 | }; | |
831 | ||
832 | static const struct clksel omap24xx_gpt_clksel[] = { | |
833 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
834 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
835 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
836 | { .parent = NULL }, | |
837 | }; | |
838 | ||
046d6b28 TL |
839 | static struct clk gpt1_ick = { |
840 | .name = "gpt1_ick", | |
b36ee724 | 841 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 842 | .parent = &l4_ck, |
d1b03f61 | 843 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
844 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
845 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
846 | .recalc = &followparent_recalc, | |
046d6b28 TL |
847 | }; |
848 | ||
849 | static struct clk gpt1_fck = { | |
850 | .name = "gpt1_fck", | |
b36ee724 | 851 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 852 | .parent = &func_32k_ck, |
d1b03f61 | 853 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
854 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
855 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
856 | .init = &omap2_init_clksel_parent, | |
857 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
858 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | |
859 | .clksel = omap24xx_gpt_clksel, | |
860 | .recalc = &omap2_clksel_recalc, | |
861 | .round_rate = &omap2_clksel_round_rate, | |
862 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
863 | }; |
864 | ||
865 | static struct clk gpt2_ick = { | |
866 | .name = "gpt2_ick", | |
b36ee724 | 867 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 868 | .parent = &l4_ck, |
d1b03f61 | 869 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
871 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
872 | .recalc = &followparent_recalc, | |
046d6b28 TL |
873 | }; |
874 | ||
875 | static struct clk gpt2_fck = { | |
876 | .name = "gpt2_fck", | |
b36ee724 | 877 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 878 | .parent = &func_32k_ck, |
d1b03f61 | 879 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
881 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
882 | .init = &omap2_init_clksel_parent, | |
883 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
884 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | |
885 | .clksel = omap24xx_gpt_clksel, | |
886 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
887 | }; |
888 | ||
889 | static struct clk gpt3_ick = { | |
890 | .name = "gpt3_ick", | |
b36ee724 | 891 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 892 | .parent = &l4_ck, |
d1b03f61 | 893 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
895 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
896 | .recalc = &followparent_recalc, | |
046d6b28 TL |
897 | }; |
898 | ||
899 | static struct clk gpt3_fck = { | |
900 | .name = "gpt3_fck", | |
b36ee724 | 901 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 902 | .parent = &func_32k_ck, |
d1b03f61 | 903 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
905 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
906 | .init = &omap2_init_clksel_parent, | |
907 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
908 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | |
909 | .clksel = omap24xx_gpt_clksel, | |
910 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
911 | }; |
912 | ||
913 | static struct clk gpt4_ick = { | |
914 | .name = "gpt4_ick", | |
b36ee724 | 915 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 916 | .parent = &l4_ck, |
d1b03f61 | 917 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
919 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
920 | .recalc = &followparent_recalc, | |
046d6b28 TL |
921 | }; |
922 | ||
923 | static struct clk gpt4_fck = { | |
924 | .name = "gpt4_fck", | |
b36ee724 | 925 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 926 | .parent = &func_32k_ck, |
d1b03f61 | 927 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
928 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
929 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
930 | .init = &omap2_init_clksel_parent, | |
931 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
932 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | |
933 | .clksel = omap24xx_gpt_clksel, | |
934 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
935 | }; |
936 | ||
937 | static struct clk gpt5_ick = { | |
938 | .name = "gpt5_ick", | |
b36ee724 | 939 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 940 | .parent = &l4_ck, |
d1b03f61 | 941 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
943 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
944 | .recalc = &followparent_recalc, | |
046d6b28 TL |
945 | }; |
946 | ||
947 | static struct clk gpt5_fck = { | |
948 | .name = "gpt5_fck", | |
b36ee724 | 949 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 950 | .parent = &func_32k_ck, |
d1b03f61 | 951 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
953 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
954 | .init = &omap2_init_clksel_parent, | |
955 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
956 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | |
957 | .clksel = omap24xx_gpt_clksel, | |
958 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
959 | }; |
960 | ||
961 | static struct clk gpt6_ick = { | |
962 | .name = "gpt6_ick", | |
b36ee724 | 963 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 964 | .parent = &l4_ck, |
d1b03f61 | 965 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
966 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
967 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
968 | .recalc = &followparent_recalc, | |
046d6b28 TL |
969 | }; |
970 | ||
971 | static struct clk gpt6_fck = { | |
972 | .name = "gpt6_fck", | |
b36ee724 | 973 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 974 | .parent = &func_32k_ck, |
d1b03f61 | 975 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
977 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
978 | .init = &omap2_init_clksel_parent, | |
979 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
980 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | |
981 | .clksel = omap24xx_gpt_clksel, | |
982 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
983 | }; |
984 | ||
985 | static struct clk gpt7_ick = { | |
986 | .name = "gpt7_ick", | |
b36ee724 | 987 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 988 | .parent = &l4_ck, |
e32744b0 PW |
989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
990 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
991 | .recalc = &followparent_recalc, | |
046d6b28 TL |
992 | }; |
993 | ||
994 | static struct clk gpt7_fck = { | |
995 | .name = "gpt7_fck", | |
b36ee724 | 996 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 997 | .parent = &func_32k_ck, |
d1b03f61 | 998 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1000 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
1001 | .init = &omap2_init_clksel_parent, | |
1002 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1003 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | |
1004 | .clksel = omap24xx_gpt_clksel, | |
1005 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1006 | }; |
1007 | ||
1008 | static struct clk gpt8_ick = { | |
1009 | .name = "gpt8_ick", | |
b36ee724 | 1010 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1011 | .parent = &l4_ck, |
d1b03f61 | 1012 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1013 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1014 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1015 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1016 | }; |
1017 | ||
1018 | static struct clk gpt8_fck = { | |
1019 | .name = "gpt8_fck", | |
b36ee724 | 1020 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1021 | .parent = &func_32k_ck, |
d1b03f61 | 1022 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1023 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1024 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1025 | .init = &omap2_init_clksel_parent, | |
1026 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1027 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | |
1028 | .clksel = omap24xx_gpt_clksel, | |
1029 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1030 | }; |
1031 | ||
1032 | static struct clk gpt9_ick = { | |
1033 | .name = "gpt9_ick", | |
b36ee724 | 1034 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1035 | .parent = &l4_ck, |
d1b03f61 | 1036 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1038 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1039 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1040 | }; |
1041 | ||
1042 | static struct clk gpt9_fck = { | |
1043 | .name = "gpt9_fck", | |
b36ee724 | 1044 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1045 | .parent = &func_32k_ck, |
d1b03f61 | 1046 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1048 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1049 | .init = &omap2_init_clksel_parent, | |
1050 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1051 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | |
1052 | .clksel = omap24xx_gpt_clksel, | |
1053 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1054 | }; |
1055 | ||
1056 | static struct clk gpt10_ick = { | |
1057 | .name = "gpt10_ick", | |
b36ee724 | 1058 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1059 | .parent = &l4_ck, |
d1b03f61 | 1060 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1061 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1062 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1063 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1064 | }; |
1065 | ||
1066 | static struct clk gpt10_fck = { | |
1067 | .name = "gpt10_fck", | |
b36ee724 | 1068 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1069 | .parent = &func_32k_ck, |
d1b03f61 | 1070 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1072 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1073 | .init = &omap2_init_clksel_parent, | |
1074 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1075 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | |
1076 | .clksel = omap24xx_gpt_clksel, | |
1077 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1078 | }; |
1079 | ||
1080 | static struct clk gpt11_ick = { | |
1081 | .name = "gpt11_ick", | |
b36ee724 | 1082 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1083 | .parent = &l4_ck, |
d1b03f61 | 1084 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1085 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1086 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1087 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1088 | }; |
1089 | ||
1090 | static struct clk gpt11_fck = { | |
1091 | .name = "gpt11_fck", | |
b36ee724 | 1092 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1093 | .parent = &func_32k_ck, |
d1b03f61 | 1094 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1095 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1096 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1097 | .init = &omap2_init_clksel_parent, | |
1098 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1099 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | |
1100 | .clksel = omap24xx_gpt_clksel, | |
1101 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1102 | }; |
1103 | ||
1104 | static struct clk gpt12_ick = { | |
1105 | .name = "gpt12_ick", | |
b36ee724 | 1106 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1107 | .parent = &l4_ck, |
d1b03f61 | 1108 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1109 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1110 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1111 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1112 | }; |
1113 | ||
1114 | static struct clk gpt12_fck = { | |
1115 | .name = "gpt12_fck", | |
b36ee724 | 1116 | .ops = &clkops_omap2_dflt_wait, |
f248076c | 1117 | .parent = &secure_32k_ck, |
d1b03f61 | 1118 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1119 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1120 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1121 | .init = &omap2_init_clksel_parent, | |
1122 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1123 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | |
1124 | .clksel = omap24xx_gpt_clksel, | |
1125 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1126 | }; |
1127 | ||
1128 | static struct clk mcbsp1_ick = { | |
b92c170d | 1129 | .name = "mcbsp1_ick", |
b36ee724 | 1130 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1131 | .parent = &l4_ck, |
d1b03f61 | 1132 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1134 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1135 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1136 | }; |
1137 | ||
1138 | static struct clk mcbsp1_fck = { | |
b92c170d | 1139 | .name = "mcbsp1_fck", |
b36ee724 | 1140 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1141 | .parent = &func_96m_ck, |
d1b03f61 | 1142 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1143 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1144 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1145 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1146 | }; |
1147 | ||
1148 | static struct clk mcbsp2_ick = { | |
b92c170d | 1149 | .name = "mcbsp2_ick", |
b36ee724 | 1150 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1151 | .parent = &l4_ck, |
d1b03f61 | 1152 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1154 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1155 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1156 | }; |
1157 | ||
1158 | static struct clk mcbsp2_fck = { | |
b92c170d | 1159 | .name = "mcbsp2_fck", |
b36ee724 | 1160 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1161 | .parent = &func_96m_ck, |
d1b03f61 | 1162 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1164 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1165 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1166 | }; |
1167 | ||
046d6b28 | 1168 | static struct clk mcspi1_ick = { |
b92c170d | 1169 | .name = "mcspi1_ick", |
b36ee724 | 1170 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1171 | .parent = &l4_ck, |
d1b03f61 | 1172 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1173 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1174 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1175 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1176 | }; |
1177 | ||
1178 | static struct clk mcspi1_fck = { | |
b92c170d | 1179 | .name = "mcspi1_fck", |
b36ee724 | 1180 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1181 | .parent = &func_48m_ck, |
d1b03f61 | 1182 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1184 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1185 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1186 | }; |
1187 | ||
1188 | static struct clk mcspi2_ick = { | |
b92c170d | 1189 | .name = "mcspi2_ick", |
b36ee724 | 1190 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1191 | .parent = &l4_ck, |
d1b03f61 | 1192 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1193 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1194 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1195 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1196 | }; |
1197 | ||
1198 | static struct clk mcspi2_fck = { | |
b92c170d | 1199 | .name = "mcspi2_fck", |
b36ee724 | 1200 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1201 | .parent = &func_48m_ck, |
d1b03f61 | 1202 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1204 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1205 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1206 | }; |
1207 | ||
046d6b28 TL |
1208 | static struct clk uart1_ick = { |
1209 | .name = "uart1_ick", | |
b36ee724 | 1210 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1211 | .parent = &l4_ck, |
d1b03f61 | 1212 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1213 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1214 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1215 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1216 | }; |
1217 | ||
1218 | static struct clk uart1_fck = { | |
1219 | .name = "uart1_fck", | |
b36ee724 | 1220 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1221 | .parent = &func_48m_ck, |
d1b03f61 | 1222 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1223 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1224 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1225 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1226 | }; |
1227 | ||
1228 | static struct clk uart2_ick = { | |
1229 | .name = "uart2_ick", | |
b36ee724 | 1230 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1231 | .parent = &l4_ck, |
d1b03f61 | 1232 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1233 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1234 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1235 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1236 | }; |
1237 | ||
1238 | static struct clk uart2_fck = { | |
1239 | .name = "uart2_fck", | |
b36ee724 | 1240 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1241 | .parent = &func_48m_ck, |
d1b03f61 | 1242 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1244 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1245 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1246 | }; |
1247 | ||
1248 | static struct clk uart3_ick = { | |
1249 | .name = "uart3_ick", | |
b36ee724 | 1250 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1251 | .parent = &l4_ck, |
d1b03f61 | 1252 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1254 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1255 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1256 | }; |
1257 | ||
1258 | static struct clk uart3_fck = { | |
1259 | .name = "uart3_fck", | |
b36ee724 | 1260 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1261 | .parent = &func_48m_ck, |
d1b03f61 | 1262 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1264 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1265 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1266 | }; |
1267 | ||
1268 | static struct clk gpios_ick = { | |
1269 | .name = "gpios_ick", | |
b36ee724 | 1270 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1271 | .parent = &l4_ck, |
d1b03f61 | 1272 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1273 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1274 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1275 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1276 | }; |
1277 | ||
1278 | static struct clk gpios_fck = { | |
1279 | .name = "gpios_fck", | |
b36ee724 | 1280 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1281 | .parent = &func_32k_ck, |
d1b03f61 | 1282 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1283 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1284 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1285 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1286 | }; |
1287 | ||
1288 | static struct clk mpu_wdt_ick = { | |
1289 | .name = "mpu_wdt_ick", | |
b36ee724 | 1290 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1291 | .parent = &l4_ck, |
d1b03f61 | 1292 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1293 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1294 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1295 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1296 | }; |
1297 | ||
1298 | static struct clk mpu_wdt_fck = { | |
1299 | .name = "mpu_wdt_fck", | |
b36ee724 | 1300 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1301 | .parent = &func_32k_ck, |
d1b03f61 | 1302 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1303 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1304 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1305 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1306 | }; |
1307 | ||
1308 | static struct clk sync_32k_ick = { | |
1309 | .name = "sync_32k_ick", | |
b36ee724 | 1310 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1311 | .parent = &l4_ck, |
8ad8ff65 | 1312 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1313 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1315 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1316 | .recalc = &followparent_recalc, | |
046d6b28 | 1317 | }; |
d1b03f61 | 1318 | |
046d6b28 TL |
1319 | static struct clk wdt1_ick = { |
1320 | .name = "wdt1_ick", | |
b36ee724 | 1321 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1322 | .parent = &l4_ck, |
d1b03f61 | 1323 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1325 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1326 | .recalc = &followparent_recalc, | |
046d6b28 | 1327 | }; |
d1b03f61 | 1328 | |
046d6b28 TL |
1329 | static struct clk omapctrl_ick = { |
1330 | .name = "omapctrl_ick", | |
b36ee724 | 1331 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1332 | .parent = &l4_ck, |
8ad8ff65 | 1333 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1334 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1335 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1336 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1337 | .recalc = &followparent_recalc, | |
046d6b28 | 1338 | }; |
d1b03f61 | 1339 | |
046d6b28 TL |
1340 | static struct clk cam_ick = { |
1341 | .name = "cam_ick", | |
bc51da4e | 1342 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1343 | .parent = &l4_ck, |
d1b03f61 | 1344 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1345 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1346 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1347 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1348 | }; |
1349 | ||
d1b03f61 PW |
1350 | /* |
1351 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | |
1352 | * split into two separate clocks, since the parent clocks are different | |
1353 | * and the clockdomains are also different. | |
1354 | */ | |
046d6b28 TL |
1355 | static struct clk cam_fck = { |
1356 | .name = "cam_fck", | |
bc51da4e | 1357 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1358 | .parent = &func_96m_ck, |
d1b03f61 | 1359 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1361 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1362 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1363 | }; |
1364 | ||
1365 | static struct clk mailboxes_ick = { | |
1366 | .name = "mailboxes_ick", | |
b36ee724 | 1367 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1368 | .parent = &l4_ck, |
d1b03f61 | 1369 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1371 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1372 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1373 | }; |
1374 | ||
1375 | static struct clk wdt4_ick = { | |
1376 | .name = "wdt4_ick", | |
b36ee724 | 1377 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1378 | .parent = &l4_ck, |
d1b03f61 | 1379 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1381 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1382 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1383 | }; |
1384 | ||
1385 | static struct clk wdt4_fck = { | |
1386 | .name = "wdt4_fck", | |
b36ee724 | 1387 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1388 | .parent = &func_32k_ck, |
d1b03f61 | 1389 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1391 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1392 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1393 | }; |
1394 | ||
1395 | static struct clk wdt3_ick = { | |
1396 | .name = "wdt3_ick", | |
b36ee724 | 1397 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1398 | .parent = &l4_ck, |
d1b03f61 | 1399 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1401 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1402 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1403 | }; |
1404 | ||
1405 | static struct clk wdt3_fck = { | |
1406 | .name = "wdt3_fck", | |
b36ee724 | 1407 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1408 | .parent = &func_32k_ck, |
d1b03f61 | 1409 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1411 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1412 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1413 | }; |
1414 | ||
1415 | static struct clk mspro_ick = { | |
1416 | .name = "mspro_ick", | |
b36ee724 | 1417 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1418 | .parent = &l4_ck, |
d1b03f61 | 1419 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1421 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1422 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1423 | }; |
1424 | ||
1425 | static struct clk mspro_fck = { | |
1426 | .name = "mspro_fck", | |
b36ee724 | 1427 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1428 | .parent = &func_96m_ck, |
d1b03f61 | 1429 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1431 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1432 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1433 | }; |
1434 | ||
1435 | static struct clk mmc_ick = { | |
1436 | .name = "mmc_ick", | |
b36ee724 | 1437 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1438 | .parent = &l4_ck, |
d1b03f61 | 1439 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1441 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1442 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1443 | }; |
1444 | ||
1445 | static struct clk mmc_fck = { | |
1446 | .name = "mmc_fck", | |
b36ee724 | 1447 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1448 | .parent = &func_96m_ck, |
d1b03f61 | 1449 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1451 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1452 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1453 | }; |
1454 | ||
1455 | static struct clk fac_ick = { | |
1456 | .name = "fac_ick", | |
b36ee724 | 1457 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1458 | .parent = &l4_ck, |
d1b03f61 | 1459 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1461 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1462 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1463 | }; |
1464 | ||
1465 | static struct clk fac_fck = { | |
1466 | .name = "fac_fck", | |
b36ee724 | 1467 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1468 | .parent = &func_12m_ck, |
d1b03f61 | 1469 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1471 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1472 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1473 | }; |
1474 | ||
1475 | static struct clk eac_ick = { | |
1476 | .name = "eac_ick", | |
b36ee724 | 1477 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1478 | .parent = &l4_ck, |
d1b03f61 | 1479 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1481 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1482 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1483 | }; |
1484 | ||
1485 | static struct clk eac_fck = { | |
1486 | .name = "eac_fck", | |
b36ee724 | 1487 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1488 | .parent = &func_96m_ck, |
d1b03f61 | 1489 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1491 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1492 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1493 | }; |
1494 | ||
1495 | static struct clk hdq_ick = { | |
1496 | .name = "hdq_ick", | |
b36ee724 | 1497 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1498 | .parent = &l4_ck, |
d1b03f61 | 1499 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1501 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1502 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1503 | }; |
1504 | ||
1505 | static struct clk hdq_fck = { | |
1506 | .name = "hdq_fck", | |
b36ee724 | 1507 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1508 | .parent = &func_12m_ck, |
d1b03f61 | 1509 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1511 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1512 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1513 | }; |
1514 | ||
1515 | static struct clk i2c2_ick = { | |
b92c170d | 1516 | .name = "i2c2_ick", |
b36ee724 | 1517 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1518 | .parent = &l4_ck, |
d1b03f61 | 1519 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1521 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1522 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1523 | }; |
1524 | ||
1525 | static struct clk i2c2_fck = { | |
b92c170d | 1526 | .name = "i2c2_fck", |
b36ee724 | 1527 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1528 | .parent = &func_12m_ck, |
d1b03f61 | 1529 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1531 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1532 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1533 | }; |
1534 | ||
046d6b28 | 1535 | static struct clk i2c1_ick = { |
b92c170d | 1536 | .name = "i2c1_ick", |
b36ee724 | 1537 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1538 | .parent = &l4_ck, |
d1b03f61 | 1539 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1541 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1542 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1543 | }; |
1544 | ||
1545 | static struct clk i2c1_fck = { | |
b92c170d | 1546 | .name = "i2c1_fck", |
b36ee724 | 1547 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1548 | .parent = &func_12m_ck, |
d1b03f61 | 1549 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1551 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1552 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1553 | }; |
1554 | ||
e32744b0 PW |
1555 | static struct clk gpmc_fck = { |
1556 | .name = "gpmc_fck", | |
897dcded | 1557 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1558 | .parent = &core_l3_ck, |
8ad8ff65 | 1559 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1560 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1561 | .recalc = &followparent_recalc, |
1562 | }; | |
1563 | ||
1564 | static struct clk sdma_fck = { | |
1565 | .name = "sdma_fck", | |
897dcded | 1566 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1567 | .parent = &core_l3_ck, |
d1b03f61 | 1568 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1569 | .recalc = &followparent_recalc, |
1570 | }; | |
1571 | ||
1572 | static struct clk sdma_ick = { | |
1573 | .name = "sdma_ick", | |
897dcded | 1574 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1575 | .parent = &l4_ck, |
d1b03f61 | 1576 | .clkdm_name = "core_l3_clkdm", |
e32744b0 | 1577 | .recalc = &followparent_recalc, |
046d6b28 TL |
1578 | }; |
1579 | ||
1580 | static struct clk vlynq_ick = { | |
1581 | .name = "vlynq_ick", | |
b36ee724 | 1582 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1583 | .parent = &core_l3_ck, |
d1b03f61 | 1584 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1586 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1587 | .recalc = &followparent_recalc, | |
1588 | }; | |
1589 | ||
1590 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | |
d74b4949 | 1591 | { .div = 1, .val = 0, .flags = RATE_IN_242X }, |
e32744b0 PW |
1592 | { .div = 0 } |
1593 | }; | |
1594 | ||
1595 | static const struct clksel_rate vlynq_fck_core_rates[] = { | |
1596 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | |
1597 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
1598 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | |
1599 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
1600 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
1601 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
1602 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | |
1603 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
d74b4949 | 1604 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, |
e32744b0 PW |
1605 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, |
1606 | { .div = 0 } | |
1607 | }; | |
1608 | ||
1609 | static const struct clksel vlynq_fck_clksel[] = { | |
1610 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | |
1611 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | |
1612 | { .parent = NULL } | |
046d6b28 TL |
1613 | }; |
1614 | ||
1615 | static struct clk vlynq_fck = { | |
1616 | .name = "vlynq_fck", | |
b36ee724 | 1617 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1618 | .parent = &func_96m_ck, |
d1b03f61 | 1619 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1621 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1622 | .init = &omap2_init_clksel_parent, | |
1623 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
1624 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | |
1625 | .clksel = vlynq_fck_clksel, | |
1626 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1627 | }; |
1628 | ||
046d6b28 TL |
1629 | static struct clk des_ick = { |
1630 | .name = "des_ick", | |
b36ee724 | 1631 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1632 | .parent = &l4_ck, |
d1b03f61 | 1633 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1635 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
1636 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1637 | }; |
1638 | ||
1639 | static struct clk sha_ick = { | |
1640 | .name = "sha_ick", | |
b36ee724 | 1641 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1642 | .parent = &l4_ck, |
d1b03f61 | 1643 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1645 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1646 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1647 | }; |
1648 | ||
1649 | static struct clk rng_ick = { | |
1650 | .name = "rng_ick", | |
b36ee724 | 1651 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1652 | .parent = &l4_ck, |
d1b03f61 | 1653 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1655 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1656 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1657 | }; |
1658 | ||
1659 | static struct clk aes_ick = { | |
1660 | .name = "aes_ick", | |
b36ee724 | 1661 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1662 | .parent = &l4_ck, |
d1b03f61 | 1663 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1665 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
1666 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1667 | }; |
1668 | ||
1669 | static struct clk pka_ick = { | |
1670 | .name = "pka_ick", | |
b36ee724 | 1671 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1672 | .parent = &l4_ck, |
d1b03f61 | 1673 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1674 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1675 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1676 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1677 | }; |
1678 | ||
1679 | static struct clk usb_fck = { | |
1680 | .name = "usb_fck", | |
b36ee724 | 1681 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1682 | .parent = &func_48m_ck, |
d1b03f61 | 1683 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1684 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1685 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1686 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1687 | }; |
1688 | ||
046d6b28 TL |
1689 | /* |
1690 | * This clock is a composite clock which does entire set changes then | |
1691 | * forces a rebalance. It keys on the MPU speed, but it really could | |
1692 | * be any key speed part of a set in the rate table. | |
1693 | * | |
1694 | * to really change a set, you need memory table sets which get changed | |
1695 | * in sram, pre-notifiers & post notifiers, changing the top set, without | |
1696 | * having low level display recalc's won't work... this is why dpm notifiers | |
1697 | * work, isr's off, walk a list of clocks already _off_ and not messing with | |
1698 | * the bus. | |
1699 | * | |
1700 | * This clock should have no parent. It embodies the entire upper level | |
1701 | * active set. A parent will mess up some of the init also. | |
1702 | */ | |
1703 | static struct clk virt_prcm_set = { | |
1704 | .name = "virt_prcm_set", | |
897dcded | 1705 | .ops = &clkops_null, |
046d6b28 | 1706 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
e32744b0 | 1707 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
046d6b28 TL |
1708 | .set_rate = &omap2_select_table_rate, |
1709 | .round_rate = &omap2_round_to_table_rate, | |
1710 | }; | |
e32744b0 | 1711 | |
d8a94458 PW |
1712 | |
1713 | /* | |
1714 | * clkdev integration | |
1715 | */ | |
1716 | ||
81b34fbe | 1717 | static struct omap_clk omap2420_clks[] = { |
d8a94458 | 1718 | /* external root sources */ |
81b34fbe PW |
1719 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), |
1720 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), | |
1721 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | |
1722 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | |
1723 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | |
d8a94458 | 1724 | /* internal analog sources */ |
81b34fbe PW |
1725 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
1726 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), | |
1727 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), | |
d8a94458 | 1728 | /* internal prcm root sources */ |
81b34fbe PW |
1729 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
1730 | CLK(NULL, "core_ck", &core_ck, CK_242X), | |
1731 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | |
1732 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | |
1733 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | |
1734 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), | |
1735 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), | |
1736 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), | |
d8a94458 PW |
1737 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), |
1738 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | |
1739 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | |
1740 | /* mpu domain clocks */ | |
81b34fbe | 1741 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), |
d8a94458 | 1742 | /* dsp domain clocks */ |
81b34fbe PW |
1743 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), |
1744 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), | |
d8a94458 | 1745 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), |
d8a94458 PW |
1746 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), |
1747 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | |
1748 | /* GFX domain clocks */ | |
81b34fbe PW |
1749 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), |
1750 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), | |
1751 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), | |
d8a94458 | 1752 | /* DSS domain clocks */ |
81b34fbe PW |
1753 | CLK("omapdss", "ick", &dss_ick, CK_242X), |
1754 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), | |
1755 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), | |
1756 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), | |
d8a94458 | 1757 | /* L3 domain clocks */ |
81b34fbe PW |
1758 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), |
1759 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), | |
1760 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), | |
d8a94458 | 1761 | /* L4 domain clocks */ |
81b34fbe PW |
1762 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), |
1763 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), | |
d8a94458 | 1764 | /* virtual meta-group clock */ |
81b34fbe | 1765 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), |
d8a94458 | 1766 | /* general l4 interface ck, multi-parent functional clk */ |
81b34fbe PW |
1767 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), |
1768 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), | |
1769 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), | |
1770 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), | |
1771 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), | |
1772 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), | |
1773 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), | |
1774 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), | |
1775 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), | |
1776 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), | |
1777 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), | |
1778 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), | |
1779 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), | |
1780 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), | |
1781 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), | |
1782 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), | |
1783 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), | |
1784 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), | |
1785 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), | |
1786 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), | |
1787 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), | |
1788 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), | |
1789 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), | |
1790 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), | |
1791 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), | |
1792 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), | |
1793 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), | |
1794 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), | |
1795 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), | |
1796 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), | |
1797 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), | |
1798 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), | |
1799 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), | |
1800 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), | |
1801 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), | |
1802 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), | |
1803 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), | |
1804 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), | |
1805 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), | |
1806 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), | |
1807 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), | |
1808 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), | |
1809 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), | |
1810 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), | |
1811 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), | |
1812 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), | |
1813 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), | |
1814 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), | |
1815 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), | |
1816 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), | |
d8a94458 PW |
1817 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), |
1818 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | |
81b34fbe PW |
1819 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), |
1820 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), | |
d8a94458 PW |
1821 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
1822 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | |
81b34fbe PW |
1823 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), |
1824 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), | |
d8a94458 PW |
1825 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), |
1826 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | |
81b34fbe PW |
1827 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), |
1828 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), | |
1829 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), | |
d8a94458 | 1830 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), |
81b34fbe | 1831 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), |
d8a94458 | 1832 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), |
81b34fbe PW |
1833 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), |
1834 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | |
1835 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | |
d8a94458 PW |
1836 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), |
1837 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | |
81b34fbe | 1838 | CLK(NULL, "des_ick", &des_ick, CK_242X), |
ee5500c4 | 1839 | CLK("omap-sham", "ick", &sha_ick, CK_242X), |
81b34fbe PW |
1840 | CLK("omap_rng", "ick", &rng_ick, CK_242X), |
1841 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), | |
1842 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), | |
1843 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | |
97b9ad16 | 1844 | CLK("musb_hdrc", "fck", &osc_ck, CK_242X), |
d8a94458 PW |
1845 | }; |
1846 | ||
1847 | /* | |
1848 | * init code | |
1849 | */ | |
1850 | ||
81b34fbe | 1851 | int __init omap2420_clk_init(void) |
d8a94458 PW |
1852 | { |
1853 | const struct prcm_config *prcm; | |
1854 | struct omap_clk *c; | |
1855 | u32 clkrate; | |
81b34fbe PW |
1856 | |
1857 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | |
1858 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | |
1859 | cpu_mask = RATE_IN_242X; | |
1860 | rate_table = omap2420_rate_table; | |
d8a94458 PW |
1861 | |
1862 | clk_init(&omap2_clk_functions); | |
1863 | ||
81b34fbe PW |
1864 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
1865 | c++) | |
d8a94458 PW |
1866 | clk_preinit(c->lk.clk); |
1867 | ||
1868 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | |
1869 | propagate_rate(&osc_ck); | |
44da0a51 | 1870 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
d8a94458 PW |
1871 | propagate_rate(&sys_ck); |
1872 | ||
81b34fbe PW |
1873 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
1874 | c++) { | |
1875 | clkdev_add(&c->lk); | |
1876 | clk_register(c->lk.clk); | |
1877 | omap2_init_clk_clkdm(c->lk.clk); | |
1878 | } | |
d8a94458 PW |
1879 | |
1880 | /* Check the MPU rate set by bootloader */ | |
1881 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | |
1882 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
1883 | if (!(prcm->flags & cpu_mask)) | |
1884 | continue; | |
1885 | if (prcm->xtal_speed != sys_ck.rate) | |
1886 | continue; | |
1887 | if (prcm->dpll_speed <= clkrate) | |
1888 | break; | |
1889 | } | |
1890 | curr_prcm_set = prcm; | |
1891 | ||
1892 | recalculate_root_clocks(); | |
1893 | ||
81b34fbe PW |
1894 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
1895 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
1896 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
d8a94458 PW |
1897 | |
1898 | /* | |
1899 | * Only enable those clocks we will need, let the drivers | |
1900 | * enable other clocks as necessary | |
1901 | */ | |
1902 | clk_enable_init_clocks(); | |
1903 | ||
1904 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | |
1905 | vclk = clk_get(NULL, "virt_prcm_set"); | |
1906 | sclk = clk_get(NULL, "sys_ck"); | |
1907 | dclk = clk_get(NULL, "dpll_ck"); | |
1908 | ||
1909 | return 0; | |
1910 | } | |
6b8858a9 | 1911 |