Commit | Line | Data |
---|---|---|
046d6b28 | 1 | /* |
8c810e7e | 2 | * OMAP2420 clock data |
046d6b28 | 3 | * |
8c810e7e PW |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2011 Nokia Corporation | |
046d6b28 | 6 | * |
8c810e7e PW |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 TL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
d8a94458 | 16 | #include <linux/kernel.h> |
2c799cef | 17 | #include <linux/io.h> |
d8a94458 | 18 | #include <linux/clk.h> |
93340a22 | 19 | #include <linux/list.h> |
046d6b28 | 20 | |
d8a94458 | 21 | #include <plat/clkdev_omap.h> |
6b8858a9 | 22 | |
dbc04161 | 23 | #include "soc.h" |
ee0839c2 | 24 | #include "iomap.h" |
d8a94458 PW |
25 | #include "clock.h" |
26 | #include "clock2xxx.h" | |
27 | #include "opp2xxx.h" | |
59fb659b PW |
28 | #include "cm2xxx_3xxx.h" |
29 | #include "prm2xxx_3xxx.h" | |
6b8858a9 PW |
30 | #include "prm-regbits-24xx.h" |
31 | #include "cm-regbits-24xx.h" | |
32 | #include "sdrc.h" | |
4814ced5 | 33 | #include "control.h" |
6b8858a9 | 34 | |
81b34fbe PW |
35 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR |
36 | ||
37 | /* | |
38 | * 2420 clock tree. | |
046d6b28 | 39 | * |
8c810e7e PW |
40 | * NOTE:In many cases here we are assigning a 'default' parent. In |
41 | * many cases the parent is selectable. The set parent calls will | |
42 | * also switch sources. | |
046d6b28 TL |
43 | * |
44 | * Several sources are given initial rates which may be wrong, this will | |
45 | * be fixed up in the init func. | |
46 | * | |
47 | * Things are broadly separated below by clock domains. It is | |
8c810e7e | 48 | * noteworthy that most peripherals have dependencies on multiple clock |
046d6b28 TL |
49 | * domains. Many get their interface clocks from the L4 domain, but get |
50 | * functional clocks from fixed sources or other core domain derived | |
51 | * clocks. | |
81b34fbe | 52 | */ |
046d6b28 TL |
53 | |
54 | /* Base external input clocks */ | |
55 | static struct clk func_32k_ck = { | |
56 | .name = "func_32k_ck", | |
897dcded | 57 | .ops = &clkops_null, |
3f9cfd3a | 58 | .rate = 32768, |
d1b03f61 | 59 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 60 | }; |
e32744b0 | 61 | |
f248076c PW |
62 | static struct clk secure_32k_ck = { |
63 | .name = "secure_32k_ck", | |
64 | .ops = &clkops_null, | |
65 | .rate = 32768, | |
f248076c PW |
66 | .clkdm_name = "wkup_clkdm", |
67 | }; | |
68 | ||
046d6b28 TL |
69 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
70 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |
71 | .name = "osc_ck", | |
548d8495 | 72 | .ops = &clkops_oscck, |
d1b03f61 | 73 | .clkdm_name = "wkup_clkdm", |
e32744b0 | 74 | .recalc = &omap2_osc_clk_recalc, |
046d6b28 TL |
75 | }; |
76 | ||
d1b03f61 | 77 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
046d6b28 TL |
78 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
79 | .name = "sys_ck", /* ~ ref_clk also */ | |
897dcded | 80 | .ops = &clkops_null, |
046d6b28 | 81 | .parent = &osc_ck, |
d1b03f61 | 82 | .clkdm_name = "wkup_clkdm", |
44da0a51 | 83 | .recalc = &omap2xxx_sys_clk_recalc, |
046d6b28 | 84 | }; |
e32744b0 | 85 | |
046d6b28 TL |
86 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
87 | .name = "alt_ck", | |
897dcded | 88 | .ops = &clkops_null, |
046d6b28 | 89 | .rate = 54000000, |
d1b03f61 | 90 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 91 | }; |
e32744b0 | 92 | |
1bccb345 PW |
93 | /* Optional external clock input for McBSP CLKS */ |
94 | static struct clk mcbsp_clks = { | |
95 | .name = "mcbsp_clks", | |
96 | .ops = &clkops_null, | |
97 | }; | |
98 | ||
046d6b28 TL |
99 | /* |
100 | * Analog domain root source clocks | |
101 | */ | |
102 | ||
103 | /* dpll_ck, is broken out in to special cases through clksel */ | |
6b8858a9 PW |
104 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
105 | * deal with this | |
106 | */ | |
107 | ||
88b8ba90 | 108 | static struct dpll_data dpll_dd = { |
6b8858a9 PW |
109 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
110 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
111 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
c0bf3132 RK |
112 | .clk_bypass = &sys_ck, |
113 | .clk_ref = &sys_ck, | |
114 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
115 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
93340a22 | 116 | .max_multiplier = 1023, |
95f538ac | 117 | .min_divider = 1, |
88b8ba90 | 118 | .max_divider = 16, |
6b8858a9 PW |
119 | }; |
120 | ||
88b8ba90 PW |
121 | /* |
122 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | |
123 | * not just a DPLL | |
124 | */ | |
046d6b28 TL |
125 | static struct clk dpll_ck = { |
126 | .name = "dpll_ck", | |
0fd0c21b | 127 | .ops = &clkops_omap2xxx_dpll_ops, |
046d6b28 | 128 | .parent = &sys_ck, /* Can be func_32k also */ |
6b8858a9 | 129 | .dpll_data = &dpll_dd, |
d1b03f61 | 130 | .clkdm_name = "wkup_clkdm", |
88b8ba90 PW |
131 | .recalc = &omap2_dpllcore_recalc, |
132 | .set_rate = &omap2_reprogram_dpllcore, | |
046d6b28 TL |
133 | }; |
134 | ||
135 | static struct clk apll96_ck = { | |
136 | .name = "apll96_ck", | |
06b16939 | 137 | .ops = &clkops_apll96, |
046d6b28 TL |
138 | .parent = &sys_ck, |
139 | .rate = 96000000, | |
51c19541 | 140 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 141 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
142 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
143 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
046d6b28 TL |
144 | }; |
145 | ||
146 | static struct clk apll54_ck = { | |
147 | .name = "apll54_ck", | |
06b16939 | 148 | .ops = &clkops_apll54, |
046d6b28 TL |
149 | .parent = &sys_ck, |
150 | .rate = 54000000, | |
51c19541 | 151 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 152 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
153 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
154 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
046d6b28 TL |
155 | }; |
156 | ||
157 | /* | |
158 | * PRCM digital base sources | |
159 | */ | |
e32744b0 PW |
160 | |
161 | /* func_54m_ck */ | |
162 | ||
163 | static const struct clksel_rate func_54m_apll54_rates[] = { | |
d74b4949 | 164 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
165 | { .div = 0 }, |
166 | }; | |
167 | ||
168 | static const struct clksel_rate func_54m_alt_rates[] = { | |
d74b4949 | 169 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
170 | { .div = 0 }, |
171 | }; | |
172 | ||
173 | static const struct clksel func_54m_clksel[] = { | |
174 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | |
175 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | |
176 | { .parent = NULL }, | |
177 | }; | |
178 | ||
046d6b28 TL |
179 | static struct clk func_54m_ck = { |
180 | .name = "func_54m_ck", | |
57137181 | 181 | .ops = &clkops_null, |
046d6b28 | 182 | .parent = &apll54_ck, /* can also be alt_clk */ |
d1b03f61 | 183 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
184 | .init = &omap2_init_clksel_parent, |
185 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 186 | .clksel_mask = OMAP24XX_54M_SOURCE_MASK, |
e32744b0 PW |
187 | .clksel = func_54m_clksel, |
188 | .recalc = &omap2_clksel_recalc, | |
046d6b28 | 189 | }; |
e32744b0 | 190 | |
046d6b28 TL |
191 | static struct clk core_ck = { |
192 | .name = "core_ck", | |
897dcded | 193 | .ops = &clkops_null, |
046d6b28 | 194 | .parent = &dpll_ck, /* can also be 32k */ |
d1b03f61 | 195 | .clkdm_name = "wkup_clkdm", |
6b8858a9 | 196 | .recalc = &followparent_recalc, |
046d6b28 | 197 | }; |
e32744b0 | 198 | |
046d6b28 TL |
199 | static struct clk func_96m_ck = { |
200 | .name = "func_96m_ck", | |
57137181 | 201 | .ops = &clkops_null, |
046d6b28 | 202 | .parent = &apll96_ck, |
d1b03f61 | 203 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 204 | .recalc = &followparent_recalc, |
e32744b0 PW |
205 | }; |
206 | ||
207 | /* func_48m_ck */ | |
208 | ||
209 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
d74b4949 | 210 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
211 | { .div = 0 }, |
212 | }; | |
213 | ||
214 | static const struct clksel_rate func_48m_alt_rates[] = { | |
d74b4949 | 215 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
216 | { .div = 0 }, |
217 | }; | |
218 | ||
219 | static const struct clksel func_48m_clksel[] = { | |
220 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
221 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
222 | { .parent = NULL } | |
046d6b28 TL |
223 | }; |
224 | ||
225 | static struct clk func_48m_ck = { | |
226 | .name = "func_48m_ck", | |
57137181 | 227 | .ops = &clkops_null, |
046d6b28 | 228 | .parent = &apll96_ck, /* 96M or Alt */ |
d1b03f61 | 229 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
230 | .init = &omap2_init_clksel_parent, |
231 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 232 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, |
e32744b0 PW |
233 | .clksel = func_48m_clksel, |
234 | .recalc = &omap2_clksel_recalc, | |
235 | .round_rate = &omap2_clksel_round_rate, | |
236 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
237 | }; |
238 | ||
239 | static struct clk func_12m_ck = { | |
240 | .name = "func_12m_ck", | |
57137181 | 241 | .ops = &clkops_null, |
046d6b28 | 242 | .parent = &func_48m_ck, |
e32744b0 | 243 | .fixed_div = 4, |
d1b03f61 | 244 | .clkdm_name = "wkup_clkdm", |
e9b98f60 | 245 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
246 | }; |
247 | ||
248 | /* Secure timer, only available in secure mode */ | |
249 | static struct clk wdt1_osc_ck = { | |
250 | .name = "ck_wdt1_osc", | |
897dcded | 251 | .ops = &clkops_null, /* RMK: missing? */ |
046d6b28 | 252 | .parent = &osc_ck, |
e32744b0 PW |
253 | .recalc = &followparent_recalc, |
254 | }; | |
255 | ||
256 | /* | |
257 | * The common_clkout* clksel_rate structs are common to | |
258 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | |
259 | * sys_clkout2_* are 2420-only, so the | |
260 | * clksel_rate flags fields are inaccurate for those clocks. This is | |
261 | * harmless since access to those clocks are gated by the struct clk | |
262 | * flags fields, which mark them as 2420-only. | |
263 | */ | |
264 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
d74b4949 | 265 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
266 | { .div = 0 } |
267 | }; | |
268 | ||
269 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
d74b4949 | 270 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
271 | { .div = 0 } |
272 | }; | |
273 | ||
274 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
d74b4949 | 275 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
276 | { .div = 0 } |
277 | }; | |
278 | ||
279 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
d74b4949 | 280 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, |
e32744b0 PW |
281 | { .div = 0 } |
282 | }; | |
283 | ||
284 | static const struct clksel common_clkout_src_clksel[] = { | |
285 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
286 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
287 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
288 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
289 | { .parent = NULL } | |
290 | }; | |
291 | ||
292 | static struct clk sys_clkout_src = { | |
293 | .name = "sys_clkout_src", | |
c1168dc3 | 294 | .ops = &clkops_omap2_dflt, |
e32744b0 | 295 | .parent = &func_54m_ck, |
d1b03f61 | 296 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 297 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
298 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
299 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 300 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
301 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
302 | .clksel = common_clkout_src_clksel, | |
303 | .recalc = &omap2_clksel_recalc, | |
304 | .round_rate = &omap2_clksel_round_rate, | |
305 | .set_rate = &omap2_clksel_set_rate | |
306 | }; | |
307 | ||
308 | static const struct clksel_rate common_clkout_rates[] = { | |
d74b4949 | 309 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
310 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
311 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | |
312 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | |
313 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | |
314 | { .div = 0 }, | |
315 | }; | |
316 | ||
317 | static const struct clksel sys_clkout_clksel[] = { | |
318 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | |
319 | { .parent = NULL } | |
046d6b28 TL |
320 | }; |
321 | ||
322 | static struct clk sys_clkout = { | |
323 | .name = "sys_clkout", | |
57137181 | 324 | .ops = &clkops_null, |
e32744b0 | 325 | .parent = &sys_clkout_src, |
d1b03f61 | 326 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 327 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
328 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
329 | .clksel = sys_clkout_clksel, | |
330 | .recalc = &omap2_clksel_recalc, | |
331 | .round_rate = &omap2_clksel_round_rate, | |
332 | .set_rate = &omap2_clksel_set_rate | |
333 | }; | |
334 | ||
335 | /* In 2430, new in 2420 ES2 */ | |
336 | static struct clk sys_clkout2_src = { | |
337 | .name = "sys_clkout2_src", | |
c1168dc3 | 338 | .ops = &clkops_omap2_dflt, |
e32744b0 | 339 | .parent = &func_54m_ck, |
d1b03f61 | 340 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 341 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
342 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
343 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 344 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
345 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, |
346 | .clksel = common_clkout_src_clksel, | |
046d6b28 | 347 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
348 | .round_rate = &omap2_clksel_round_rate, |
349 | .set_rate = &omap2_clksel_set_rate | |
350 | }; | |
351 | ||
352 | static const struct clksel sys_clkout2_clksel[] = { | |
353 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | |
354 | { .parent = NULL } | |
046d6b28 TL |
355 | }; |
356 | ||
357 | /* In 2430, new in 2420 ES2 */ | |
358 | static struct clk sys_clkout2 = { | |
359 | .name = "sys_clkout2", | |
57137181 | 360 | .ops = &clkops_null, |
e32744b0 | 361 | .parent = &sys_clkout2_src, |
d1b03f61 | 362 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 363 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
364 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
365 | .clksel = sys_clkout2_clksel, | |
046d6b28 | 366 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
367 | .round_rate = &omap2_clksel_round_rate, |
368 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
369 | }; |
370 | ||
b824efae TL |
371 | static struct clk emul_ck = { |
372 | .name = "emul_ck", | |
c1168dc3 | 373 | .ops = &clkops_omap2_dflt, |
b824efae | 374 | .parent = &func_54m_ck, |
d1b03f61 | 375 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 376 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, |
e32744b0 PW |
377 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
378 | .recalc = &followparent_recalc, | |
b824efae TL |
379 | |
380 | }; | |
e32744b0 | 381 | |
046d6b28 TL |
382 | /* |
383 | * MPU clock domain | |
384 | * Clocks: | |
385 | * MPU_FCLK, MPU_ICLK | |
386 | * INT_M_FCLK, INT_M_I_CLK | |
387 | * | |
388 | * - Individual clocks are hardware managed. | |
389 | * - Base divider comes from: CM_CLKSEL_MPU | |
390 | * | |
391 | */ | |
e32744b0 | 392 | static const struct clksel_rate mpu_core_rates[] = { |
d74b4949 | 393 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
394 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
395 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
396 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
397 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
398 | { .div = 0 }, | |
399 | }; | |
400 | ||
401 | static const struct clksel mpu_clksel[] = { | |
402 | { .parent = &core_ck, .rates = mpu_core_rates }, | |
403 | { .parent = NULL } | |
404 | }; | |
405 | ||
046d6b28 TL |
406 | static struct clk mpu_ck = { /* Control cpu */ |
407 | .name = "mpu_ck", | |
897dcded | 408 | .ops = &clkops_null, |
046d6b28 | 409 | .parent = &core_ck, |
d1b03f61 | 410 | .clkdm_name = "mpu_clkdm", |
6b8858a9 PW |
411 | .init = &omap2_init_clksel_parent, |
412 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
413 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | |
e32744b0 | 414 | .clksel = mpu_clksel, |
046d6b28 TL |
415 | .recalc = &omap2_clksel_recalc, |
416 | }; | |
e32744b0 | 417 | |
046d6b28 | 418 | /* |
81b34fbe | 419 | * DSP (2420-UMA+IVA1) clock domain |
046d6b28 | 420 | * Clocks: |
046d6b28 | 421 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
e32744b0 PW |
422 | * |
423 | * Won't be too specific here. The core clock comes into this block | |
424 | * it is divided then tee'ed. One branch goes directly to xyz enable | |
425 | * controls. The other branch gets further divided by 2 then possibly | |
426 | * routed into a synchronizer and out of clocks abc. | |
046d6b28 | 427 | */ |
e32744b0 | 428 | static const struct clksel_rate dsp_fck_core_rates[] = { |
d74b4949 | 429 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
430 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
431 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
432 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
433 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
434 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
435 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
436 | { .div = 0 }, | |
437 | }; | |
438 | ||
439 | static const struct clksel dsp_fck_clksel[] = { | |
440 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
441 | { .parent = NULL } | |
442 | }; | |
443 | ||
444 | static struct clk dsp_fck = { | |
445 | .name = "dsp_fck", | |
b36ee724 | 446 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 447 | .parent = &core_ck, |
d1b03f61 | 448 | .clkdm_name = "dsp_clkdm", |
e32744b0 PW |
449 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
450 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
451 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
452 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | |
453 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
454 | .recalc = &omap2_clksel_recalc, |
455 | }; | |
456 | ||
22411396 PW |
457 | static const struct clksel dsp_ick_clksel[] = { |
458 | { .parent = &dsp_fck, .rates = dsp_ick_rates }, | |
e32744b0 | 459 | { .parent = NULL } |
046d6b28 TL |
460 | }; |
461 | ||
046d6b28 TL |
462 | static struct clk dsp_ick = { |
463 | .name = "dsp_ick", /* apparently ipi and isp */ | |
6ae690da | 464 | .ops = &clkops_omap2_iclk_dflt_wait, |
22411396 PW |
465 | .parent = &dsp_fck, |
466 | .clkdm_name = "dsp_clkdm", | |
e32744b0 PW |
467 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
468 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | |
22411396 PW |
469 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
470 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | |
471 | .clksel = dsp_ick_clksel, | |
472 | .recalc = &omap2_clksel_recalc, | |
e32744b0 PW |
473 | }; |
474 | ||
d1b03f61 PW |
475 | /* |
476 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | |
477 | * the C54x, but which is contained in the DSP powerdomain. Does not | |
478 | * exist on later OMAPs. | |
479 | */ | |
046d6b28 TL |
480 | static struct clk iva1_ifck = { |
481 | .name = "iva1_ifck", | |
b36ee724 | 482 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 483 | .parent = &core_ck, |
d1b03f61 | 484 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
485 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
486 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | |
487 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
488 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | |
489 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
490 | .recalc = &omap2_clksel_recalc, |
491 | }; | |
492 | ||
493 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | |
494 | static struct clk iva1_mpu_int_ifck = { | |
495 | .name = "iva1_mpu_int_ifck", | |
b36ee724 | 496 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 497 | .parent = &iva1_ifck, |
d1b03f61 | 498 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
499 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
500 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | |
501 | .fixed_div = 2, | |
e9b98f60 | 502 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
503 | }; |
504 | ||
505 | /* | |
506 | * L3 clock domain | |
507 | * L3 clocks are used for both interface and functional clocks to | |
508 | * multiple entities. Some of these clocks are completely managed | |
509 | * by hardware, and some others allow software control. Hardware | |
510 | * managed ones general are based on directly CLK_REQ signals and | |
511 | * various auto idle settings. The functional spec sets many of these | |
512 | * as 'tie-high' for their enables. | |
513 | * | |
514 | * I-CLOCKS: | |
515 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | |
516 | * CAM, HS-USB. | |
517 | * F-CLOCK | |
518 | * SSI. | |
519 | * | |
520 | * GPMC memories and SDRC have timing and clock sensitive registers which | |
521 | * may very well need notification when the clock changes. Currently for low | |
522 | * operating points, these are taken care of in sleep.S. | |
523 | */ | |
e32744b0 PW |
524 | static const struct clksel_rate core_l3_core_rates[] = { |
525 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
526 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
d74b4949 | 527 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
e32744b0 PW |
528 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
529 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
530 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
531 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | |
532 | { .div = 0 } | |
533 | }; | |
534 | ||
535 | static const struct clksel core_l3_clksel[] = { | |
536 | { .parent = &core_ck, .rates = core_l3_core_rates }, | |
537 | { .parent = NULL } | |
538 | }; | |
539 | ||
046d6b28 TL |
540 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
541 | .name = "core_l3_ck", | |
897dcded | 542 | .ops = &clkops_null, |
046d6b28 | 543 | .parent = &core_ck, |
d1b03f61 | 544 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
545 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
546 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | |
547 | .clksel = core_l3_clksel, | |
046d6b28 | 548 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
549 | }; |
550 | ||
551 | /* usb_l4_ick */ | |
552 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
553 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 554 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
555 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
556 | { .div = 0 } | |
557 | }; | |
558 | ||
559 | static const struct clksel usb_l4_ick_clksel[] = { | |
560 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
561 | { .parent = NULL }, | |
046d6b28 TL |
562 | }; |
563 | ||
d1b03f61 | 564 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
046d6b28 TL |
565 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
566 | .name = "usb_l4_ick", | |
6ae690da | 567 | .ops = &clkops_omap2_iclk_dflt_wait, |
fde0fd49 | 568 | .parent = &core_l3_ck, |
d1b03f61 | 569 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
571 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
572 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
573 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | |
574 | .clksel = usb_l4_ick_clksel, | |
046d6b28 TL |
575 | .recalc = &omap2_clksel_recalc, |
576 | }; | |
577 | ||
d1b03f61 PW |
578 | /* |
579 | * L4 clock management domain | |
580 | * | |
581 | * This domain contains lots of interface clocks from the L4 interface, some | |
582 | * functional clocks. Fixed APLL functional source clocks are managed in | |
583 | * this domain. | |
584 | */ | |
585 | static const struct clksel_rate l4_core_l3_rates[] = { | |
d74b4949 | 586 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
d1b03f61 PW |
587 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
588 | { .div = 0 } | |
589 | }; | |
590 | ||
591 | static const struct clksel l4_clksel[] = { | |
592 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | |
593 | { .parent = NULL } | |
594 | }; | |
595 | ||
596 | static struct clk l4_ck = { /* used both as an ick and fck */ | |
597 | .name = "l4_ck", | |
897dcded | 598 | .ops = &clkops_null, |
d1b03f61 | 599 | .parent = &core_l3_ck, |
d1b03f61 PW |
600 | .clkdm_name = "core_l4_clkdm", |
601 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
602 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | |
603 | .clksel = l4_clksel, | |
604 | .recalc = &omap2_clksel_recalc, | |
d1b03f61 PW |
605 | }; |
606 | ||
046d6b28 TL |
607 | /* |
608 | * SSI is in L3 management domain, its direct parent is core not l3, | |
609 | * many core power domain entities are grouped into the L3 clock | |
610 | * domain. | |
d1b03f61 | 611 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
046d6b28 TL |
612 | * |
613 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | |
614 | */ | |
e32744b0 PW |
615 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
616 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 617 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
618 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
619 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
e32744b0 PW |
620 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
621 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
622 | { .div = 0 } | |
623 | }; | |
624 | ||
625 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
626 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
627 | { .parent = NULL } | |
628 | }; | |
629 | ||
046d6b28 TL |
630 | static struct clk ssi_ssr_sst_fck = { |
631 | .name = "ssi_fck", | |
b36ee724 | 632 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 633 | .parent = &core_ck, |
d1b03f61 | 634 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
635 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
636 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
637 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
638 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | |
639 | .clksel = ssi_ssr_sst_fck_clksel, | |
046d6b28 TL |
640 | .recalc = &omap2_clksel_recalc, |
641 | }; | |
642 | ||
9299fd85 PW |
643 | /* |
644 | * Presumably this is the same as SSI_ICLK. | |
645 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | |
646 | */ | |
647 | static struct clk ssi_l4_ick = { | |
648 | .name = "ssi_l4_ick", | |
6ae690da | 649 | .ops = &clkops_omap2_iclk_dflt_wait, |
9299fd85 PW |
650 | .parent = &l4_ck, |
651 | .clkdm_name = "core_l4_clkdm", | |
652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
653 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
654 | .recalc = &followparent_recalc, | |
655 | }; | |
656 | ||
d1b03f61 | 657 | |
046d6b28 TL |
658 | /* |
659 | * GFX clock domain | |
660 | * Clocks: | |
661 | * GFX_FCLK, GFX_ICLK | |
662 | * GFX_CG1(2d), GFX_CG2(3d) | |
663 | * | |
664 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | |
665 | * The 2d and 3d clocks run at a hardware determined | |
666 | * divided value of fclk. | |
667 | * | |
668 | */ | |
e32744b0 PW |
669 | |
670 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | |
671 | static const struct clksel gfx_fck_clksel[] = { | |
672 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
673 | { .parent = NULL }, | |
674 | }; | |
675 | ||
046d6b28 TL |
676 | static struct clk gfx_3d_fck = { |
677 | .name = "gfx_3d_fck", | |
b36ee724 | 678 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 679 | .parent = &core_l3_ck, |
d1b03f61 | 680 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
681 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
682 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | |
683 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
684 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
685 | .clksel = gfx_fck_clksel, | |
046d6b28 | 686 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
687 | .round_rate = &omap2_clksel_round_rate, |
688 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
689 | }; |
690 | ||
691 | static struct clk gfx_2d_fck = { | |
692 | .name = "gfx_2d_fck", | |
b36ee724 | 693 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 694 | .parent = &core_l3_ck, |
d1b03f61 | 695 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
696 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
697 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | |
698 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
699 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
700 | .clksel = gfx_fck_clksel, | |
046d6b28 TL |
701 | .recalc = &omap2_clksel_recalc, |
702 | }; | |
703 | ||
6ae690da | 704 | /* This interface clock does not have a CM_AUTOIDLE bit */ |
046d6b28 TL |
705 | static struct clk gfx_ick = { |
706 | .name = "gfx_ick", /* From l3 */ | |
b36ee724 | 707 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 708 | .parent = &core_l3_ck, |
d1b03f61 | 709 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
710 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
711 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
712 | .recalc = &followparent_recalc, | |
046d6b28 TL |
713 | }; |
714 | ||
046d6b28 TL |
715 | /* |
716 | * DSS clock domain | |
717 | * CLOCKs: | |
718 | * DSS_L4_ICLK, DSS_L3_ICLK, | |
719 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | |
720 | * | |
721 | * DSS is both initiator and target. | |
722 | */ | |
e32744b0 PW |
723 | /* XXX Add RATE_NOT_VALIDATED */ |
724 | ||
725 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
d74b4949 | 726 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
727 | { .div = 0 } |
728 | }; | |
729 | ||
730 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
731 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
732 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
733 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
734 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
735 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
736 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
737 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
738 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
739 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
d74b4949 | 740 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, |
e32744b0 PW |
741 | { .div = 0 } |
742 | }; | |
743 | ||
744 | static const struct clksel dss1_fck_clksel[] = { | |
745 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
746 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
747 | { .parent = NULL }, | |
748 | }; | |
749 | ||
046d6b28 TL |
750 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
751 | .name = "dss_ick", | |
6ae690da | 752 | .ops = &clkops_omap2_iclk_dflt, |
046d6b28 | 753 | .parent = &l4_ck, /* really both l3 and l4 */ |
d1b03f61 | 754 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
755 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
756 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
757 | .recalc = &followparent_recalc, | |
046d6b28 TL |
758 | }; |
759 | ||
760 | static struct clk dss1_fck = { | |
761 | .name = "dss1_fck", | |
bc51da4e | 762 | .ops = &clkops_omap2_dflt, |
046d6b28 | 763 | .parent = &core_ck, /* Core or sys */ |
d1b03f61 | 764 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
766 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
767 | .init = &omap2_init_clksel_parent, | |
768 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
769 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | |
770 | .clksel = dss1_fck_clksel, | |
046d6b28 | 771 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
772 | }; |
773 | ||
774 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
d74b4949 | 775 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
776 | { .div = 0 } |
777 | }; | |
778 | ||
779 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
d74b4949 | 780 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
781 | { .div = 0 } |
782 | }; | |
783 | ||
784 | static const struct clksel dss2_fck_clksel[] = { | |
785 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
786 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
787 | { .parent = NULL } | |
046d6b28 TL |
788 | }; |
789 | ||
790 | static struct clk dss2_fck = { /* Alt clk used in power management */ | |
791 | .name = "dss2_fck", | |
bc51da4e | 792 | .ops = &clkops_omap2_dflt, |
046d6b28 | 793 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
d1b03f61 | 794 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
795 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
796 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | |
797 | .init = &omap2_init_clksel_parent, | |
798 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
799 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | |
800 | .clksel = dss2_fck_clksel, | |
d4521f67 | 801 | .recalc = &omap2_clksel_recalc, |
046d6b28 TL |
802 | }; |
803 | ||
804 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |
805 | .name = "dss_54m_fck", /* 54m tv clk */ | |
b36ee724 | 806 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 807 | .parent = &func_54m_ck, |
d1b03f61 | 808 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
809 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
810 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
811 | .recalc = &followparent_recalc, | |
046d6b28 TL |
812 | }; |
813 | ||
19c1c0ce PW |
814 | static struct clk wu_l4_ick = { |
815 | .name = "wu_l4_ick", | |
816 | .ops = &clkops_null, | |
817 | .parent = &sys_ck, | |
818 | .clkdm_name = "wkup_clkdm", | |
819 | .recalc = &followparent_recalc, | |
820 | }; | |
821 | ||
046d6b28 TL |
822 | /* |
823 | * CORE power domain ICLK & FCLK defines. | |
824 | * Many of the these can have more than one possible parent. Entries | |
825 | * here will likely have an L4 interface parent, and may have multiple | |
826 | * functional clock parents. | |
827 | */ | |
e32744b0 | 828 | static const struct clksel_rate gpt_alt_rates[] = { |
d74b4949 | 829 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
830 | { .div = 0 } |
831 | }; | |
832 | ||
833 | static const struct clksel omap24xx_gpt_clksel[] = { | |
834 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
835 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
836 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
837 | { .parent = NULL }, | |
838 | }; | |
839 | ||
046d6b28 TL |
840 | static struct clk gpt1_ick = { |
841 | .name = "gpt1_ick", | |
6ae690da | 842 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
843 | .parent = &wu_l4_ick, |
844 | .clkdm_name = "wkup_clkdm", | |
e32744b0 PW |
845 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
846 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
847 | .recalc = &followparent_recalc, | |
046d6b28 TL |
848 | }; |
849 | ||
850 | static struct clk gpt1_fck = { | |
851 | .name = "gpt1_fck", | |
b36ee724 | 852 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 853 | .parent = &func_32k_ck, |
d1b03f61 | 854 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
855 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
856 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
857 | .init = &omap2_init_clksel_parent, | |
858 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
859 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | |
860 | .clksel = omap24xx_gpt_clksel, | |
861 | .recalc = &omap2_clksel_recalc, | |
862 | .round_rate = &omap2_clksel_round_rate, | |
863 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
864 | }; |
865 | ||
866 | static struct clk gpt2_ick = { | |
867 | .name = "gpt2_ick", | |
6ae690da | 868 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 869 | .parent = &l4_ck, |
d1b03f61 | 870 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
872 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
873 | .recalc = &followparent_recalc, | |
046d6b28 TL |
874 | }; |
875 | ||
876 | static struct clk gpt2_fck = { | |
877 | .name = "gpt2_fck", | |
b36ee724 | 878 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 879 | .parent = &func_32k_ck, |
d1b03f61 | 880 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
881 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
882 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
883 | .init = &omap2_init_clksel_parent, | |
884 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
885 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | |
886 | .clksel = omap24xx_gpt_clksel, | |
887 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
888 | }; |
889 | ||
890 | static struct clk gpt3_ick = { | |
891 | .name = "gpt3_ick", | |
6ae690da | 892 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 893 | .parent = &l4_ck, |
d1b03f61 | 894 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
895 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
896 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
897 | .recalc = &followparent_recalc, | |
046d6b28 TL |
898 | }; |
899 | ||
900 | static struct clk gpt3_fck = { | |
901 | .name = "gpt3_fck", | |
b36ee724 | 902 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 903 | .parent = &func_32k_ck, |
d1b03f61 | 904 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
905 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
906 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
907 | .init = &omap2_init_clksel_parent, | |
908 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
909 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | |
910 | .clksel = omap24xx_gpt_clksel, | |
911 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
912 | }; |
913 | ||
914 | static struct clk gpt4_ick = { | |
915 | .name = "gpt4_ick", | |
6ae690da | 916 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 917 | .parent = &l4_ck, |
d1b03f61 | 918 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
919 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
920 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
921 | .recalc = &followparent_recalc, | |
046d6b28 TL |
922 | }; |
923 | ||
924 | static struct clk gpt4_fck = { | |
925 | .name = "gpt4_fck", | |
b36ee724 | 926 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 927 | .parent = &func_32k_ck, |
d1b03f61 | 928 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
929 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
930 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
931 | .init = &omap2_init_clksel_parent, | |
932 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
933 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | |
934 | .clksel = omap24xx_gpt_clksel, | |
935 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
936 | }; |
937 | ||
938 | static struct clk gpt5_ick = { | |
939 | .name = "gpt5_ick", | |
6ae690da | 940 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 941 | .parent = &l4_ck, |
d1b03f61 | 942 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
943 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
944 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
945 | .recalc = &followparent_recalc, | |
046d6b28 TL |
946 | }; |
947 | ||
948 | static struct clk gpt5_fck = { | |
949 | .name = "gpt5_fck", | |
b36ee724 | 950 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 951 | .parent = &func_32k_ck, |
d1b03f61 | 952 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
953 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
954 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
955 | .init = &omap2_init_clksel_parent, | |
956 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
957 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | |
958 | .clksel = omap24xx_gpt_clksel, | |
959 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
960 | }; |
961 | ||
962 | static struct clk gpt6_ick = { | |
963 | .name = "gpt6_ick", | |
6ae690da | 964 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 965 | .parent = &l4_ck, |
d1b03f61 | 966 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
967 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
968 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
969 | .recalc = &followparent_recalc, | |
046d6b28 TL |
970 | }; |
971 | ||
972 | static struct clk gpt6_fck = { | |
973 | .name = "gpt6_fck", | |
b36ee724 | 974 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 975 | .parent = &func_32k_ck, |
d1b03f61 | 976 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
978 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
979 | .init = &omap2_init_clksel_parent, | |
980 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
981 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | |
982 | .clksel = omap24xx_gpt_clksel, | |
983 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
984 | }; |
985 | ||
986 | static struct clk gpt7_ick = { | |
987 | .name = "gpt7_ick", | |
6ae690da | 988 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 989 | .parent = &l4_ck, |
a4fc9274 | 990 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
991 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
992 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
993 | .recalc = &followparent_recalc, | |
046d6b28 TL |
994 | }; |
995 | ||
996 | static struct clk gpt7_fck = { | |
997 | .name = "gpt7_fck", | |
b36ee724 | 998 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 999 | .parent = &func_32k_ck, |
d1b03f61 | 1000 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1001 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1002 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
1003 | .init = &omap2_init_clksel_parent, | |
1004 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1005 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | |
1006 | .clksel = omap24xx_gpt_clksel, | |
1007 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1008 | }; |
1009 | ||
1010 | static struct clk gpt8_ick = { | |
1011 | .name = "gpt8_ick", | |
6ae690da | 1012 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1013 | .parent = &l4_ck, |
d1b03f61 | 1014 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1015 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1016 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1017 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1018 | }; |
1019 | ||
1020 | static struct clk gpt8_fck = { | |
1021 | .name = "gpt8_fck", | |
b36ee724 | 1022 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1023 | .parent = &func_32k_ck, |
d1b03f61 | 1024 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1026 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1027 | .init = &omap2_init_clksel_parent, | |
1028 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1029 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | |
1030 | .clksel = omap24xx_gpt_clksel, | |
1031 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1032 | }; |
1033 | ||
1034 | static struct clk gpt9_ick = { | |
1035 | .name = "gpt9_ick", | |
6ae690da | 1036 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1037 | .parent = &l4_ck, |
d1b03f61 | 1038 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1039 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1040 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1041 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1042 | }; |
1043 | ||
1044 | static struct clk gpt9_fck = { | |
1045 | .name = "gpt9_fck", | |
b36ee724 | 1046 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1047 | .parent = &func_32k_ck, |
d1b03f61 | 1048 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1049 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1050 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1051 | .init = &omap2_init_clksel_parent, | |
1052 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1053 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | |
1054 | .clksel = omap24xx_gpt_clksel, | |
1055 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1056 | }; |
1057 | ||
1058 | static struct clk gpt10_ick = { | |
1059 | .name = "gpt10_ick", | |
6ae690da | 1060 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1061 | .parent = &l4_ck, |
d1b03f61 | 1062 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1063 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1064 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1065 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1066 | }; |
1067 | ||
1068 | static struct clk gpt10_fck = { | |
1069 | .name = "gpt10_fck", | |
b36ee724 | 1070 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1071 | .parent = &func_32k_ck, |
d1b03f61 | 1072 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1073 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1074 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1075 | .init = &omap2_init_clksel_parent, | |
1076 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1077 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | |
1078 | .clksel = omap24xx_gpt_clksel, | |
1079 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1080 | }; |
1081 | ||
1082 | static struct clk gpt11_ick = { | |
1083 | .name = "gpt11_ick", | |
6ae690da | 1084 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1085 | .parent = &l4_ck, |
d1b03f61 | 1086 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1087 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1088 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1089 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1090 | }; |
1091 | ||
1092 | static struct clk gpt11_fck = { | |
1093 | .name = "gpt11_fck", | |
b36ee724 | 1094 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1095 | .parent = &func_32k_ck, |
d1b03f61 | 1096 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1097 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1098 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1099 | .init = &omap2_init_clksel_parent, | |
1100 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1101 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | |
1102 | .clksel = omap24xx_gpt_clksel, | |
1103 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1104 | }; |
1105 | ||
1106 | static struct clk gpt12_ick = { | |
1107 | .name = "gpt12_ick", | |
6ae690da | 1108 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1109 | .parent = &l4_ck, |
d1b03f61 | 1110 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1111 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1112 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1113 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1114 | }; |
1115 | ||
1116 | static struct clk gpt12_fck = { | |
1117 | .name = "gpt12_fck", | |
b36ee724 | 1118 | .ops = &clkops_omap2_dflt_wait, |
f248076c | 1119 | .parent = &secure_32k_ck, |
d1b03f61 | 1120 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1121 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1122 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1123 | .init = &omap2_init_clksel_parent, | |
1124 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1125 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | |
1126 | .clksel = omap24xx_gpt_clksel, | |
1127 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1128 | }; |
1129 | ||
1130 | static struct clk mcbsp1_ick = { | |
b92c170d | 1131 | .name = "mcbsp1_ick", |
6ae690da | 1132 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1133 | .parent = &l4_ck, |
d1b03f61 | 1134 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1135 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1136 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1137 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1138 | }; |
1139 | ||
1bccb345 PW |
1140 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
1141 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
1142 | { .div = 0 } | |
1143 | }; | |
1144 | ||
1145 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1146 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1147 | { .div = 0 } | |
1148 | }; | |
1149 | ||
1150 | static const struct clksel mcbsp_fck_clksel[] = { | |
1151 | { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, | |
1152 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1153 | { .parent = NULL } | |
1154 | }; | |
1155 | ||
046d6b28 | 1156 | static struct clk mcbsp1_fck = { |
b92c170d | 1157 | .name = "mcbsp1_fck", |
b36ee724 | 1158 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1159 | .parent = &func_96m_ck, |
1bccb345 | 1160 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1161 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1162 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1163 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1bccb345 PW |
1164 | .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
1165 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1166 | .clksel = mcbsp_fck_clksel, | |
1167 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1168 | }; |
1169 | ||
1170 | static struct clk mcbsp2_ick = { | |
b92c170d | 1171 | .name = "mcbsp2_ick", |
6ae690da | 1172 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1173 | .parent = &l4_ck, |
d1b03f61 | 1174 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1175 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1176 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1177 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1178 | }; |
1179 | ||
1180 | static struct clk mcbsp2_fck = { | |
b92c170d | 1181 | .name = "mcbsp2_fck", |
b36ee724 | 1182 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1183 | .parent = &func_96m_ck, |
1bccb345 | 1184 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1185 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1186 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1187 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1bccb345 PW |
1188 | .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
1189 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
1190 | .clksel = mcbsp_fck_clksel, | |
1191 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1192 | }; |
1193 | ||
046d6b28 | 1194 | static struct clk mcspi1_ick = { |
b92c170d | 1195 | .name = "mcspi1_ick", |
6ae690da | 1196 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1197 | .parent = &l4_ck, |
d1b03f61 | 1198 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1199 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1200 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1201 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1202 | }; |
1203 | ||
1204 | static struct clk mcspi1_fck = { | |
b92c170d | 1205 | .name = "mcspi1_fck", |
b36ee724 | 1206 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1207 | .parent = &func_48m_ck, |
d1b03f61 | 1208 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1209 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1210 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1211 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1212 | }; |
1213 | ||
1214 | static struct clk mcspi2_ick = { | |
b92c170d | 1215 | .name = "mcspi2_ick", |
6ae690da | 1216 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1217 | .parent = &l4_ck, |
d1b03f61 | 1218 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1219 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1220 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1221 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1222 | }; |
1223 | ||
1224 | static struct clk mcspi2_fck = { | |
b92c170d | 1225 | .name = "mcspi2_fck", |
b36ee724 | 1226 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1227 | .parent = &func_48m_ck, |
d1b03f61 | 1228 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1229 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1230 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1231 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1232 | }; |
1233 | ||
046d6b28 TL |
1234 | static struct clk uart1_ick = { |
1235 | .name = "uart1_ick", | |
6ae690da | 1236 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1237 | .parent = &l4_ck, |
d1b03f61 | 1238 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1239 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1240 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1241 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1242 | }; |
1243 | ||
1244 | static struct clk uart1_fck = { | |
1245 | .name = "uart1_fck", | |
b36ee724 | 1246 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1247 | .parent = &func_48m_ck, |
d1b03f61 | 1248 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1249 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1250 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1251 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1252 | }; |
1253 | ||
1254 | static struct clk uart2_ick = { | |
1255 | .name = "uart2_ick", | |
6ae690da | 1256 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1257 | .parent = &l4_ck, |
d1b03f61 | 1258 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1259 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1260 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1261 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1262 | }; |
1263 | ||
1264 | static struct clk uart2_fck = { | |
1265 | .name = "uart2_fck", | |
b36ee724 | 1266 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1267 | .parent = &func_48m_ck, |
d1b03f61 | 1268 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1269 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1270 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1271 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1272 | }; |
1273 | ||
1274 | static struct clk uart3_ick = { | |
1275 | .name = "uart3_ick", | |
6ae690da | 1276 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1277 | .parent = &l4_ck, |
d1b03f61 | 1278 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1279 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1280 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1281 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1282 | }; |
1283 | ||
1284 | static struct clk uart3_fck = { | |
1285 | .name = "uart3_fck", | |
b36ee724 | 1286 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1287 | .parent = &func_48m_ck, |
d1b03f61 | 1288 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1289 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1290 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1291 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1292 | }; |
1293 | ||
1294 | static struct clk gpios_ick = { | |
1295 | .name = "gpios_ick", | |
6ae690da | 1296 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
1297 | .parent = &wu_l4_ick, |
1298 | .clkdm_name = "wkup_clkdm", | |
e32744b0 PW |
1299 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1300 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1301 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1302 | }; |
1303 | ||
1304 | static struct clk gpios_fck = { | |
1305 | .name = "gpios_fck", | |
b36ee724 | 1306 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1307 | .parent = &func_32k_ck, |
d1b03f61 | 1308 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1309 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1310 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1311 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1312 | }; |
1313 | ||
1314 | static struct clk mpu_wdt_ick = { | |
1315 | .name = "mpu_wdt_ick", | |
6ae690da | 1316 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
1317 | .parent = &wu_l4_ick, |
1318 | .clkdm_name = "wkup_clkdm", | |
e32744b0 PW |
1319 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1320 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1321 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1322 | }; |
1323 | ||
1324 | static struct clk mpu_wdt_fck = { | |
1325 | .name = "mpu_wdt_fck", | |
b36ee724 | 1326 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1327 | .parent = &func_32k_ck, |
d1b03f61 | 1328 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1329 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1330 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1331 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1332 | }; |
1333 | ||
1334 | static struct clk sync_32k_ick = { | |
1335 | .name = "sync_32k_ick", | |
6ae690da | 1336 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
1337 | .parent = &wu_l4_ick, |
1338 | .clkdm_name = "wkup_clkdm", | |
8ad8ff65 | 1339 | .flags = ENABLE_ON_INIT, |
e32744b0 PW |
1340 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1341 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1342 | .recalc = &followparent_recalc, | |
046d6b28 | 1343 | }; |
d1b03f61 | 1344 | |
046d6b28 TL |
1345 | static struct clk wdt1_ick = { |
1346 | .name = "wdt1_ick", | |
6ae690da | 1347 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
1348 | .parent = &wu_l4_ick, |
1349 | .clkdm_name = "wkup_clkdm", | |
e32744b0 PW |
1350 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1351 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1352 | .recalc = &followparent_recalc, | |
046d6b28 | 1353 | }; |
d1b03f61 | 1354 | |
046d6b28 TL |
1355 | static struct clk omapctrl_ick = { |
1356 | .name = "omapctrl_ick", | |
6ae690da | 1357 | .ops = &clkops_omap2_iclk_dflt_wait, |
19c1c0ce PW |
1358 | .parent = &wu_l4_ick, |
1359 | .clkdm_name = "wkup_clkdm", | |
8ad8ff65 | 1360 | .flags = ENABLE_ON_INIT, |
e32744b0 PW |
1361 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1362 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1363 | .recalc = &followparent_recalc, | |
046d6b28 | 1364 | }; |
d1b03f61 | 1365 | |
046d6b28 TL |
1366 | static struct clk cam_ick = { |
1367 | .name = "cam_ick", | |
6ae690da | 1368 | .ops = &clkops_omap2_iclk_dflt, |
046d6b28 | 1369 | .parent = &l4_ck, |
d1b03f61 | 1370 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1372 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1373 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1374 | }; |
1375 | ||
d1b03f61 PW |
1376 | /* |
1377 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | |
1378 | * split into two separate clocks, since the parent clocks are different | |
1379 | * and the clockdomains are also different. | |
1380 | */ | |
046d6b28 TL |
1381 | static struct clk cam_fck = { |
1382 | .name = "cam_fck", | |
bc51da4e | 1383 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1384 | .parent = &func_96m_ck, |
d1b03f61 | 1385 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1386 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1387 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1388 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1389 | }; |
1390 | ||
1391 | static struct clk mailboxes_ick = { | |
1392 | .name = "mailboxes_ick", | |
6ae690da | 1393 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1394 | .parent = &l4_ck, |
d1b03f61 | 1395 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1396 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1397 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1398 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1399 | }; |
1400 | ||
1401 | static struct clk wdt4_ick = { | |
1402 | .name = "wdt4_ick", | |
6ae690da | 1403 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1404 | .parent = &l4_ck, |
d1b03f61 | 1405 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1406 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1407 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1408 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1409 | }; |
1410 | ||
1411 | static struct clk wdt4_fck = { | |
1412 | .name = "wdt4_fck", | |
b36ee724 | 1413 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1414 | .parent = &func_32k_ck, |
d1b03f61 | 1415 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1416 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1417 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1418 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1419 | }; |
1420 | ||
1421 | static struct clk wdt3_ick = { | |
1422 | .name = "wdt3_ick", | |
6ae690da | 1423 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1424 | .parent = &l4_ck, |
d1b03f61 | 1425 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1426 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1427 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1428 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1429 | }; |
1430 | ||
1431 | static struct clk wdt3_fck = { | |
1432 | .name = "wdt3_fck", | |
b36ee724 | 1433 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1434 | .parent = &func_32k_ck, |
d1b03f61 | 1435 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1436 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1437 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1438 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1439 | }; |
1440 | ||
1441 | static struct clk mspro_ick = { | |
1442 | .name = "mspro_ick", | |
6ae690da | 1443 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1444 | .parent = &l4_ck, |
d1b03f61 | 1445 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1447 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1448 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1449 | }; |
1450 | ||
1451 | static struct clk mspro_fck = { | |
1452 | .name = "mspro_fck", | |
b36ee724 | 1453 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1454 | .parent = &func_96m_ck, |
d1b03f61 | 1455 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1456 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1457 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1458 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1459 | }; |
1460 | ||
1461 | static struct clk mmc_ick = { | |
1462 | .name = "mmc_ick", | |
6ae690da | 1463 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1464 | .parent = &l4_ck, |
d1b03f61 | 1465 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1467 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1468 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1469 | }; |
1470 | ||
1471 | static struct clk mmc_fck = { | |
1472 | .name = "mmc_fck", | |
b36ee724 | 1473 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1474 | .parent = &func_96m_ck, |
d1b03f61 | 1475 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1476 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1477 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1478 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1479 | }; |
1480 | ||
1481 | static struct clk fac_ick = { | |
1482 | .name = "fac_ick", | |
6ae690da | 1483 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1484 | .parent = &l4_ck, |
d1b03f61 | 1485 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1486 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1487 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1488 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1489 | }; |
1490 | ||
1491 | static struct clk fac_fck = { | |
1492 | .name = "fac_fck", | |
b36ee724 | 1493 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1494 | .parent = &func_12m_ck, |
d1b03f61 | 1495 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1497 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1498 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1499 | }; |
1500 | ||
1501 | static struct clk eac_ick = { | |
1502 | .name = "eac_ick", | |
6ae690da | 1503 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1504 | .parent = &l4_ck, |
d1b03f61 | 1505 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1506 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1507 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1508 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1509 | }; |
1510 | ||
1511 | static struct clk eac_fck = { | |
1512 | .name = "eac_fck", | |
b36ee724 | 1513 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1514 | .parent = &func_96m_ck, |
d1b03f61 | 1515 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1517 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1518 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1519 | }; |
1520 | ||
1521 | static struct clk hdq_ick = { | |
1522 | .name = "hdq_ick", | |
6ae690da | 1523 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1524 | .parent = &l4_ck, |
d1b03f61 | 1525 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1527 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1528 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1529 | }; |
1530 | ||
1531 | static struct clk hdq_fck = { | |
1532 | .name = "hdq_fck", | |
b36ee724 | 1533 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1534 | .parent = &func_12m_ck, |
d1b03f61 | 1535 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1536 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1537 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1538 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1539 | }; |
1540 | ||
1541 | static struct clk i2c2_ick = { | |
b92c170d | 1542 | .name = "i2c2_ick", |
6ae690da | 1543 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1544 | .parent = &l4_ck, |
d1b03f61 | 1545 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1547 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1548 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1549 | }; |
1550 | ||
1551 | static struct clk i2c2_fck = { | |
b92c170d | 1552 | .name = "i2c2_fck", |
b36ee724 | 1553 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1554 | .parent = &func_12m_ck, |
d1b03f61 | 1555 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1556 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1557 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1558 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1559 | }; |
1560 | ||
046d6b28 | 1561 | static struct clk i2c1_ick = { |
b92c170d | 1562 | .name = "i2c1_ick", |
6ae690da | 1563 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1564 | .parent = &l4_ck, |
d1b03f61 | 1565 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1566 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1567 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1568 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1569 | }; |
1570 | ||
1571 | static struct clk i2c1_fck = { | |
b92c170d | 1572 | .name = "i2c1_fck", |
b36ee724 | 1573 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1574 | .parent = &func_12m_ck, |
d1b03f61 | 1575 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1577 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1578 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1579 | }; |
1580 | ||
6ae690da PW |
1581 | /* |
1582 | * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE | |
1583 | * accesses derived from this data. | |
1584 | */ | |
e32744b0 PW |
1585 | static struct clk gpmc_fck = { |
1586 | .name = "gpmc_fck", | |
6ae690da | 1587 | .ops = &clkops_omap2_iclk_idle_only, |
e32744b0 | 1588 | .parent = &core_l3_ck, |
8ad8ff65 | 1589 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1590 | .clkdm_name = "core_l3_clkdm", |
6ae690da PW |
1591 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1592 | .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, | |
e32744b0 PW |
1593 | .recalc = &followparent_recalc, |
1594 | }; | |
1595 | ||
1596 | static struct clk sdma_fck = { | |
1597 | .name = "sdma_fck", | |
897dcded | 1598 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1599 | .parent = &core_l3_ck, |
d1b03f61 | 1600 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1601 | .recalc = &followparent_recalc, |
1602 | }; | |
1603 | ||
6ae690da PW |
1604 | /* |
1605 | * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE | |
1606 | * accesses derived from this data. | |
1607 | */ | |
e32744b0 PW |
1608 | static struct clk sdma_ick = { |
1609 | .name = "sdma_ick", | |
6ae690da | 1610 | .ops = &clkops_omap2_iclk_idle_only, |
a1fed577 | 1611 | .parent = &core_l3_ck, |
d1b03f61 | 1612 | .clkdm_name = "core_l3_clkdm", |
6ae690da PW |
1613 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1614 | .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, | |
e32744b0 | 1615 | .recalc = &followparent_recalc, |
046d6b28 TL |
1616 | }; |
1617 | ||
a56d9ea8 PW |
1618 | /* |
1619 | * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE | |
1620 | * accesses derived from this data. | |
1621 | */ | |
1622 | static struct clk sdrc_ick = { | |
1623 | .name = "sdrc_ick", | |
1624 | .ops = &clkops_omap2_iclk_idle_only, | |
1625 | .parent = &core_l3_ck, | |
1626 | .flags = ENABLE_ON_INIT, | |
1627 | .clkdm_name = "core_l3_clkdm", | |
1628 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1629 | .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, | |
1630 | .recalc = &followparent_recalc, | |
1631 | }; | |
1632 | ||
046d6b28 TL |
1633 | static struct clk vlynq_ick = { |
1634 | .name = "vlynq_ick", | |
6ae690da | 1635 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1636 | .parent = &core_l3_ck, |
d1b03f61 | 1637 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1638 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1639 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1640 | .recalc = &followparent_recalc, | |
1641 | }; | |
1642 | ||
1643 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | |
d74b4949 | 1644 | { .div = 1, .val = 0, .flags = RATE_IN_242X }, |
e32744b0 PW |
1645 | { .div = 0 } |
1646 | }; | |
1647 | ||
1648 | static const struct clksel_rate vlynq_fck_core_rates[] = { | |
1649 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | |
1650 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
1651 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | |
1652 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
1653 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
1654 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
1655 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | |
1656 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
d74b4949 | 1657 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, |
e32744b0 PW |
1658 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, |
1659 | { .div = 0 } | |
1660 | }; | |
1661 | ||
1662 | static const struct clksel vlynq_fck_clksel[] = { | |
1663 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | |
1664 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | |
1665 | { .parent = NULL } | |
046d6b28 TL |
1666 | }; |
1667 | ||
1668 | static struct clk vlynq_fck = { | |
1669 | .name = "vlynq_fck", | |
b36ee724 | 1670 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1671 | .parent = &func_96m_ck, |
d1b03f61 | 1672 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1673 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1674 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1675 | .init = &omap2_init_clksel_parent, | |
1676 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
1677 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | |
1678 | .clksel = vlynq_fck_clksel, | |
1679 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1680 | }; |
1681 | ||
046d6b28 TL |
1682 | static struct clk des_ick = { |
1683 | .name = "des_ick", | |
6ae690da | 1684 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1685 | .parent = &l4_ck, |
d1b03f61 | 1686 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1687 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1688 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
1689 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1690 | }; |
1691 | ||
1692 | static struct clk sha_ick = { | |
1693 | .name = "sha_ick", | |
6ae690da | 1694 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1695 | .parent = &l4_ck, |
d1b03f61 | 1696 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1697 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1698 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1699 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1700 | }; |
1701 | ||
1702 | static struct clk rng_ick = { | |
1703 | .name = "rng_ick", | |
6ae690da | 1704 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1705 | .parent = &l4_ck, |
d1b03f61 | 1706 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1707 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1708 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1709 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1710 | }; |
1711 | ||
1712 | static struct clk aes_ick = { | |
1713 | .name = "aes_ick", | |
6ae690da | 1714 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1715 | .parent = &l4_ck, |
d1b03f61 | 1716 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1718 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
1719 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1720 | }; |
1721 | ||
1722 | static struct clk pka_ick = { | |
1723 | .name = "pka_ick", | |
6ae690da | 1724 | .ops = &clkops_omap2_iclk_dflt_wait, |
046d6b28 | 1725 | .parent = &l4_ck, |
d1b03f61 | 1726 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1728 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1729 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1730 | }; |
1731 | ||
1732 | static struct clk usb_fck = { | |
1733 | .name = "usb_fck", | |
b36ee724 | 1734 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1735 | .parent = &func_48m_ck, |
d1b03f61 | 1736 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1738 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1739 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1740 | }; |
1741 | ||
046d6b28 TL |
1742 | /* |
1743 | * This clock is a composite clock which does entire set changes then | |
1744 | * forces a rebalance. It keys on the MPU speed, but it really could | |
1745 | * be any key speed part of a set in the rate table. | |
1746 | * | |
1747 | * to really change a set, you need memory table sets which get changed | |
1748 | * in sram, pre-notifiers & post notifiers, changing the top set, without | |
1749 | * having low level display recalc's won't work... this is why dpm notifiers | |
1750 | * work, isr's off, walk a list of clocks already _off_ and not messing with | |
1751 | * the bus. | |
1752 | * | |
1753 | * This clock should have no parent. It embodies the entire upper level | |
1754 | * active set. A parent will mess up some of the init also. | |
1755 | */ | |
1756 | static struct clk virt_prcm_set = { | |
1757 | .name = "virt_prcm_set", | |
897dcded | 1758 | .ops = &clkops_null, |
046d6b28 | 1759 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
e32744b0 | 1760 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
046d6b28 TL |
1761 | .set_rate = &omap2_select_table_rate, |
1762 | .round_rate = &omap2_round_to_table_rate, | |
1763 | }; | |
e32744b0 | 1764 | |
d8a94458 PW |
1765 | |
1766 | /* | |
1767 | * clkdev integration | |
1768 | */ | |
1769 | ||
81b34fbe | 1770 | static struct omap_clk omap2420_clks[] = { |
d8a94458 | 1771 | /* external root sources */ |
81b34fbe PW |
1772 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), |
1773 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), | |
1774 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | |
1775 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | |
1776 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | |
1bccb345 | 1777 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), |
d8a94458 | 1778 | /* internal analog sources */ |
81b34fbe PW |
1779 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
1780 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), | |
1781 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), | |
d8a94458 | 1782 | /* internal prcm root sources */ |
81b34fbe PW |
1783 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
1784 | CLK(NULL, "core_ck", &core_ck, CK_242X), | |
1785 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | |
1786 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | |
1787 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | |
1788 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), | |
1789 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), | |
1790 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), | |
d8a94458 PW |
1791 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), |
1792 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | |
1793 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | |
1794 | /* mpu domain clocks */ | |
81b34fbe | 1795 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), |
d8a94458 | 1796 | /* dsp domain clocks */ |
81b34fbe | 1797 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), |
d8a94458 | 1798 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), |
d8a94458 PW |
1799 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), |
1800 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | |
1801 | /* GFX domain clocks */ | |
81b34fbe PW |
1802 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), |
1803 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), | |
1804 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), | |
d8a94458 | 1805 | /* DSS domain clocks */ |
8b9cb3a8 | 1806 | CLK("omapdss_dss", "ick", &dss_ick, CK_242X), |
6ea74cb9 | 1807 | CLK(NULL, "dss_ick", &dss_ick, CK_242X), |
bf1e0776 BC |
1808 | CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), |
1809 | CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), | |
1810 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), | |
d8a94458 | 1811 | /* L3 domain clocks */ |
81b34fbe PW |
1812 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), |
1813 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), | |
1814 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), | |
d8a94458 | 1815 | /* L4 domain clocks */ |
81b34fbe PW |
1816 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), |
1817 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), | |
19c1c0ce | 1818 | CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), |
d8a94458 | 1819 | /* virtual meta-group clock */ |
81b34fbe | 1820 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), |
d8a94458 | 1821 | /* general l4 interface ck, multi-parent functional clk */ |
81b34fbe PW |
1822 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), |
1823 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), | |
1824 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), | |
1825 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), | |
1826 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), | |
1827 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), | |
1828 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), | |
1829 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), | |
1830 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), | |
1831 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), | |
1832 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), | |
1833 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), | |
1834 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), | |
1835 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), | |
1836 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), | |
1837 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), | |
1838 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), | |
1839 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), | |
1840 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), | |
1841 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), | |
1842 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), | |
1843 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), | |
1844 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), | |
1845 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), | |
1846 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), | |
6ea74cb9 | 1847 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), |
bf1e0776 | 1848 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), |
81b34fbe | 1849 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), |
6ea74cb9 | 1850 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), |
bf1e0776 | 1851 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), |
81b34fbe | 1852 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), |
6ea74cb9 | 1853 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), |
bf1e0776 | 1854 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), |
81b34fbe | 1855 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), |
6ea74cb9 | 1856 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), |
bf1e0776 | 1857 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), |
81b34fbe PW |
1858 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), |
1859 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), | |
1860 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), | |
1861 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), | |
1862 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), | |
1863 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), | |
1864 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), | |
1865 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), | |
1866 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), | |
6ea74cb9 | 1867 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), |
bf1e0776 | 1868 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), |
81b34fbe PW |
1869 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), |
1870 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), | |
1871 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), | |
1872 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), | |
6ea74cb9 | 1873 | CLK(NULL, "cam_fck", &cam_fck, CK_242X), |
81b34fbe | 1874 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), |
6ea74cb9 | 1875 | CLK(NULL, "cam_ick", &cam_ick, CK_242X), |
81b34fbe PW |
1876 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), |
1877 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), | |
1878 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), | |
d8a94458 PW |
1879 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), |
1880 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | |
81b34fbe PW |
1881 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), |
1882 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), | |
d8a94458 | 1883 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
6ea74cb9 | 1884 | CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), |
d8a94458 | 1885 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), |
6ea74cb9 | 1886 | CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), |
81b34fbe PW |
1887 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), |
1888 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), | |
d8a94458 PW |
1889 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), |
1890 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | |
81b34fbe | 1891 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), |
6ea74cb9 | 1892 | CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), |
bf1e0776 | 1893 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), |
6ea74cb9 | 1894 | CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), |
f7bb0d9a | 1895 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), |
6ea74cb9 | 1896 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), |
bf1e0776 | 1897 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), |
f7bb0d9a | 1898 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), |
6ea74cb9 | 1899 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), |
bf1e0776 | 1900 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), |
81b34fbe PW |
1901 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), |
1902 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | |
1903 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | |
a56d9ea8 | 1904 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), |
d8a94458 PW |
1905 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), |
1906 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | |
81b34fbe | 1907 | CLK(NULL, "des_ick", &des_ick, CK_242X), |
ee5500c4 | 1908 | CLK("omap-sham", "ick", &sha_ick, CK_242X), |
6ea74cb9 | 1909 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), |
81b34fbe | 1910 | CLK("omap_rng", "ick", &rng_ick, CK_242X), |
6ea74cb9 | 1911 | CLK(NULL, "rng_ick", &rng_ick, CK_242X), |
82a0c149 | 1912 | CLK("omap-aes", "ick", &aes_ick, CK_242X), |
6ea74cb9 | 1913 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), |
81b34fbe PW |
1914 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), |
1915 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | |
05ac10dd | 1916 | CLK("musb-hdrc", "fck", &osc_ck, CK_242X), |
f84c3782 JH |
1917 | CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), |
1918 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), | |
1919 | CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), | |
c810fde2 | 1920 | CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), |
d8a94458 PW |
1921 | }; |
1922 | ||
1923 | /* | |
1924 | * init code | |
1925 | */ | |
1926 | ||
81b34fbe | 1927 | int __init omap2420_clk_init(void) |
d8a94458 PW |
1928 | { |
1929 | const struct prcm_config *prcm; | |
1930 | struct omap_clk *c; | |
1931 | u32 clkrate; | |
81b34fbe PW |
1932 | |
1933 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | |
1934 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | |
1935 | cpu_mask = RATE_IN_242X; | |
1936 | rate_table = omap2420_rate_table; | |
d8a94458 PW |
1937 | |
1938 | clk_init(&omap2_clk_functions); | |
1939 | ||
81b34fbe PW |
1940 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
1941 | c++) | |
d8a94458 PW |
1942 | clk_preinit(c->lk.clk); |
1943 | ||
1944 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | |
1945 | propagate_rate(&osc_ck); | |
44da0a51 | 1946 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
d8a94458 PW |
1947 | propagate_rate(&sys_ck); |
1948 | ||
81b34fbe PW |
1949 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
1950 | c++) { | |
1951 | clkdev_add(&c->lk); | |
1952 | clk_register(c->lk.clk); | |
1953 | omap2_init_clk_clkdm(c->lk.clk); | |
1954 | } | |
d8a94458 | 1955 | |
c6461f5c PW |
1956 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
1957 | omap_clk_disable_autoidle_all(); | |
1958 | ||
d8a94458 PW |
1959 | /* Check the MPU rate set by bootloader */ |
1960 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | |
1961 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
1962 | if (!(prcm->flags & cpu_mask)) | |
1963 | continue; | |
1964 | if (prcm->xtal_speed != sys_ck.rate) | |
1965 | continue; | |
1966 | if (prcm->dpll_speed <= clkrate) | |
1967 | break; | |
1968 | } | |
1969 | curr_prcm_set = prcm; | |
1970 | ||
1971 | recalculate_root_clocks(); | |
1972 | ||
81b34fbe PW |
1973 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
1974 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
1975 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
d8a94458 PW |
1976 | |
1977 | /* | |
1978 | * Only enable those clocks we will need, let the drivers | |
1979 | * enable other clocks as necessary | |
1980 | */ | |
1981 | clk_enable_init_clocks(); | |
1982 | ||
1983 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | |
1984 | vclk = clk_get(NULL, "virt_prcm_set"); | |
1985 | sclk = clk_get(NULL, "sys_ck"); | |
1986 | dclk = clk_get(NULL, "dpll_ck"); | |
1987 | ||
1988 | return 0; | |
1989 | } | |
6b8858a9 | 1990 |