Commit | Line | Data |
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046d6b28 | 1 | /* |
81b34fbe | 2 | * linux/arch/arm/mach-omap2/clock2430_data.c |
046d6b28 | 3 | * |
d8a94458 | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
93340a22 | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
046d6b28 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 TL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
d8a94458 PW |
16 | #include <linux/kernel.h> |
17 | #include <linux/clk.h> | |
93340a22 | 18 | #include <linux/list.h> |
046d6b28 | 19 | |
d8a94458 | 20 | #include <plat/clkdev_omap.h> |
6b8858a9 | 21 | |
d8a94458 PW |
22 | #include "clock.h" |
23 | #include "clock2xxx.h" | |
24 | #include "opp2xxx.h" | |
6b8858a9 PW |
25 | #include "prm.h" |
26 | #include "cm.h" | |
27 | #include "prm-regbits-24xx.h" | |
28 | #include "cm-regbits-24xx.h" | |
29 | #include "sdrc.h" | |
30 | ||
81b34fbe PW |
31 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR |
32 | ||
33 | /* | |
34 | * 2430 clock tree. | |
046d6b28 TL |
35 | * |
36 | * NOTE:In many cases here we are assigning a 'default' parent. In many | |
37 | * cases the parent is selectable. The get/set parent calls will also | |
38 | * switch sources. | |
39 | * | |
40 | * Many some clocks say always_enabled, but they can be auto idled for | |
41 | * power savings. They will always be available upon clock request. | |
42 | * | |
43 | * Several sources are given initial rates which may be wrong, this will | |
44 | * be fixed up in the init func. | |
45 | * | |
46 | * Things are broadly separated below by clock domains. It is | |
47 | * noteworthy that most periferals have dependencies on multiple clock | |
48 | * domains. Many get their interface clocks from the L4 domain, but get | |
49 | * functional clocks from fixed sources or other core domain derived | |
50 | * clocks. | |
81b34fbe | 51 | */ |
046d6b28 TL |
52 | |
53 | /* Base external input clocks */ | |
54 | static struct clk func_32k_ck = { | |
55 | .name = "func_32k_ck", | |
897dcded | 56 | .ops = &clkops_null, |
046d6b28 | 57 | .rate = 32000, |
d1b03f61 | 58 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 59 | }; |
e32744b0 | 60 | |
f248076c PW |
61 | static struct clk secure_32k_ck = { |
62 | .name = "secure_32k_ck", | |
63 | .ops = &clkops_null, | |
64 | .rate = 32768, | |
f248076c PW |
65 | .clkdm_name = "wkup_clkdm", |
66 | }; | |
67 | ||
046d6b28 TL |
68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |
70 | .name = "osc_ck", | |
548d8495 | 71 | .ops = &clkops_oscck, |
d1b03f61 | 72 | .clkdm_name = "wkup_clkdm", |
e32744b0 | 73 | .recalc = &omap2_osc_clk_recalc, |
046d6b28 TL |
74 | }; |
75 | ||
d1b03f61 | 76 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
046d6b28 TL |
77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
78 | .name = "sys_ck", /* ~ ref_clk also */ | |
897dcded | 79 | .ops = &clkops_null, |
046d6b28 | 80 | .parent = &osc_ck, |
d1b03f61 | 81 | .clkdm_name = "wkup_clkdm", |
44da0a51 | 82 | .recalc = &omap2xxx_sys_clk_recalc, |
046d6b28 | 83 | }; |
e32744b0 | 84 | |
046d6b28 TL |
85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
86 | .name = "alt_ck", | |
897dcded | 87 | .ops = &clkops_null, |
046d6b28 | 88 | .rate = 54000000, |
d1b03f61 | 89 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 90 | }; |
e32744b0 | 91 | |
046d6b28 TL |
92 | /* |
93 | * Analog domain root source clocks | |
94 | */ | |
95 | ||
96 | /* dpll_ck, is broken out in to special cases through clksel */ | |
6b8858a9 PW |
97 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
98 | * deal with this | |
99 | */ | |
100 | ||
88b8ba90 | 101 | static struct dpll_data dpll_dd = { |
6b8858a9 PW |
102 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
103 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
104 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
c0bf3132 RK |
105 | .clk_bypass = &sys_ck, |
106 | .clk_ref = &sys_ck, | |
107 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
108 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
93340a22 | 109 | .max_multiplier = 1023, |
95f538ac | 110 | .min_divider = 1, |
88b8ba90 PW |
111 | .max_divider = 16, |
112 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
6b8858a9 PW |
113 | }; |
114 | ||
88b8ba90 PW |
115 | /* |
116 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | |
117 | * not just a DPLL | |
118 | */ | |
046d6b28 TL |
119 | static struct clk dpll_ck = { |
120 | .name = "dpll_ck", | |
897dcded | 121 | .ops = &clkops_null, |
046d6b28 | 122 | .parent = &sys_ck, /* Can be func_32k also */ |
6b8858a9 | 123 | .dpll_data = &dpll_dd, |
d1b03f61 | 124 | .clkdm_name = "wkup_clkdm", |
88b8ba90 PW |
125 | .recalc = &omap2_dpllcore_recalc, |
126 | .set_rate = &omap2_reprogram_dpllcore, | |
046d6b28 TL |
127 | }; |
128 | ||
129 | static struct clk apll96_ck = { | |
130 | .name = "apll96_ck", | |
06b16939 | 131 | .ops = &clkops_apll96, |
046d6b28 TL |
132 | .parent = &sys_ck, |
133 | .rate = 96000000, | |
51c19541 | 134 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 135 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
136 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
137 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
046d6b28 TL |
138 | }; |
139 | ||
140 | static struct clk apll54_ck = { | |
141 | .name = "apll54_ck", | |
06b16939 | 142 | .ops = &clkops_apll54, |
046d6b28 TL |
143 | .parent = &sys_ck, |
144 | .rate = 54000000, | |
51c19541 | 145 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 146 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
147 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
148 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
046d6b28 TL |
149 | }; |
150 | ||
151 | /* | |
152 | * PRCM digital base sources | |
153 | */ | |
e32744b0 PW |
154 | |
155 | /* func_54m_ck */ | |
156 | ||
157 | static const struct clksel_rate func_54m_apll54_rates[] = { | |
d74b4949 | 158 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
159 | { .div = 0 }, |
160 | }; | |
161 | ||
162 | static const struct clksel_rate func_54m_alt_rates[] = { | |
d74b4949 | 163 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
164 | { .div = 0 }, |
165 | }; | |
166 | ||
167 | static const struct clksel func_54m_clksel[] = { | |
168 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | |
169 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | |
170 | { .parent = NULL }, | |
171 | }; | |
172 | ||
046d6b28 TL |
173 | static struct clk func_54m_ck = { |
174 | .name = "func_54m_ck", | |
57137181 | 175 | .ops = &clkops_null, |
046d6b28 | 176 | .parent = &apll54_ck, /* can also be alt_clk */ |
d1b03f61 | 177 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
178 | .init = &omap2_init_clksel_parent, |
179 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 180 | .clksel_mask = OMAP24XX_54M_SOURCE_MASK, |
e32744b0 PW |
181 | .clksel = func_54m_clksel, |
182 | .recalc = &omap2_clksel_recalc, | |
046d6b28 | 183 | }; |
e32744b0 | 184 | |
046d6b28 TL |
185 | static struct clk core_ck = { |
186 | .name = "core_ck", | |
897dcded | 187 | .ops = &clkops_null, |
046d6b28 | 188 | .parent = &dpll_ck, /* can also be 32k */ |
d1b03f61 | 189 | .clkdm_name = "wkup_clkdm", |
6b8858a9 | 190 | .recalc = &followparent_recalc, |
046d6b28 | 191 | }; |
e32744b0 PW |
192 | |
193 | /* func_96m_ck */ | |
194 | static const struct clksel_rate func_96m_apll96_rates[] = { | |
d74b4949 | 195 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 | 196 | { .div = 0 }, |
046d6b28 TL |
197 | }; |
198 | ||
e32744b0 | 199 | static const struct clksel_rate func_96m_alt_rates[] = { |
d74b4949 | 200 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, |
e32744b0 PW |
201 | { .div = 0 }, |
202 | }; | |
203 | ||
204 | static const struct clksel func_96m_clksel[] = { | |
205 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, | |
206 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, | |
207 | { .parent = NULL } | |
208 | }; | |
209 | ||
046d6b28 TL |
210 | static struct clk func_96m_ck = { |
211 | .name = "func_96m_ck", | |
57137181 | 212 | .ops = &clkops_null, |
046d6b28 | 213 | .parent = &apll96_ck, |
d1b03f61 | 214 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
215 | .init = &omap2_init_clksel_parent, |
216 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 217 | .clksel_mask = OMAP2430_96M_SOURCE_MASK, |
e32744b0 PW |
218 | .clksel = func_96m_clksel, |
219 | .recalc = &omap2_clksel_recalc, | |
e32744b0 PW |
220 | }; |
221 | ||
222 | /* func_48m_ck */ | |
223 | ||
224 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
d74b4949 | 225 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
226 | { .div = 0 }, |
227 | }; | |
228 | ||
229 | static const struct clksel_rate func_48m_alt_rates[] = { | |
d74b4949 | 230 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
231 | { .div = 0 }, |
232 | }; | |
233 | ||
234 | static const struct clksel func_48m_clksel[] = { | |
235 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
236 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
237 | { .parent = NULL } | |
046d6b28 TL |
238 | }; |
239 | ||
240 | static struct clk func_48m_ck = { | |
241 | .name = "func_48m_ck", | |
57137181 | 242 | .ops = &clkops_null, |
046d6b28 | 243 | .parent = &apll96_ck, /* 96M or Alt */ |
d1b03f61 | 244 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
245 | .init = &omap2_init_clksel_parent, |
246 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 247 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, |
e32744b0 PW |
248 | .clksel = func_48m_clksel, |
249 | .recalc = &omap2_clksel_recalc, | |
250 | .round_rate = &omap2_clksel_round_rate, | |
251 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
252 | }; |
253 | ||
254 | static struct clk func_12m_ck = { | |
255 | .name = "func_12m_ck", | |
57137181 | 256 | .ops = &clkops_null, |
046d6b28 | 257 | .parent = &func_48m_ck, |
e32744b0 | 258 | .fixed_div = 4, |
d1b03f61 | 259 | .clkdm_name = "wkup_clkdm", |
e9b98f60 | 260 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
261 | }; |
262 | ||
263 | /* Secure timer, only available in secure mode */ | |
264 | static struct clk wdt1_osc_ck = { | |
265 | .name = "ck_wdt1_osc", | |
897dcded | 266 | .ops = &clkops_null, /* RMK: missing? */ |
046d6b28 | 267 | .parent = &osc_ck, |
e32744b0 PW |
268 | .recalc = &followparent_recalc, |
269 | }; | |
270 | ||
271 | /* | |
272 | * The common_clkout* clksel_rate structs are common to | |
273 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | |
274 | * sys_clkout2_* are 2420-only, so the | |
275 | * clksel_rate flags fields are inaccurate for those clocks. This is | |
276 | * harmless since access to those clocks are gated by the struct clk | |
277 | * flags fields, which mark them as 2420-only. | |
278 | */ | |
279 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
d74b4949 | 280 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
281 | { .div = 0 } |
282 | }; | |
283 | ||
284 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
d74b4949 | 285 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
286 | { .div = 0 } |
287 | }; | |
288 | ||
289 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
d74b4949 | 290 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
291 | { .div = 0 } |
292 | }; | |
293 | ||
294 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
d74b4949 | 295 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, |
e32744b0 PW |
296 | { .div = 0 } |
297 | }; | |
298 | ||
299 | static const struct clksel common_clkout_src_clksel[] = { | |
300 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
301 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
302 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
303 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
304 | { .parent = NULL } | |
305 | }; | |
306 | ||
307 | static struct clk sys_clkout_src = { | |
308 | .name = "sys_clkout_src", | |
c1168dc3 | 309 | .ops = &clkops_omap2_dflt, |
e32744b0 | 310 | .parent = &func_54m_ck, |
d1b03f61 | 311 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 312 | .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
313 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
314 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 315 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
316 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
317 | .clksel = common_clkout_src_clksel, | |
318 | .recalc = &omap2_clksel_recalc, | |
319 | .round_rate = &omap2_clksel_round_rate, | |
320 | .set_rate = &omap2_clksel_set_rate | |
321 | }; | |
322 | ||
323 | static const struct clksel_rate common_clkout_rates[] = { | |
d74b4949 | 324 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
325 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
326 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | |
327 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | |
328 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | |
329 | { .div = 0 }, | |
330 | }; | |
331 | ||
332 | static const struct clksel sys_clkout_clksel[] = { | |
333 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | |
334 | { .parent = NULL } | |
046d6b28 TL |
335 | }; |
336 | ||
337 | static struct clk sys_clkout = { | |
338 | .name = "sys_clkout", | |
57137181 | 339 | .ops = &clkops_null, |
e32744b0 | 340 | .parent = &sys_clkout_src, |
d1b03f61 | 341 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 342 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
343 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
344 | .clksel = sys_clkout_clksel, | |
345 | .recalc = &omap2_clksel_recalc, | |
346 | .round_rate = &omap2_clksel_round_rate, | |
347 | .set_rate = &omap2_clksel_set_rate | |
348 | }; | |
349 | ||
b824efae TL |
350 | static struct clk emul_ck = { |
351 | .name = "emul_ck", | |
c1168dc3 | 352 | .ops = &clkops_omap2_dflt, |
b824efae | 353 | .parent = &func_54m_ck, |
d1b03f61 | 354 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 355 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, |
e32744b0 PW |
356 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
357 | .recalc = &followparent_recalc, | |
b824efae TL |
358 | |
359 | }; | |
e32744b0 | 360 | |
046d6b28 TL |
361 | /* |
362 | * MPU clock domain | |
363 | * Clocks: | |
364 | * MPU_FCLK, MPU_ICLK | |
365 | * INT_M_FCLK, INT_M_I_CLK | |
366 | * | |
367 | * - Individual clocks are hardware managed. | |
368 | * - Base divider comes from: CM_CLKSEL_MPU | |
369 | * | |
370 | */ | |
e32744b0 | 371 | static const struct clksel_rate mpu_core_rates[] = { |
d74b4949 | 372 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 | 373 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
374 | { .div = 0 }, |
375 | }; | |
376 | ||
377 | static const struct clksel mpu_clksel[] = { | |
378 | { .parent = &core_ck, .rates = mpu_core_rates }, | |
379 | { .parent = NULL } | |
380 | }; | |
381 | ||
046d6b28 TL |
382 | static struct clk mpu_ck = { /* Control cpu */ |
383 | .name = "mpu_ck", | |
897dcded | 384 | .ops = &clkops_null, |
046d6b28 | 385 | .parent = &core_ck, |
d1b03f61 | 386 | .clkdm_name = "mpu_clkdm", |
6b8858a9 PW |
387 | .init = &omap2_init_clksel_parent, |
388 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
389 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | |
e32744b0 | 390 | .clksel = mpu_clksel, |
046d6b28 TL |
391 | .recalc = &omap2_clksel_recalc, |
392 | }; | |
e32744b0 | 393 | |
046d6b28 | 394 | /* |
81b34fbe | 395 | * DSP (2430-IVA2.1) clock domain |
046d6b28 | 396 | * Clocks: |
e32744b0 | 397 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
e32744b0 PW |
398 | * |
399 | * Won't be too specific here. The core clock comes into this block | |
400 | * it is divided then tee'ed. One branch goes directly to xyz enable | |
401 | * controls. The other branch gets further divided by 2 then possibly | |
402 | * routed into a synchronizer and out of clocks abc. | |
046d6b28 | 403 | */ |
e32744b0 | 404 | static const struct clksel_rate dsp_fck_core_rates[] = { |
d74b4949 | 405 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
406 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
407 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
408 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
e32744b0 PW |
409 | { .div = 0 }, |
410 | }; | |
411 | ||
412 | static const struct clksel dsp_fck_clksel[] = { | |
413 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
414 | { .parent = NULL } | |
415 | }; | |
416 | ||
417 | static struct clk dsp_fck = { | |
418 | .name = "dsp_fck", | |
b36ee724 | 419 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 420 | .parent = &core_ck, |
d1b03f61 | 421 | .clkdm_name = "dsp_clkdm", |
e32744b0 PW |
422 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
423 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
424 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
425 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | |
426 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
427 | .recalc = &omap2_clksel_recalc, |
428 | }; | |
429 | ||
e32744b0 PW |
430 | /* DSP interface clock */ |
431 | static const struct clksel_rate dsp_irate_ick_rates[] = { | |
d74b4949 | 432 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
433 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
434 | { .div = 3, .val = 3, .flags = RATE_IN_243X }, | |
435 | { .div = 0 }, | |
436 | }; | |
437 | ||
438 | static const struct clksel dsp_irate_ick_clksel[] = { | |
439 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | |
440 | { .parent = NULL } | |
046d6b28 TL |
441 | }; |
442 | ||
d1b03f61 | 443 | /* This clock does not exist as such in the TRM. */ |
e32744b0 PW |
444 | static struct clk dsp_irate_ick = { |
445 | .name = "dsp_irate_ick", | |
57137181 | 446 | .ops = &clkops_null, |
e32744b0 | 447 | .parent = &dsp_fck, |
e32744b0 PW |
448 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
449 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | |
450 | .clksel = dsp_irate_ick_clksel, | |
046d6b28 TL |
451 | .recalc = &omap2_clksel_recalc, |
452 | }; | |
453 | ||
e32744b0 PW |
454 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
455 | static struct clk iva2_1_ick = { | |
456 | .name = "iva2_1_ick", | |
b36ee724 | 457 | .ops = &clkops_omap2_dflt_wait, |
e32744b0 | 458 | .parent = &dsp_irate_ick, |
e32744b0 PW |
459 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
460 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
046d6b28 TL |
461 | }; |
462 | ||
046d6b28 TL |
463 | /* |
464 | * L3 clock domain | |
465 | * L3 clocks are used for both interface and functional clocks to | |
466 | * multiple entities. Some of these clocks are completely managed | |
467 | * by hardware, and some others allow software control. Hardware | |
468 | * managed ones general are based on directly CLK_REQ signals and | |
469 | * various auto idle settings. The functional spec sets many of these | |
470 | * as 'tie-high' for their enables. | |
471 | * | |
472 | * I-CLOCKS: | |
473 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | |
474 | * CAM, HS-USB. | |
475 | * F-CLOCK | |
476 | * SSI. | |
477 | * | |
478 | * GPMC memories and SDRC have timing and clock sensitive registers which | |
479 | * may very well need notification when the clock changes. Currently for low | |
480 | * operating points, these are taken care of in sleep.S. | |
481 | */ | |
e32744b0 PW |
482 | static const struct clksel_rate core_l3_core_rates[] = { |
483 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 484 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
e32744b0 | 485 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
e32744b0 PW |
486 | { .div = 0 } |
487 | }; | |
488 | ||
489 | static const struct clksel core_l3_clksel[] = { | |
490 | { .parent = &core_ck, .rates = core_l3_core_rates }, | |
491 | { .parent = NULL } | |
492 | }; | |
493 | ||
046d6b28 TL |
494 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
495 | .name = "core_l3_ck", | |
897dcded | 496 | .ops = &clkops_null, |
046d6b28 | 497 | .parent = &core_ck, |
d1b03f61 | 498 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
499 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
500 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | |
501 | .clksel = core_l3_clksel, | |
046d6b28 | 502 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
503 | }; |
504 | ||
505 | /* usb_l4_ick */ | |
506 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
507 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 508 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
509 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
510 | { .div = 0 } | |
511 | }; | |
512 | ||
513 | static const struct clksel usb_l4_ick_clksel[] = { | |
514 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
515 | { .parent = NULL }, | |
046d6b28 TL |
516 | }; |
517 | ||
d1b03f61 | 518 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
046d6b28 TL |
519 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
520 | .name = "usb_l4_ick", | |
b36ee724 | 521 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 522 | .parent = &core_l3_ck, |
d1b03f61 | 523 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
524 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
525 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
526 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
527 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | |
528 | .clksel = usb_l4_ick_clksel, | |
046d6b28 TL |
529 | .recalc = &omap2_clksel_recalc, |
530 | }; | |
531 | ||
d1b03f61 PW |
532 | /* |
533 | * L4 clock management domain | |
534 | * | |
535 | * This domain contains lots of interface clocks from the L4 interface, some | |
536 | * functional clocks. Fixed APLL functional source clocks are managed in | |
537 | * this domain. | |
538 | */ | |
539 | static const struct clksel_rate l4_core_l3_rates[] = { | |
d74b4949 | 540 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
d1b03f61 PW |
541 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
542 | { .div = 0 } | |
543 | }; | |
544 | ||
545 | static const struct clksel l4_clksel[] = { | |
546 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | |
547 | { .parent = NULL } | |
548 | }; | |
549 | ||
550 | static struct clk l4_ck = { /* used both as an ick and fck */ | |
551 | .name = "l4_ck", | |
897dcded | 552 | .ops = &clkops_null, |
d1b03f61 | 553 | .parent = &core_l3_ck, |
d1b03f61 PW |
554 | .clkdm_name = "core_l4_clkdm", |
555 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
556 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | |
557 | .clksel = l4_clksel, | |
558 | .recalc = &omap2_clksel_recalc, | |
d1b03f61 PW |
559 | }; |
560 | ||
046d6b28 TL |
561 | /* |
562 | * SSI is in L3 management domain, its direct parent is core not l3, | |
563 | * many core power domain entities are grouped into the L3 clock | |
564 | * domain. | |
d1b03f61 | 565 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
046d6b28 TL |
566 | * |
567 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | |
568 | */ | |
e32744b0 PW |
569 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
570 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 571 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
572 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
573 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
574 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | |
e32744b0 PW |
575 | { .div = 0 } |
576 | }; | |
577 | ||
578 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
579 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
580 | { .parent = NULL } | |
581 | }; | |
582 | ||
046d6b28 TL |
583 | static struct clk ssi_ssr_sst_fck = { |
584 | .name = "ssi_fck", | |
b36ee724 | 585 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 586 | .parent = &core_ck, |
d1b03f61 | 587 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
588 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
589 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
590 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
591 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | |
592 | .clksel = ssi_ssr_sst_fck_clksel, | |
046d6b28 TL |
593 | .recalc = &omap2_clksel_recalc, |
594 | }; | |
595 | ||
9299fd85 PW |
596 | /* |
597 | * Presumably this is the same as SSI_ICLK. | |
598 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | |
599 | */ | |
600 | static struct clk ssi_l4_ick = { | |
601 | .name = "ssi_l4_ick", | |
602 | .ops = &clkops_omap2_dflt_wait, | |
603 | .parent = &l4_ck, | |
604 | .clkdm_name = "core_l4_clkdm", | |
605 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
606 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
607 | .recalc = &followparent_recalc, | |
608 | }; | |
609 | ||
d1b03f61 | 610 | |
046d6b28 TL |
611 | /* |
612 | * GFX clock domain | |
613 | * Clocks: | |
614 | * GFX_FCLK, GFX_ICLK | |
615 | * GFX_CG1(2d), GFX_CG2(3d) | |
616 | * | |
617 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | |
618 | * The 2d and 3d clocks run at a hardware determined | |
619 | * divided value of fclk. | |
620 | * | |
621 | */ | |
e32744b0 PW |
622 | |
623 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | |
624 | static const struct clksel gfx_fck_clksel[] = { | |
625 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
626 | { .parent = NULL }, | |
627 | }; | |
628 | ||
046d6b28 TL |
629 | static struct clk gfx_3d_fck = { |
630 | .name = "gfx_3d_fck", | |
b36ee724 | 631 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 632 | .parent = &core_l3_ck, |
d1b03f61 | 633 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
634 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
635 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | |
636 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
637 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
638 | .clksel = gfx_fck_clksel, | |
046d6b28 | 639 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
640 | .round_rate = &omap2_clksel_round_rate, |
641 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
642 | }; |
643 | ||
644 | static struct clk gfx_2d_fck = { | |
645 | .name = "gfx_2d_fck", | |
b36ee724 | 646 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 647 | .parent = &core_l3_ck, |
d1b03f61 | 648 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
649 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
650 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | |
651 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
652 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
653 | .clksel = gfx_fck_clksel, | |
046d6b28 TL |
654 | .recalc = &omap2_clksel_recalc, |
655 | }; | |
656 | ||
657 | static struct clk gfx_ick = { | |
658 | .name = "gfx_ick", /* From l3 */ | |
b36ee724 | 659 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 660 | .parent = &core_l3_ck, |
d1b03f61 | 661 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
662 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
663 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
664 | .recalc = &followparent_recalc, | |
046d6b28 TL |
665 | }; |
666 | ||
667 | /* | |
668 | * Modem clock domain (2430) | |
669 | * CLOCKS: | |
670 | * MDM_OSC_CLK | |
671 | * MDM_ICLK | |
e32744b0 | 672 | * These clocks are usable in chassis mode only. |
046d6b28 | 673 | */ |
e32744b0 PW |
674 | static const struct clksel_rate mdm_ick_core_rates[] = { |
675 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, | |
d74b4949 | 676 | { .div = 4, .val = 4, .flags = RATE_IN_243X }, |
e32744b0 PW |
677 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, |
678 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, | |
679 | { .div = 0 } | |
680 | }; | |
681 | ||
682 | static const struct clksel mdm_ick_clksel[] = { | |
683 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, | |
684 | { .parent = NULL } | |
685 | }; | |
686 | ||
046d6b28 TL |
687 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
688 | .name = "mdm_ick", | |
b36ee724 | 689 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 690 | .parent = &core_ck, |
d1b03f61 | 691 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
692 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
693 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | |
694 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | |
695 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | |
696 | .clksel = mdm_ick_clksel, | |
046d6b28 TL |
697 | .recalc = &omap2_clksel_recalc, |
698 | }; | |
699 | ||
700 | static struct clk mdm_osc_ck = { | |
701 | .name = "mdm_osc_ck", | |
b36ee724 | 702 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 703 | .parent = &osc_ck, |
d1b03f61 | 704 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
705 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
706 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | |
707 | .recalc = &followparent_recalc, | |
046d6b28 TL |
708 | }; |
709 | ||
046d6b28 TL |
710 | /* |
711 | * DSS clock domain | |
712 | * CLOCKs: | |
713 | * DSS_L4_ICLK, DSS_L3_ICLK, | |
714 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | |
715 | * | |
716 | * DSS is both initiator and target. | |
717 | */ | |
e32744b0 PW |
718 | /* XXX Add RATE_NOT_VALIDATED */ |
719 | ||
720 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
d74b4949 | 721 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
722 | { .div = 0 } |
723 | }; | |
724 | ||
725 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
726 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
727 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
728 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
729 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
730 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
731 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
732 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
733 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
734 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
d74b4949 | 735 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, |
e32744b0 PW |
736 | { .div = 0 } |
737 | }; | |
738 | ||
739 | static const struct clksel dss1_fck_clksel[] = { | |
740 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
741 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
742 | { .parent = NULL }, | |
743 | }; | |
744 | ||
046d6b28 TL |
745 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
746 | .name = "dss_ick", | |
bc51da4e | 747 | .ops = &clkops_omap2_dflt, |
046d6b28 | 748 | .parent = &l4_ck, /* really both l3 and l4 */ |
d1b03f61 | 749 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
750 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
751 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
752 | .recalc = &followparent_recalc, | |
046d6b28 TL |
753 | }; |
754 | ||
755 | static struct clk dss1_fck = { | |
756 | .name = "dss1_fck", | |
bc51da4e | 757 | .ops = &clkops_omap2_dflt, |
046d6b28 | 758 | .parent = &core_ck, /* Core or sys */ |
d1b03f61 | 759 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
760 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
761 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
762 | .init = &omap2_init_clksel_parent, | |
763 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
764 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | |
765 | .clksel = dss1_fck_clksel, | |
046d6b28 | 766 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
767 | }; |
768 | ||
769 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
d74b4949 | 770 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
771 | { .div = 0 } |
772 | }; | |
773 | ||
774 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
d74b4949 | 775 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
776 | { .div = 0 } |
777 | }; | |
778 | ||
779 | static const struct clksel dss2_fck_clksel[] = { | |
780 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
781 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
782 | { .parent = NULL } | |
046d6b28 TL |
783 | }; |
784 | ||
785 | static struct clk dss2_fck = { /* Alt clk used in power management */ | |
786 | .name = "dss2_fck", | |
bc51da4e | 787 | .ops = &clkops_omap2_dflt, |
046d6b28 | 788 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
d1b03f61 | 789 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
791 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | |
792 | .init = &omap2_init_clksel_parent, | |
793 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
794 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | |
795 | .clksel = dss2_fck_clksel, | |
796 | .recalc = &followparent_recalc, | |
046d6b28 TL |
797 | }; |
798 | ||
799 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |
800 | .name = "dss_54m_fck", /* 54m tv clk */ | |
b36ee724 | 801 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 802 | .parent = &func_54m_ck, |
d1b03f61 | 803 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
804 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
805 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
806 | .recalc = &followparent_recalc, | |
046d6b28 TL |
807 | }; |
808 | ||
809 | /* | |
810 | * CORE power domain ICLK & FCLK defines. | |
811 | * Many of the these can have more than one possible parent. Entries | |
812 | * here will likely have an L4 interface parent, and may have multiple | |
813 | * functional clock parents. | |
814 | */ | |
e32744b0 | 815 | static const struct clksel_rate gpt_alt_rates[] = { |
d74b4949 | 816 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
817 | { .div = 0 } |
818 | }; | |
819 | ||
820 | static const struct clksel omap24xx_gpt_clksel[] = { | |
821 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
822 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
823 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
824 | { .parent = NULL }, | |
825 | }; | |
826 | ||
046d6b28 TL |
827 | static struct clk gpt1_ick = { |
828 | .name = "gpt1_ick", | |
b36ee724 | 829 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 830 | .parent = &l4_ck, |
d1b03f61 | 831 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
832 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
833 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
834 | .recalc = &followparent_recalc, | |
046d6b28 TL |
835 | }; |
836 | ||
837 | static struct clk gpt1_fck = { | |
838 | .name = "gpt1_fck", | |
b36ee724 | 839 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 840 | .parent = &func_32k_ck, |
d1b03f61 | 841 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
842 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
843 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
844 | .init = &omap2_init_clksel_parent, | |
845 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
846 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | |
847 | .clksel = omap24xx_gpt_clksel, | |
848 | .recalc = &omap2_clksel_recalc, | |
849 | .round_rate = &omap2_clksel_round_rate, | |
850 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
851 | }; |
852 | ||
853 | static struct clk gpt2_ick = { | |
854 | .name = "gpt2_ick", | |
b36ee724 | 855 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 856 | .parent = &l4_ck, |
d1b03f61 | 857 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
859 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
860 | .recalc = &followparent_recalc, | |
046d6b28 TL |
861 | }; |
862 | ||
863 | static struct clk gpt2_fck = { | |
864 | .name = "gpt2_fck", | |
b36ee724 | 865 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 866 | .parent = &func_32k_ck, |
d1b03f61 | 867 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
868 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
869 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
870 | .init = &omap2_init_clksel_parent, | |
871 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
872 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | |
873 | .clksel = omap24xx_gpt_clksel, | |
874 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
875 | }; |
876 | ||
877 | static struct clk gpt3_ick = { | |
878 | .name = "gpt3_ick", | |
b36ee724 | 879 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 880 | .parent = &l4_ck, |
d1b03f61 | 881 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
882 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
883 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
884 | .recalc = &followparent_recalc, | |
046d6b28 TL |
885 | }; |
886 | ||
887 | static struct clk gpt3_fck = { | |
888 | .name = "gpt3_fck", | |
b36ee724 | 889 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 890 | .parent = &func_32k_ck, |
d1b03f61 | 891 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
892 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
893 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
894 | .init = &omap2_init_clksel_parent, | |
895 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
896 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | |
897 | .clksel = omap24xx_gpt_clksel, | |
898 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
899 | }; |
900 | ||
901 | static struct clk gpt4_ick = { | |
902 | .name = "gpt4_ick", | |
b36ee724 | 903 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 904 | .parent = &l4_ck, |
d1b03f61 | 905 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
906 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
907 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
908 | .recalc = &followparent_recalc, | |
046d6b28 TL |
909 | }; |
910 | ||
911 | static struct clk gpt4_fck = { | |
912 | .name = "gpt4_fck", | |
b36ee724 | 913 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 914 | .parent = &func_32k_ck, |
d1b03f61 | 915 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
916 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
917 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
918 | .init = &omap2_init_clksel_parent, | |
919 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
920 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | |
921 | .clksel = omap24xx_gpt_clksel, | |
922 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
923 | }; |
924 | ||
925 | static struct clk gpt5_ick = { | |
926 | .name = "gpt5_ick", | |
b36ee724 | 927 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 928 | .parent = &l4_ck, |
d1b03f61 | 929 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
930 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
931 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
932 | .recalc = &followparent_recalc, | |
046d6b28 TL |
933 | }; |
934 | ||
935 | static struct clk gpt5_fck = { | |
936 | .name = "gpt5_fck", | |
b36ee724 | 937 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 938 | .parent = &func_32k_ck, |
d1b03f61 | 939 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
941 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
942 | .init = &omap2_init_clksel_parent, | |
943 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
944 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | |
945 | .clksel = omap24xx_gpt_clksel, | |
946 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
947 | }; |
948 | ||
949 | static struct clk gpt6_ick = { | |
950 | .name = "gpt6_ick", | |
b36ee724 | 951 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 952 | .parent = &l4_ck, |
d1b03f61 | 953 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
954 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
955 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
956 | .recalc = &followparent_recalc, | |
046d6b28 TL |
957 | }; |
958 | ||
959 | static struct clk gpt6_fck = { | |
960 | .name = "gpt6_fck", | |
b36ee724 | 961 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 962 | .parent = &func_32k_ck, |
d1b03f61 | 963 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
964 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
965 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
966 | .init = &omap2_init_clksel_parent, | |
967 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
968 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | |
969 | .clksel = omap24xx_gpt_clksel, | |
970 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
971 | }; |
972 | ||
973 | static struct clk gpt7_ick = { | |
974 | .name = "gpt7_ick", | |
b36ee724 | 975 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 976 | .parent = &l4_ck, |
e32744b0 PW |
977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
978 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
979 | .recalc = &followparent_recalc, | |
046d6b28 TL |
980 | }; |
981 | ||
982 | static struct clk gpt7_fck = { | |
983 | .name = "gpt7_fck", | |
b36ee724 | 984 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 985 | .parent = &func_32k_ck, |
d1b03f61 | 986 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
988 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
989 | .init = &omap2_init_clksel_parent, | |
990 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
991 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | |
992 | .clksel = omap24xx_gpt_clksel, | |
993 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
994 | }; |
995 | ||
996 | static struct clk gpt8_ick = { | |
997 | .name = "gpt8_ick", | |
b36ee724 | 998 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 999 | .parent = &l4_ck, |
d1b03f61 | 1000 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1001 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1002 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1003 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1004 | }; |
1005 | ||
1006 | static struct clk gpt8_fck = { | |
1007 | .name = "gpt8_fck", | |
b36ee724 | 1008 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1009 | .parent = &func_32k_ck, |
d1b03f61 | 1010 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1011 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1012 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1013 | .init = &omap2_init_clksel_parent, | |
1014 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1015 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | |
1016 | .clksel = omap24xx_gpt_clksel, | |
1017 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1018 | }; |
1019 | ||
1020 | static struct clk gpt9_ick = { | |
1021 | .name = "gpt9_ick", | |
b36ee724 | 1022 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1023 | .parent = &l4_ck, |
d1b03f61 | 1024 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1026 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1027 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1028 | }; |
1029 | ||
1030 | static struct clk gpt9_fck = { | |
1031 | .name = "gpt9_fck", | |
b36ee724 | 1032 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1033 | .parent = &func_32k_ck, |
d1b03f61 | 1034 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1036 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1037 | .init = &omap2_init_clksel_parent, | |
1038 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1039 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | |
1040 | .clksel = omap24xx_gpt_clksel, | |
1041 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1042 | }; |
1043 | ||
1044 | static struct clk gpt10_ick = { | |
1045 | .name = "gpt10_ick", | |
b36ee724 | 1046 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1047 | .parent = &l4_ck, |
d1b03f61 | 1048 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1049 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1050 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1051 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1052 | }; |
1053 | ||
1054 | static struct clk gpt10_fck = { | |
1055 | .name = "gpt10_fck", | |
b36ee724 | 1056 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1057 | .parent = &func_32k_ck, |
d1b03f61 | 1058 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1059 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1060 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1061 | .init = &omap2_init_clksel_parent, | |
1062 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1063 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | |
1064 | .clksel = omap24xx_gpt_clksel, | |
1065 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1066 | }; |
1067 | ||
1068 | static struct clk gpt11_ick = { | |
1069 | .name = "gpt11_ick", | |
b36ee724 | 1070 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1071 | .parent = &l4_ck, |
d1b03f61 | 1072 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1073 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1074 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1075 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1076 | }; |
1077 | ||
1078 | static struct clk gpt11_fck = { | |
1079 | .name = "gpt11_fck", | |
b36ee724 | 1080 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1081 | .parent = &func_32k_ck, |
d1b03f61 | 1082 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1083 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1084 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1085 | .init = &omap2_init_clksel_parent, | |
1086 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1087 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | |
1088 | .clksel = omap24xx_gpt_clksel, | |
1089 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1090 | }; |
1091 | ||
1092 | static struct clk gpt12_ick = { | |
1093 | .name = "gpt12_ick", | |
b36ee724 | 1094 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1095 | .parent = &l4_ck, |
d1b03f61 | 1096 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1097 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1098 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1099 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1100 | }; |
1101 | ||
1102 | static struct clk gpt12_fck = { | |
1103 | .name = "gpt12_fck", | |
b36ee724 | 1104 | .ops = &clkops_omap2_dflt_wait, |
f248076c | 1105 | .parent = &secure_32k_ck, |
d1b03f61 | 1106 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1107 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1108 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1109 | .init = &omap2_init_clksel_parent, | |
1110 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1111 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | |
1112 | .clksel = omap24xx_gpt_clksel, | |
1113 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1114 | }; |
1115 | ||
1116 | static struct clk mcbsp1_ick = { | |
b92c170d | 1117 | .name = "mcbsp1_ick", |
b36ee724 | 1118 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1119 | .parent = &l4_ck, |
d1b03f61 | 1120 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1121 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1122 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1123 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1124 | }; |
1125 | ||
1126 | static struct clk mcbsp1_fck = { | |
b92c170d | 1127 | .name = "mcbsp1_fck", |
b36ee724 | 1128 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1129 | .parent = &func_96m_ck, |
d1b03f61 | 1130 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1132 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1133 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1134 | }; |
1135 | ||
1136 | static struct clk mcbsp2_ick = { | |
b92c170d | 1137 | .name = "mcbsp2_ick", |
b36ee724 | 1138 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1139 | .parent = &l4_ck, |
d1b03f61 | 1140 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1141 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1142 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1143 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1144 | }; |
1145 | ||
1146 | static struct clk mcbsp2_fck = { | |
b92c170d | 1147 | .name = "mcbsp2_fck", |
b36ee724 | 1148 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1149 | .parent = &func_96m_ck, |
d1b03f61 | 1150 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1151 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1152 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1153 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1154 | }; |
1155 | ||
1156 | static struct clk mcbsp3_ick = { | |
b92c170d | 1157 | .name = "mcbsp3_ick", |
b36ee724 | 1158 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1159 | .parent = &l4_ck, |
d1b03f61 | 1160 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1161 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1162 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1163 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1164 | }; |
1165 | ||
1166 | static struct clk mcbsp3_fck = { | |
b92c170d | 1167 | .name = "mcbsp3_fck", |
b36ee724 | 1168 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1169 | .parent = &func_96m_ck, |
d1b03f61 | 1170 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1171 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1172 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1173 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1174 | }; |
1175 | ||
1176 | static struct clk mcbsp4_ick = { | |
b92c170d | 1177 | .name = "mcbsp4_ick", |
b36ee724 | 1178 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1179 | .parent = &l4_ck, |
d1b03f61 | 1180 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1181 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1182 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1183 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1184 | }; |
1185 | ||
1186 | static struct clk mcbsp4_fck = { | |
b92c170d | 1187 | .name = "mcbsp4_fck", |
b36ee724 | 1188 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1189 | .parent = &func_96m_ck, |
d1b03f61 | 1190 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1191 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1192 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1193 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1194 | }; |
1195 | ||
1196 | static struct clk mcbsp5_ick = { | |
b92c170d | 1197 | .name = "mcbsp5_ick", |
b36ee724 | 1198 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1199 | .parent = &l4_ck, |
d1b03f61 | 1200 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1202 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1203 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1204 | }; |
1205 | ||
1206 | static struct clk mcbsp5_fck = { | |
b92c170d | 1207 | .name = "mcbsp5_fck", |
b36ee724 | 1208 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1209 | .parent = &func_96m_ck, |
d1b03f61 | 1210 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1212 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1213 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1214 | }; |
1215 | ||
1216 | static struct clk mcspi1_ick = { | |
b92c170d | 1217 | .name = "mcspi1_ick", |
b36ee724 | 1218 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1219 | .parent = &l4_ck, |
d1b03f61 | 1220 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1221 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1222 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1223 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1224 | }; |
1225 | ||
1226 | static struct clk mcspi1_fck = { | |
b92c170d | 1227 | .name = "mcspi1_fck", |
b36ee724 | 1228 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1229 | .parent = &func_48m_ck, |
d1b03f61 | 1230 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1231 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1232 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1233 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1234 | }; |
1235 | ||
1236 | static struct clk mcspi2_ick = { | |
b92c170d | 1237 | .name = "mcspi2_ick", |
b36ee724 | 1238 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1239 | .parent = &l4_ck, |
d1b03f61 | 1240 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1241 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1242 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1243 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1244 | }; |
1245 | ||
1246 | static struct clk mcspi2_fck = { | |
b92c170d | 1247 | .name = "mcspi2_fck", |
b36ee724 | 1248 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1249 | .parent = &func_48m_ck, |
d1b03f61 | 1250 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1252 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1253 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1254 | }; |
1255 | ||
1256 | static struct clk mcspi3_ick = { | |
b92c170d | 1257 | .name = "mcspi3_ick", |
b36ee724 | 1258 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1259 | .parent = &l4_ck, |
d1b03f61 | 1260 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1262 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1263 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1264 | }; |
1265 | ||
1266 | static struct clk mcspi3_fck = { | |
b92c170d | 1267 | .name = "mcspi3_fck", |
b36ee724 | 1268 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1269 | .parent = &func_48m_ck, |
d1b03f61 | 1270 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1272 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1273 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1274 | }; |
1275 | ||
1276 | static struct clk uart1_ick = { | |
1277 | .name = "uart1_ick", | |
b36ee724 | 1278 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1279 | .parent = &l4_ck, |
d1b03f61 | 1280 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1281 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1282 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1283 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1284 | }; |
1285 | ||
1286 | static struct clk uart1_fck = { | |
1287 | .name = "uart1_fck", | |
b36ee724 | 1288 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1289 | .parent = &func_48m_ck, |
d1b03f61 | 1290 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1291 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1292 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1293 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1294 | }; |
1295 | ||
1296 | static struct clk uart2_ick = { | |
1297 | .name = "uart2_ick", | |
b36ee724 | 1298 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1299 | .parent = &l4_ck, |
d1b03f61 | 1300 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1301 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1302 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1303 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1304 | }; |
1305 | ||
1306 | static struct clk uart2_fck = { | |
1307 | .name = "uart2_fck", | |
b36ee724 | 1308 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1309 | .parent = &func_48m_ck, |
d1b03f61 | 1310 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1311 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1312 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1313 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1314 | }; |
1315 | ||
1316 | static struct clk uart3_ick = { | |
1317 | .name = "uart3_ick", | |
b36ee724 | 1318 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1319 | .parent = &l4_ck, |
d1b03f61 | 1320 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1321 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1322 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1323 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1324 | }; |
1325 | ||
1326 | static struct clk uart3_fck = { | |
1327 | .name = "uart3_fck", | |
b36ee724 | 1328 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1329 | .parent = &func_48m_ck, |
d1b03f61 | 1330 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1331 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1332 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1333 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1334 | }; |
1335 | ||
1336 | static struct clk gpios_ick = { | |
1337 | .name = "gpios_ick", | |
b36ee724 | 1338 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1339 | .parent = &l4_ck, |
d1b03f61 | 1340 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1341 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1342 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1343 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1344 | }; |
1345 | ||
1346 | static struct clk gpios_fck = { | |
1347 | .name = "gpios_fck", | |
b36ee724 | 1348 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1349 | .parent = &func_32k_ck, |
d1b03f61 | 1350 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1351 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1352 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1353 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1354 | }; |
1355 | ||
1356 | static struct clk mpu_wdt_ick = { | |
1357 | .name = "mpu_wdt_ick", | |
b36ee724 | 1358 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1359 | .parent = &l4_ck, |
d1b03f61 | 1360 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1361 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1362 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1363 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1364 | }; |
1365 | ||
1366 | static struct clk mpu_wdt_fck = { | |
1367 | .name = "mpu_wdt_fck", | |
b36ee724 | 1368 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1369 | .parent = &func_32k_ck, |
d1b03f61 | 1370 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1371 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1372 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1373 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1374 | }; |
1375 | ||
1376 | static struct clk sync_32k_ick = { | |
1377 | .name = "sync_32k_ick", | |
b36ee724 | 1378 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1379 | .parent = &l4_ck, |
8ad8ff65 | 1380 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1381 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1382 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1383 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1384 | .recalc = &followparent_recalc, | |
046d6b28 | 1385 | }; |
d1b03f61 | 1386 | |
046d6b28 TL |
1387 | static struct clk wdt1_ick = { |
1388 | .name = "wdt1_ick", | |
b36ee724 | 1389 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1390 | .parent = &l4_ck, |
d1b03f61 | 1391 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1392 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1393 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1394 | .recalc = &followparent_recalc, | |
046d6b28 | 1395 | }; |
d1b03f61 | 1396 | |
046d6b28 TL |
1397 | static struct clk omapctrl_ick = { |
1398 | .name = "omapctrl_ick", | |
b36ee724 | 1399 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1400 | .parent = &l4_ck, |
8ad8ff65 | 1401 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1402 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1403 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1404 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1405 | .recalc = &followparent_recalc, | |
046d6b28 | 1406 | }; |
d1b03f61 | 1407 | |
046d6b28 TL |
1408 | static struct clk icr_ick = { |
1409 | .name = "icr_ick", | |
b36ee724 | 1410 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1411 | .parent = &l4_ck, |
d1b03f61 | 1412 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1413 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1414 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | |
1415 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1416 | }; |
1417 | ||
1418 | static struct clk cam_ick = { | |
1419 | .name = "cam_ick", | |
bc51da4e | 1420 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1421 | .parent = &l4_ck, |
d1b03f61 | 1422 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1423 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1424 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1425 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1426 | }; |
1427 | ||
d1b03f61 PW |
1428 | /* |
1429 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | |
1430 | * split into two separate clocks, since the parent clocks are different | |
1431 | * and the clockdomains are also different. | |
1432 | */ | |
046d6b28 TL |
1433 | static struct clk cam_fck = { |
1434 | .name = "cam_fck", | |
bc51da4e | 1435 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1436 | .parent = &func_96m_ck, |
d1b03f61 | 1437 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1439 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1440 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1441 | }; |
1442 | ||
1443 | static struct clk mailboxes_ick = { | |
1444 | .name = "mailboxes_ick", | |
b36ee724 | 1445 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1446 | .parent = &l4_ck, |
d1b03f61 | 1447 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1448 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1449 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1450 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1451 | }; |
1452 | ||
1453 | static struct clk wdt4_ick = { | |
1454 | .name = "wdt4_ick", | |
b36ee724 | 1455 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1456 | .parent = &l4_ck, |
d1b03f61 | 1457 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1458 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1459 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1460 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1461 | }; |
1462 | ||
1463 | static struct clk wdt4_fck = { | |
1464 | .name = "wdt4_fck", | |
b36ee724 | 1465 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1466 | .parent = &func_32k_ck, |
d1b03f61 | 1467 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1468 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1469 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1470 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1471 | }; |
1472 | ||
046d6b28 TL |
1473 | static struct clk mspro_ick = { |
1474 | .name = "mspro_ick", | |
b36ee724 | 1475 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1476 | .parent = &l4_ck, |
d1b03f61 | 1477 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1479 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1480 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1481 | }; |
1482 | ||
1483 | static struct clk mspro_fck = { | |
1484 | .name = "mspro_fck", | |
b36ee724 | 1485 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1486 | .parent = &func_96m_ck, |
d1b03f61 | 1487 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1489 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1490 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1491 | }; |
1492 | ||
046d6b28 TL |
1493 | static struct clk fac_ick = { |
1494 | .name = "fac_ick", | |
b36ee724 | 1495 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1496 | .parent = &l4_ck, |
d1b03f61 | 1497 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1498 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1499 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1500 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1501 | }; |
1502 | ||
1503 | static struct clk fac_fck = { | |
1504 | .name = "fac_fck", | |
b36ee724 | 1505 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1506 | .parent = &func_12m_ck, |
d1b03f61 | 1507 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1509 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1510 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1511 | }; |
1512 | ||
046d6b28 TL |
1513 | static struct clk hdq_ick = { |
1514 | .name = "hdq_ick", | |
b36ee724 | 1515 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1516 | .parent = &l4_ck, |
d1b03f61 | 1517 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1519 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1520 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1521 | }; |
1522 | ||
1523 | static struct clk hdq_fck = { | |
1524 | .name = "hdq_fck", | |
b36ee724 | 1525 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1526 | .parent = &func_12m_ck, |
d1b03f61 | 1527 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1528 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1529 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1530 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1531 | }; |
1532 | ||
81b34fbe PW |
1533 | /* |
1534 | * XXX This is marked as a 2420-only define, but it claims to be present | |
1535 | * on 2430 also. Double-check. | |
1536 | */ | |
046d6b28 | 1537 | static struct clk i2c2_ick = { |
b92c170d | 1538 | .name = "i2c2_ick", |
b36ee724 | 1539 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1540 | .parent = &l4_ck, |
d1b03f61 | 1541 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1543 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1544 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1545 | }; |
1546 | ||
046d6b28 | 1547 | static struct clk i2chs2_fck = { |
b92c170d | 1548 | .name = "i2chs2_fck", |
3dc21975 | 1549 | .ops = &clkops_omap2430_i2chs_wait, |
046d6b28 | 1550 | .parent = &func_96m_ck, |
d1b03f61 | 1551 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1552 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1553 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
1554 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1555 | }; |
1556 | ||
81b34fbe PW |
1557 | /* |
1558 | * XXX This is marked as a 2420-only define, but it claims to be present | |
1559 | * on 2430 also. Double-check. | |
1560 | */ | |
046d6b28 | 1561 | static struct clk i2c1_ick = { |
b92c170d | 1562 | .name = "i2c1_ick", |
b36ee724 | 1563 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1564 | .parent = &l4_ck, |
d1b03f61 | 1565 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1566 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1567 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1568 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1569 | }; |
1570 | ||
046d6b28 | 1571 | static struct clk i2chs1_fck = { |
b92c170d | 1572 | .name = "i2chs1_fck", |
3dc21975 | 1573 | .ops = &clkops_omap2430_i2chs_wait, |
046d6b28 | 1574 | .parent = &func_96m_ck, |
d1b03f61 | 1575 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1577 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
1578 | .recalc = &followparent_recalc, | |
1579 | }; | |
1580 | ||
1581 | static struct clk gpmc_fck = { | |
1582 | .name = "gpmc_fck", | |
897dcded | 1583 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1584 | .parent = &core_l3_ck, |
8ad8ff65 | 1585 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1586 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1587 | .recalc = &followparent_recalc, |
1588 | }; | |
1589 | ||
1590 | static struct clk sdma_fck = { | |
1591 | .name = "sdma_fck", | |
897dcded | 1592 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1593 | .parent = &core_l3_ck, |
d1b03f61 | 1594 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1595 | .recalc = &followparent_recalc, |
1596 | }; | |
1597 | ||
1598 | static struct clk sdma_ick = { | |
1599 | .name = "sdma_ick", | |
897dcded | 1600 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1601 | .parent = &l4_ck, |
d1b03f61 | 1602 | .clkdm_name = "core_l3_clkdm", |
e32744b0 | 1603 | .recalc = &followparent_recalc, |
046d6b28 TL |
1604 | }; |
1605 | ||
046d6b28 TL |
1606 | static struct clk sdrc_ick = { |
1607 | .name = "sdrc_ick", | |
b36ee724 | 1608 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1609 | .parent = &l4_ck, |
8ad8ff65 | 1610 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1611 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1612 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1613 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | |
1614 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1615 | }; |
1616 | ||
1617 | static struct clk des_ick = { | |
1618 | .name = "des_ick", | |
b36ee724 | 1619 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1620 | .parent = &l4_ck, |
d1b03f61 | 1621 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1623 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
1624 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1625 | }; |
1626 | ||
1627 | static struct clk sha_ick = { | |
1628 | .name = "sha_ick", | |
b36ee724 | 1629 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1630 | .parent = &l4_ck, |
d1b03f61 | 1631 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1633 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1634 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1635 | }; |
1636 | ||
1637 | static struct clk rng_ick = { | |
1638 | .name = "rng_ick", | |
b36ee724 | 1639 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1640 | .parent = &l4_ck, |
d1b03f61 | 1641 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1642 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1643 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1644 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1645 | }; |
1646 | ||
1647 | static struct clk aes_ick = { | |
1648 | .name = "aes_ick", | |
b36ee724 | 1649 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1650 | .parent = &l4_ck, |
d1b03f61 | 1651 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1653 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
1654 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1655 | }; |
1656 | ||
1657 | static struct clk pka_ick = { | |
1658 | .name = "pka_ick", | |
b36ee724 | 1659 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1660 | .parent = &l4_ck, |
d1b03f61 | 1661 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1662 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1663 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1664 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1665 | }; |
1666 | ||
1667 | static struct clk usb_fck = { | |
1668 | .name = "usb_fck", | |
b36ee724 | 1669 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1670 | .parent = &func_48m_ck, |
d1b03f61 | 1671 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1673 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1674 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1675 | }; |
1676 | ||
1677 | static struct clk usbhs_ick = { | |
1678 | .name = "usbhs_ick", | |
b36ee724 | 1679 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 1680 | .parent = &core_l3_ck, |
d1b03f61 | 1681 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1682 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1683 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | |
1684 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1685 | }; |
1686 | ||
1687 | static struct clk mmchs1_ick = { | |
b92c170d | 1688 | .name = "mmchs1_ick", |
b36ee724 | 1689 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1690 | .parent = &l4_ck, |
d1b03f61 | 1691 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1692 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1693 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1694 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1695 | }; |
1696 | ||
1697 | static struct clk mmchs1_fck = { | |
b92c170d | 1698 | .name = "mmchs1_fck", |
b36ee724 | 1699 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1700 | .parent = &func_96m_ck, |
d1b03f61 | 1701 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1703 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1704 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1705 | }; |
1706 | ||
1707 | static struct clk mmchs2_ick = { | |
b92c170d | 1708 | .name = "mmchs2_ick", |
b36ee724 | 1709 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1710 | .parent = &l4_ck, |
d1b03f61 | 1711 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1713 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1714 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1715 | }; |
1716 | ||
1717 | static struct clk mmchs2_fck = { | |
b92c170d | 1718 | .name = "mmchs2_fck", |
b36ee724 | 1719 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1720 | .parent = &func_96m_ck, |
e32744b0 PW |
1721 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1722 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1723 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1724 | }; |
1725 | ||
1726 | static struct clk gpio5_ick = { | |
1727 | .name = "gpio5_ick", | |
b36ee724 | 1728 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1729 | .parent = &l4_ck, |
d1b03f61 | 1730 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1731 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1732 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1733 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1734 | }; |
1735 | ||
1736 | static struct clk gpio5_fck = { | |
1737 | .name = "gpio5_fck", | |
b36ee724 | 1738 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1739 | .parent = &func_32k_ck, |
d1b03f61 | 1740 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1742 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1743 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1744 | }; |
1745 | ||
1746 | static struct clk mdm_intc_ick = { | |
1747 | .name = "mdm_intc_ick", | |
b36ee724 | 1748 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1749 | .parent = &l4_ck, |
d1b03f61 | 1750 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1752 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | |
1753 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1754 | }; |
1755 | ||
1756 | static struct clk mmchsdb1_fck = { | |
b92c170d | 1757 | .name = "mmchsdb1_fck", |
b36ee724 | 1758 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1759 | .parent = &func_32k_ck, |
d1b03f61 | 1760 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1762 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | |
1763 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1764 | }; |
1765 | ||
1766 | static struct clk mmchsdb2_fck = { | |
b92c170d | 1767 | .name = "mmchsdb2_fck", |
b36ee724 | 1768 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1769 | .parent = &func_32k_ck, |
d1b03f61 | 1770 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1772 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | |
1773 | .recalc = &followparent_recalc, | |
046d6b28 | 1774 | }; |
e32744b0 | 1775 | |
046d6b28 TL |
1776 | /* |
1777 | * This clock is a composite clock which does entire set changes then | |
1778 | * forces a rebalance. It keys on the MPU speed, but it really could | |
1779 | * be any key speed part of a set in the rate table. | |
1780 | * | |
1781 | * to really change a set, you need memory table sets which get changed | |
1782 | * in sram, pre-notifiers & post notifiers, changing the top set, without | |
1783 | * having low level display recalc's won't work... this is why dpm notifiers | |
1784 | * work, isr's off, walk a list of clocks already _off_ and not messing with | |
1785 | * the bus. | |
1786 | * | |
1787 | * This clock should have no parent. It embodies the entire upper level | |
1788 | * active set. A parent will mess up some of the init also. | |
1789 | */ | |
1790 | static struct clk virt_prcm_set = { | |
1791 | .name = "virt_prcm_set", | |
897dcded | 1792 | .ops = &clkops_null, |
046d6b28 | 1793 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
e32744b0 | 1794 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
046d6b28 TL |
1795 | .set_rate = &omap2_select_table_rate, |
1796 | .round_rate = &omap2_round_to_table_rate, | |
1797 | }; | |
e32744b0 | 1798 | |
d8a94458 PW |
1799 | |
1800 | /* | |
1801 | * clkdev integration | |
1802 | */ | |
1803 | ||
81b34fbe | 1804 | static struct omap_clk omap2430_clks[] = { |
d8a94458 | 1805 | /* external root sources */ |
81b34fbe PW |
1806 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), |
1807 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), | |
1808 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), | |
1809 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), | |
1810 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), | |
d8a94458 | 1811 | /* internal analog sources */ |
81b34fbe PW |
1812 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
1813 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), | |
1814 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), | |
d8a94458 | 1815 | /* internal prcm root sources */ |
81b34fbe PW |
1816 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
1817 | CLK(NULL, "core_ck", &core_ck, CK_243X), | |
1818 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), | |
1819 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), | |
1820 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), | |
1821 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), | |
1822 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), | |
1823 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), | |
1824 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), | |
d8a94458 | 1825 | /* mpu domain clocks */ |
81b34fbe | 1826 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), |
d8a94458 | 1827 | /* dsp domain clocks */ |
81b34fbe PW |
1828 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), |
1829 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X), | |
d8a94458 | 1830 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
d8a94458 | 1831 | /* GFX domain clocks */ |
81b34fbe PW |
1832 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), |
1833 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), | |
1834 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), | |
d8a94458 PW |
1835 | /* Modem domain clocks */ |
1836 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | |
1837 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | |
1838 | /* DSS domain clocks */ | |
81b34fbe PW |
1839 | CLK("omapdss", "ick", &dss_ick, CK_243X), |
1840 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), | |
1841 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), | |
1842 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), | |
d8a94458 | 1843 | /* L3 domain clocks */ |
81b34fbe PW |
1844 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), |
1845 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), | |
1846 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), | |
d8a94458 | 1847 | /* L4 domain clocks */ |
81b34fbe PW |
1848 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), |
1849 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), | |
d8a94458 | 1850 | /* virtual meta-group clock */ |
81b34fbe | 1851 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), |
d8a94458 | 1852 | /* general l4 interface ck, multi-parent functional clk */ |
81b34fbe PW |
1853 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), |
1854 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), | |
1855 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), | |
1856 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), | |
1857 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), | |
1858 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), | |
1859 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), | |
1860 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), | |
1861 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), | |
1862 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), | |
1863 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), | |
1864 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), | |
1865 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), | |
1866 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), | |
1867 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), | |
1868 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), | |
1869 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), | |
1870 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), | |
1871 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), | |
1872 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), | |
1873 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), | |
1874 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), | |
1875 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), | |
1876 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), | |
1877 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), | |
1878 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), | |
1879 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), | |
1880 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), | |
d8a94458 PW |
1881 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
1882 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | |
1883 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | |
1884 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | |
1885 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | |
1886 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | |
81b34fbe PW |
1887 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), |
1888 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), | |
1889 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), | |
1890 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), | |
d8a94458 PW |
1891 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
1892 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | |
81b34fbe PW |
1893 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), |
1894 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), | |
1895 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), | |
1896 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), | |
1897 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), | |
1898 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), | |
1899 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), | |
1900 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), | |
1901 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), | |
1902 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), | |
1903 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), | |
1904 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), | |
1905 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), | |
d8a94458 | 1906 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
81b34fbe PW |
1907 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), |
1908 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), | |
1909 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), | |
1910 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), | |
1911 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), | |
1912 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), | |
1913 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), | |
1914 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), | |
1915 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), | |
1916 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), | |
1917 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), | |
1918 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X), | |
d8a94458 | 1919 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), |
81b34fbe | 1920 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X), |
d8a94458 | 1921 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), |
81b34fbe PW |
1922 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
1923 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), | |
1924 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), | |
d8a94458 | 1925 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
81b34fbe | 1926 | CLK(NULL, "des_ick", &des_ick, CK_243X), |
ee5500c4 | 1927 | CLK("omap-sham", "ick", &sha_ick, CK_243X), |
81b34fbe PW |
1928 | CLK("omap_rng", "ick", &rng_ick, CK_243X), |
1929 | CLK(NULL, "aes_ick", &aes_ick, CK_243X), | |
1930 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), | |
1931 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), | |
d8a94458 PW |
1932 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), |
1933 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | |
1934 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | |
1935 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | |
1936 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | |
1937 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | |
1938 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | |
1939 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | |
1940 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | |
1941 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | |
1942 | }; | |
1943 | ||
1944 | /* | |
1945 | * init code | |
1946 | */ | |
1947 | ||
81b34fbe | 1948 | int __init omap2430_clk_init(void) |
d8a94458 PW |
1949 | { |
1950 | const struct prcm_config *prcm; | |
1951 | struct omap_clk *c; | |
1952 | u32 clkrate; | |
81b34fbe PW |
1953 | |
1954 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
1955 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | |
1956 | cpu_mask = RATE_IN_243X; | |
1957 | rate_table = omap2430_rate_table; | |
d8a94458 PW |
1958 | |
1959 | clk_init(&omap2_clk_functions); | |
1960 | ||
81b34fbe PW |
1961 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
1962 | c++) | |
d8a94458 PW |
1963 | clk_preinit(c->lk.clk); |
1964 | ||
1965 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | |
1966 | propagate_rate(&osc_ck); | |
44da0a51 | 1967 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
d8a94458 PW |
1968 | propagate_rate(&sys_ck); |
1969 | ||
81b34fbe PW |
1970 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
1971 | c++) { | |
1972 | clkdev_add(&c->lk); | |
1973 | clk_register(c->lk.clk); | |
1974 | omap2_init_clk_clkdm(c->lk.clk); | |
1975 | } | |
d8a94458 PW |
1976 | |
1977 | /* Check the MPU rate set by bootloader */ | |
1978 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | |
1979 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
1980 | if (!(prcm->flags & cpu_mask)) | |
1981 | continue; | |
1982 | if (prcm->xtal_speed != sys_ck.rate) | |
1983 | continue; | |
1984 | if (prcm->dpll_speed <= clkrate) | |
1985 | break; | |
1986 | } | |
1987 | curr_prcm_set = prcm; | |
1988 | ||
1989 | recalculate_root_clocks(); | |
1990 | ||
81b34fbe PW |
1991 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
1992 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
1993 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
d8a94458 PW |
1994 | |
1995 | /* | |
1996 | * Only enable those clocks we will need, let the drivers | |
1997 | * enable other clocks as necessary | |
1998 | */ | |
1999 | clk_enable_init_clocks(); | |
2000 | ||
2001 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | |
2002 | vclk = clk_get(NULL, "virt_prcm_set"); | |
2003 | sclk = clk_get(NULL, "sys_ck"); | |
2004 | dclk = clk_get(NULL, "dpll_ck"); | |
2005 | ||
2006 | return 0; | |
2007 | } | |
6b8858a9 | 2008 |