Commit | Line | Data |
---|---|---|
046d6b28 | 1 | /* |
81b34fbe | 2 | * linux/arch/arm/mach-omap2/clock2430_data.c |
046d6b28 | 3 | * |
d8a94458 | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
93340a22 | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
046d6b28 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 TL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
d8a94458 PW |
16 | #include <linux/kernel.h> |
17 | #include <linux/clk.h> | |
93340a22 | 18 | #include <linux/list.h> |
046d6b28 | 19 | |
d8a94458 | 20 | #include <plat/clkdev_omap.h> |
6b8858a9 | 21 | |
d8a94458 PW |
22 | #include "clock.h" |
23 | #include "clock2xxx.h" | |
24 | #include "opp2xxx.h" | |
59fb659b PW |
25 | #include "cm2xxx_3xxx.h" |
26 | #include "prm2xxx_3xxx.h" | |
6b8858a9 PW |
27 | #include "prm-regbits-24xx.h" |
28 | #include "cm-regbits-24xx.h" | |
29 | #include "sdrc.h" | |
4814ced5 | 30 | #include "control.h" |
6b8858a9 | 31 | |
81b34fbe PW |
32 | #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR |
33 | ||
34 | /* | |
35 | * 2430 clock tree. | |
046d6b28 TL |
36 | * |
37 | * NOTE:In many cases here we are assigning a 'default' parent. In many | |
38 | * cases the parent is selectable. The get/set parent calls will also | |
39 | * switch sources. | |
40 | * | |
41 | * Many some clocks say always_enabled, but they can be auto idled for | |
42 | * power savings. They will always be available upon clock request. | |
43 | * | |
44 | * Several sources are given initial rates which may be wrong, this will | |
45 | * be fixed up in the init func. | |
46 | * | |
47 | * Things are broadly separated below by clock domains. It is | |
48 | * noteworthy that most periferals have dependencies on multiple clock | |
49 | * domains. Many get their interface clocks from the L4 domain, but get | |
50 | * functional clocks from fixed sources or other core domain derived | |
51 | * clocks. | |
81b34fbe | 52 | */ |
046d6b28 TL |
53 | |
54 | /* Base external input clocks */ | |
55 | static struct clk func_32k_ck = { | |
56 | .name = "func_32k_ck", | |
897dcded | 57 | .ops = &clkops_null, |
046d6b28 | 58 | .rate = 32000, |
d1b03f61 | 59 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 60 | }; |
e32744b0 | 61 | |
f248076c PW |
62 | static struct clk secure_32k_ck = { |
63 | .name = "secure_32k_ck", | |
64 | .ops = &clkops_null, | |
65 | .rate = 32768, | |
f248076c PW |
66 | .clkdm_name = "wkup_clkdm", |
67 | }; | |
68 | ||
046d6b28 TL |
69 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
70 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |
71 | .name = "osc_ck", | |
548d8495 | 72 | .ops = &clkops_oscck, |
d1b03f61 | 73 | .clkdm_name = "wkup_clkdm", |
e32744b0 | 74 | .recalc = &omap2_osc_clk_recalc, |
046d6b28 TL |
75 | }; |
76 | ||
d1b03f61 | 77 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
046d6b28 TL |
78 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
79 | .name = "sys_ck", /* ~ ref_clk also */ | |
897dcded | 80 | .ops = &clkops_null, |
046d6b28 | 81 | .parent = &osc_ck, |
d1b03f61 | 82 | .clkdm_name = "wkup_clkdm", |
44da0a51 | 83 | .recalc = &omap2xxx_sys_clk_recalc, |
046d6b28 | 84 | }; |
e32744b0 | 85 | |
046d6b28 TL |
86 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
87 | .name = "alt_ck", | |
897dcded | 88 | .ops = &clkops_null, |
046d6b28 | 89 | .rate = 54000000, |
d1b03f61 | 90 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 91 | }; |
e32744b0 | 92 | |
b115b743 PW |
93 | /* Optional external clock input for McBSP CLKS */ |
94 | static struct clk mcbsp_clks = { | |
95 | .name = "mcbsp_clks", | |
96 | .ops = &clkops_null, | |
97 | }; | |
98 | ||
046d6b28 TL |
99 | /* |
100 | * Analog domain root source clocks | |
101 | */ | |
102 | ||
103 | /* dpll_ck, is broken out in to special cases through clksel */ | |
6b8858a9 PW |
104 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
105 | * deal with this | |
106 | */ | |
107 | ||
88b8ba90 | 108 | static struct dpll_data dpll_dd = { |
6b8858a9 PW |
109 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
110 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
111 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
c0bf3132 RK |
112 | .clk_bypass = &sys_ck, |
113 | .clk_ref = &sys_ck, | |
114 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
115 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
93340a22 | 116 | .max_multiplier = 1023, |
95f538ac | 117 | .min_divider = 1, |
88b8ba90 PW |
118 | .max_divider = 16, |
119 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
6b8858a9 PW |
120 | }; |
121 | ||
88b8ba90 PW |
122 | /* |
123 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | |
124 | * not just a DPLL | |
125 | */ | |
046d6b28 TL |
126 | static struct clk dpll_ck = { |
127 | .name = "dpll_ck", | |
897dcded | 128 | .ops = &clkops_null, |
046d6b28 | 129 | .parent = &sys_ck, /* Can be func_32k also */ |
6b8858a9 | 130 | .dpll_data = &dpll_dd, |
d1b03f61 | 131 | .clkdm_name = "wkup_clkdm", |
88b8ba90 PW |
132 | .recalc = &omap2_dpllcore_recalc, |
133 | .set_rate = &omap2_reprogram_dpllcore, | |
046d6b28 TL |
134 | }; |
135 | ||
136 | static struct clk apll96_ck = { | |
137 | .name = "apll96_ck", | |
06b16939 | 138 | .ops = &clkops_apll96, |
046d6b28 TL |
139 | .parent = &sys_ck, |
140 | .rate = 96000000, | |
51c19541 | 141 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 142 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
143 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
144 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
046d6b28 TL |
145 | }; |
146 | ||
147 | static struct clk apll54_ck = { | |
148 | .name = "apll54_ck", | |
06b16939 | 149 | .ops = &clkops_apll54, |
046d6b28 TL |
150 | .parent = &sys_ck, |
151 | .rate = 54000000, | |
51c19541 | 152 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 153 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
154 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
155 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
046d6b28 TL |
156 | }; |
157 | ||
158 | /* | |
159 | * PRCM digital base sources | |
160 | */ | |
e32744b0 PW |
161 | |
162 | /* func_54m_ck */ | |
163 | ||
164 | static const struct clksel_rate func_54m_apll54_rates[] = { | |
d74b4949 | 165 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
166 | { .div = 0 }, |
167 | }; | |
168 | ||
169 | static const struct clksel_rate func_54m_alt_rates[] = { | |
d74b4949 | 170 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
171 | { .div = 0 }, |
172 | }; | |
173 | ||
174 | static const struct clksel func_54m_clksel[] = { | |
175 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | |
176 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | |
177 | { .parent = NULL }, | |
178 | }; | |
179 | ||
046d6b28 TL |
180 | static struct clk func_54m_ck = { |
181 | .name = "func_54m_ck", | |
57137181 | 182 | .ops = &clkops_null, |
046d6b28 | 183 | .parent = &apll54_ck, /* can also be alt_clk */ |
d1b03f61 | 184 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
185 | .init = &omap2_init_clksel_parent, |
186 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 187 | .clksel_mask = OMAP24XX_54M_SOURCE_MASK, |
e32744b0 PW |
188 | .clksel = func_54m_clksel, |
189 | .recalc = &omap2_clksel_recalc, | |
046d6b28 | 190 | }; |
e32744b0 | 191 | |
046d6b28 TL |
192 | static struct clk core_ck = { |
193 | .name = "core_ck", | |
897dcded | 194 | .ops = &clkops_null, |
046d6b28 | 195 | .parent = &dpll_ck, /* can also be 32k */ |
d1b03f61 | 196 | .clkdm_name = "wkup_clkdm", |
6b8858a9 | 197 | .recalc = &followparent_recalc, |
046d6b28 | 198 | }; |
e32744b0 PW |
199 | |
200 | /* func_96m_ck */ | |
201 | static const struct clksel_rate func_96m_apll96_rates[] = { | |
d74b4949 | 202 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 | 203 | { .div = 0 }, |
046d6b28 TL |
204 | }; |
205 | ||
e32744b0 | 206 | static const struct clksel_rate func_96m_alt_rates[] = { |
d74b4949 | 207 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, |
e32744b0 PW |
208 | { .div = 0 }, |
209 | }; | |
210 | ||
211 | static const struct clksel func_96m_clksel[] = { | |
212 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, | |
213 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, | |
214 | { .parent = NULL } | |
215 | }; | |
216 | ||
046d6b28 TL |
217 | static struct clk func_96m_ck = { |
218 | .name = "func_96m_ck", | |
57137181 | 219 | .ops = &clkops_null, |
046d6b28 | 220 | .parent = &apll96_ck, |
d1b03f61 | 221 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
222 | .init = &omap2_init_clksel_parent, |
223 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 224 | .clksel_mask = OMAP2430_96M_SOURCE_MASK, |
e32744b0 PW |
225 | .clksel = func_96m_clksel, |
226 | .recalc = &omap2_clksel_recalc, | |
e32744b0 PW |
227 | }; |
228 | ||
229 | /* func_48m_ck */ | |
230 | ||
231 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
d74b4949 | 232 | { .div = 2, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
233 | { .div = 0 }, |
234 | }; | |
235 | ||
236 | static const struct clksel_rate func_48m_alt_rates[] = { | |
d74b4949 | 237 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
238 | { .div = 0 }, |
239 | }; | |
240 | ||
241 | static const struct clksel func_48m_clksel[] = { | |
242 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
243 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
244 | { .parent = NULL } | |
046d6b28 TL |
245 | }; |
246 | ||
247 | static struct clk func_48m_ck = { | |
248 | .name = "func_48m_ck", | |
57137181 | 249 | .ops = &clkops_null, |
046d6b28 | 250 | .parent = &apll96_ck, /* 96M or Alt */ |
d1b03f61 | 251 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
252 | .init = &omap2_init_clksel_parent, |
253 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
f38ca10a | 254 | .clksel_mask = OMAP24XX_48M_SOURCE_MASK, |
e32744b0 PW |
255 | .clksel = func_48m_clksel, |
256 | .recalc = &omap2_clksel_recalc, | |
257 | .round_rate = &omap2_clksel_round_rate, | |
258 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
259 | }; |
260 | ||
261 | static struct clk func_12m_ck = { | |
262 | .name = "func_12m_ck", | |
57137181 | 263 | .ops = &clkops_null, |
046d6b28 | 264 | .parent = &func_48m_ck, |
e32744b0 | 265 | .fixed_div = 4, |
d1b03f61 | 266 | .clkdm_name = "wkup_clkdm", |
e9b98f60 | 267 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
268 | }; |
269 | ||
270 | /* Secure timer, only available in secure mode */ | |
271 | static struct clk wdt1_osc_ck = { | |
272 | .name = "ck_wdt1_osc", | |
897dcded | 273 | .ops = &clkops_null, /* RMK: missing? */ |
046d6b28 | 274 | .parent = &osc_ck, |
e32744b0 PW |
275 | .recalc = &followparent_recalc, |
276 | }; | |
277 | ||
278 | /* | |
279 | * The common_clkout* clksel_rate structs are common to | |
280 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | |
281 | * sys_clkout2_* are 2420-only, so the | |
282 | * clksel_rate flags fields are inaccurate for those clocks. This is | |
283 | * harmless since access to those clocks are gated by the struct clk | |
284 | * flags fields, which mark them as 2420-only. | |
285 | */ | |
286 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
d74b4949 | 287 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
288 | { .div = 0 } |
289 | }; | |
290 | ||
291 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
d74b4949 | 292 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
293 | { .div = 0 } |
294 | }; | |
295 | ||
296 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
d74b4949 | 297 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
298 | { .div = 0 } |
299 | }; | |
300 | ||
301 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
d74b4949 | 302 | { .div = 1, .val = 3, .flags = RATE_IN_24XX }, |
e32744b0 PW |
303 | { .div = 0 } |
304 | }; | |
305 | ||
306 | static const struct clksel common_clkout_src_clksel[] = { | |
307 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
308 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
309 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
310 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
311 | { .parent = NULL } | |
312 | }; | |
313 | ||
314 | static struct clk sys_clkout_src = { | |
315 | .name = "sys_clkout_src", | |
c1168dc3 | 316 | .ops = &clkops_omap2_dflt, |
e32744b0 | 317 | .parent = &func_54m_ck, |
d1b03f61 | 318 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 319 | .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
320 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
321 | .init = &omap2_init_clksel_parent, | |
81b34fbe | 322 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
323 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
324 | .clksel = common_clkout_src_clksel, | |
325 | .recalc = &omap2_clksel_recalc, | |
326 | .round_rate = &omap2_clksel_round_rate, | |
327 | .set_rate = &omap2_clksel_set_rate | |
328 | }; | |
329 | ||
330 | static const struct clksel_rate common_clkout_rates[] = { | |
d74b4949 | 331 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
332 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
333 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | |
334 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | |
335 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | |
336 | { .div = 0 }, | |
337 | }; | |
338 | ||
339 | static const struct clksel sys_clkout_clksel[] = { | |
340 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | |
341 | { .parent = NULL } | |
046d6b28 TL |
342 | }; |
343 | ||
344 | static struct clk sys_clkout = { | |
345 | .name = "sys_clkout", | |
57137181 | 346 | .ops = &clkops_null, |
e32744b0 | 347 | .parent = &sys_clkout_src, |
d1b03f61 | 348 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 349 | .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, |
e32744b0 PW |
350 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
351 | .clksel = sys_clkout_clksel, | |
352 | .recalc = &omap2_clksel_recalc, | |
353 | .round_rate = &omap2_clksel_round_rate, | |
354 | .set_rate = &omap2_clksel_set_rate | |
355 | }; | |
356 | ||
b824efae TL |
357 | static struct clk emul_ck = { |
358 | .name = "emul_ck", | |
c1168dc3 | 359 | .ops = &clkops_omap2_dflt, |
b824efae | 360 | .parent = &func_54m_ck, |
d1b03f61 | 361 | .clkdm_name = "wkup_clkdm", |
81b34fbe | 362 | .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, |
e32744b0 PW |
363 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
364 | .recalc = &followparent_recalc, | |
b824efae TL |
365 | |
366 | }; | |
e32744b0 | 367 | |
046d6b28 TL |
368 | /* |
369 | * MPU clock domain | |
370 | * Clocks: | |
371 | * MPU_FCLK, MPU_ICLK | |
372 | * INT_M_FCLK, INT_M_I_CLK | |
373 | * | |
374 | * - Individual clocks are hardware managed. | |
375 | * - Base divider comes from: CM_CLKSEL_MPU | |
376 | * | |
377 | */ | |
e32744b0 | 378 | static const struct clksel_rate mpu_core_rates[] = { |
d74b4949 | 379 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 | 380 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
381 | { .div = 0 }, |
382 | }; | |
383 | ||
384 | static const struct clksel mpu_clksel[] = { | |
385 | { .parent = &core_ck, .rates = mpu_core_rates }, | |
386 | { .parent = NULL } | |
387 | }; | |
388 | ||
046d6b28 TL |
389 | static struct clk mpu_ck = { /* Control cpu */ |
390 | .name = "mpu_ck", | |
897dcded | 391 | .ops = &clkops_null, |
046d6b28 | 392 | .parent = &core_ck, |
d1b03f61 | 393 | .clkdm_name = "mpu_clkdm", |
6b8858a9 PW |
394 | .init = &omap2_init_clksel_parent, |
395 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
396 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | |
e32744b0 | 397 | .clksel = mpu_clksel, |
046d6b28 TL |
398 | .recalc = &omap2_clksel_recalc, |
399 | }; | |
e32744b0 | 400 | |
046d6b28 | 401 | /* |
81b34fbe | 402 | * DSP (2430-IVA2.1) clock domain |
046d6b28 | 403 | * Clocks: |
e32744b0 | 404 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
e32744b0 PW |
405 | * |
406 | * Won't be too specific here. The core clock comes into this block | |
407 | * it is divided then tee'ed. One branch goes directly to xyz enable | |
408 | * controls. The other branch gets further divided by 2 then possibly | |
409 | * routed into a synchronizer and out of clocks abc. | |
046d6b28 | 410 | */ |
e32744b0 | 411 | static const struct clksel_rate dsp_fck_core_rates[] = { |
d74b4949 | 412 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
413 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
414 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
415 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
e32744b0 PW |
416 | { .div = 0 }, |
417 | }; | |
418 | ||
419 | static const struct clksel dsp_fck_clksel[] = { | |
420 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
421 | { .parent = NULL } | |
422 | }; | |
423 | ||
424 | static struct clk dsp_fck = { | |
425 | .name = "dsp_fck", | |
b36ee724 | 426 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 427 | .parent = &core_ck, |
d1b03f61 | 428 | .clkdm_name = "dsp_clkdm", |
e32744b0 PW |
429 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
430 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
431 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
432 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | |
433 | .clksel = dsp_fck_clksel, | |
046d6b28 TL |
434 | .recalc = &omap2_clksel_recalc, |
435 | }; | |
436 | ||
e32744b0 PW |
437 | /* DSP interface clock */ |
438 | static const struct clksel_rate dsp_irate_ick_rates[] = { | |
d74b4949 | 439 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
440 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
441 | { .div = 3, .val = 3, .flags = RATE_IN_243X }, | |
442 | { .div = 0 }, | |
443 | }; | |
444 | ||
445 | static const struct clksel dsp_irate_ick_clksel[] = { | |
446 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | |
447 | { .parent = NULL } | |
046d6b28 TL |
448 | }; |
449 | ||
d1b03f61 | 450 | /* This clock does not exist as such in the TRM. */ |
e32744b0 PW |
451 | static struct clk dsp_irate_ick = { |
452 | .name = "dsp_irate_ick", | |
57137181 | 453 | .ops = &clkops_null, |
e32744b0 | 454 | .parent = &dsp_fck, |
e32744b0 PW |
455 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
456 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | |
457 | .clksel = dsp_irate_ick_clksel, | |
046d6b28 TL |
458 | .recalc = &omap2_clksel_recalc, |
459 | }; | |
460 | ||
e32744b0 PW |
461 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
462 | static struct clk iva2_1_ick = { | |
463 | .name = "iva2_1_ick", | |
b36ee724 | 464 | .ops = &clkops_omap2_dflt_wait, |
e32744b0 | 465 | .parent = &dsp_irate_ick, |
e32744b0 PW |
466 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
467 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
046d6b28 TL |
468 | }; |
469 | ||
046d6b28 TL |
470 | /* |
471 | * L3 clock domain | |
472 | * L3 clocks are used for both interface and functional clocks to | |
473 | * multiple entities. Some of these clocks are completely managed | |
474 | * by hardware, and some others allow software control. Hardware | |
475 | * managed ones general are based on directly CLK_REQ signals and | |
476 | * various auto idle settings. The functional spec sets many of these | |
477 | * as 'tie-high' for their enables. | |
478 | * | |
479 | * I-CLOCKS: | |
480 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | |
481 | * CAM, HS-USB. | |
482 | * F-CLOCK | |
483 | * SSI. | |
484 | * | |
485 | * GPMC memories and SDRC have timing and clock sensitive registers which | |
486 | * may very well need notification when the clock changes. Currently for low | |
487 | * operating points, these are taken care of in sleep.S. | |
488 | */ | |
e32744b0 PW |
489 | static const struct clksel_rate core_l3_core_rates[] = { |
490 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 491 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
e32744b0 | 492 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
e32744b0 PW |
493 | { .div = 0 } |
494 | }; | |
495 | ||
496 | static const struct clksel core_l3_clksel[] = { | |
497 | { .parent = &core_ck, .rates = core_l3_core_rates }, | |
498 | { .parent = NULL } | |
499 | }; | |
500 | ||
046d6b28 TL |
501 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
502 | .name = "core_l3_ck", | |
897dcded | 503 | .ops = &clkops_null, |
046d6b28 | 504 | .parent = &core_ck, |
d1b03f61 | 505 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
506 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
507 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | |
508 | .clksel = core_l3_clksel, | |
046d6b28 | 509 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
510 | }; |
511 | ||
512 | /* usb_l4_ick */ | |
513 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
514 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 515 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
516 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
517 | { .div = 0 } | |
518 | }; | |
519 | ||
520 | static const struct clksel usb_l4_ick_clksel[] = { | |
521 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
522 | { .parent = NULL }, | |
046d6b28 TL |
523 | }; |
524 | ||
d1b03f61 | 525 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
046d6b28 TL |
526 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
527 | .name = "usb_l4_ick", | |
b36ee724 | 528 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 529 | .parent = &core_l3_ck, |
d1b03f61 | 530 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
531 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
532 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
533 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
534 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | |
535 | .clksel = usb_l4_ick_clksel, | |
046d6b28 TL |
536 | .recalc = &omap2_clksel_recalc, |
537 | }; | |
538 | ||
d1b03f61 PW |
539 | /* |
540 | * L4 clock management domain | |
541 | * | |
542 | * This domain contains lots of interface clocks from the L4 interface, some | |
543 | * functional clocks. Fixed APLL functional source clocks are managed in | |
544 | * this domain. | |
545 | */ | |
546 | static const struct clksel_rate l4_core_l3_rates[] = { | |
d74b4949 | 547 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
d1b03f61 PW |
548 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
549 | { .div = 0 } | |
550 | }; | |
551 | ||
552 | static const struct clksel l4_clksel[] = { | |
553 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | |
554 | { .parent = NULL } | |
555 | }; | |
556 | ||
557 | static struct clk l4_ck = { /* used both as an ick and fck */ | |
558 | .name = "l4_ck", | |
897dcded | 559 | .ops = &clkops_null, |
d1b03f61 | 560 | .parent = &core_l3_ck, |
d1b03f61 PW |
561 | .clkdm_name = "core_l4_clkdm", |
562 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
563 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | |
564 | .clksel = l4_clksel, | |
565 | .recalc = &omap2_clksel_recalc, | |
d1b03f61 PW |
566 | }; |
567 | ||
046d6b28 TL |
568 | /* |
569 | * SSI is in L3 management domain, its direct parent is core not l3, | |
570 | * many core power domain entities are grouped into the L3 clock | |
571 | * domain. | |
d1b03f61 | 572 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
046d6b28 TL |
573 | * |
574 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | |
575 | */ | |
e32744b0 PW |
576 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
577 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
d74b4949 | 578 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
579 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
580 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
581 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | |
e32744b0 PW |
582 | { .div = 0 } |
583 | }; | |
584 | ||
585 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
586 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
587 | { .parent = NULL } | |
588 | }; | |
589 | ||
046d6b28 TL |
590 | static struct clk ssi_ssr_sst_fck = { |
591 | .name = "ssi_fck", | |
b36ee724 | 592 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 593 | .parent = &core_ck, |
d1b03f61 | 594 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
595 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
596 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
597 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
598 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | |
599 | .clksel = ssi_ssr_sst_fck_clksel, | |
046d6b28 TL |
600 | .recalc = &omap2_clksel_recalc, |
601 | }; | |
602 | ||
9299fd85 PW |
603 | /* |
604 | * Presumably this is the same as SSI_ICLK. | |
605 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | |
606 | */ | |
607 | static struct clk ssi_l4_ick = { | |
608 | .name = "ssi_l4_ick", | |
609 | .ops = &clkops_omap2_dflt_wait, | |
610 | .parent = &l4_ck, | |
611 | .clkdm_name = "core_l4_clkdm", | |
612 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
613 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
614 | .recalc = &followparent_recalc, | |
615 | }; | |
616 | ||
d1b03f61 | 617 | |
046d6b28 TL |
618 | /* |
619 | * GFX clock domain | |
620 | * Clocks: | |
621 | * GFX_FCLK, GFX_ICLK | |
622 | * GFX_CG1(2d), GFX_CG2(3d) | |
623 | * | |
624 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | |
625 | * The 2d and 3d clocks run at a hardware determined | |
626 | * divided value of fclk. | |
627 | * | |
628 | */ | |
e32744b0 PW |
629 | |
630 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | |
631 | static const struct clksel gfx_fck_clksel[] = { | |
632 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
633 | { .parent = NULL }, | |
634 | }; | |
635 | ||
046d6b28 TL |
636 | static struct clk gfx_3d_fck = { |
637 | .name = "gfx_3d_fck", | |
b36ee724 | 638 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 639 | .parent = &core_l3_ck, |
d1b03f61 | 640 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
641 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
642 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | |
643 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
644 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
645 | .clksel = gfx_fck_clksel, | |
046d6b28 | 646 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
647 | .round_rate = &omap2_clksel_round_rate, |
648 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
649 | }; |
650 | ||
651 | static struct clk gfx_2d_fck = { | |
652 | .name = "gfx_2d_fck", | |
b36ee724 | 653 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 654 | .parent = &core_l3_ck, |
d1b03f61 | 655 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
656 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
657 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | |
658 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
659 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
660 | .clksel = gfx_fck_clksel, | |
046d6b28 TL |
661 | .recalc = &omap2_clksel_recalc, |
662 | }; | |
663 | ||
664 | static struct clk gfx_ick = { | |
665 | .name = "gfx_ick", /* From l3 */ | |
b36ee724 | 666 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 667 | .parent = &core_l3_ck, |
d1b03f61 | 668 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
669 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
670 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
671 | .recalc = &followparent_recalc, | |
046d6b28 TL |
672 | }; |
673 | ||
674 | /* | |
675 | * Modem clock domain (2430) | |
676 | * CLOCKS: | |
677 | * MDM_OSC_CLK | |
678 | * MDM_ICLK | |
e32744b0 | 679 | * These clocks are usable in chassis mode only. |
046d6b28 | 680 | */ |
e32744b0 PW |
681 | static const struct clksel_rate mdm_ick_core_rates[] = { |
682 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, | |
d74b4949 | 683 | { .div = 4, .val = 4, .flags = RATE_IN_243X }, |
e32744b0 PW |
684 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, |
685 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, | |
686 | { .div = 0 } | |
687 | }; | |
688 | ||
689 | static const struct clksel mdm_ick_clksel[] = { | |
690 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, | |
691 | { .parent = NULL } | |
692 | }; | |
693 | ||
046d6b28 TL |
694 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
695 | .name = "mdm_ick", | |
b36ee724 | 696 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 697 | .parent = &core_ck, |
d1b03f61 | 698 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
699 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
700 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | |
701 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | |
702 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | |
703 | .clksel = mdm_ick_clksel, | |
046d6b28 TL |
704 | .recalc = &omap2_clksel_recalc, |
705 | }; | |
706 | ||
707 | static struct clk mdm_osc_ck = { | |
708 | .name = "mdm_osc_ck", | |
b36ee724 | 709 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 710 | .parent = &osc_ck, |
d1b03f61 | 711 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
712 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
713 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | |
714 | .recalc = &followparent_recalc, | |
046d6b28 TL |
715 | }; |
716 | ||
046d6b28 TL |
717 | /* |
718 | * DSS clock domain | |
719 | * CLOCKs: | |
720 | * DSS_L4_ICLK, DSS_L3_ICLK, | |
721 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | |
722 | * | |
723 | * DSS is both initiator and target. | |
724 | */ | |
e32744b0 PW |
725 | /* XXX Add RATE_NOT_VALIDATED */ |
726 | ||
727 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
d74b4949 | 728 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
729 | { .div = 0 } |
730 | }; | |
731 | ||
732 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
733 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
734 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
735 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
736 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
737 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
738 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
739 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
740 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
741 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
d74b4949 | 742 | { .div = 16, .val = 16, .flags = RATE_IN_24XX }, |
e32744b0 PW |
743 | { .div = 0 } |
744 | }; | |
745 | ||
746 | static const struct clksel dss1_fck_clksel[] = { | |
747 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
748 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
749 | { .parent = NULL }, | |
750 | }; | |
751 | ||
046d6b28 TL |
752 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
753 | .name = "dss_ick", | |
bc51da4e | 754 | .ops = &clkops_omap2_dflt, |
046d6b28 | 755 | .parent = &l4_ck, /* really both l3 and l4 */ |
d1b03f61 | 756 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
757 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
758 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
759 | .recalc = &followparent_recalc, | |
046d6b28 TL |
760 | }; |
761 | ||
762 | static struct clk dss1_fck = { | |
763 | .name = "dss1_fck", | |
bc51da4e | 764 | .ops = &clkops_omap2_dflt, |
046d6b28 | 765 | .parent = &core_ck, /* Core or sys */ |
d1b03f61 | 766 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
767 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
768 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
769 | .init = &omap2_init_clksel_parent, | |
770 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
771 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | |
772 | .clksel = dss1_fck_clksel, | |
046d6b28 | 773 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
774 | }; |
775 | ||
776 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
d74b4949 | 777 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, |
e32744b0 PW |
778 | { .div = 0 } |
779 | }; | |
780 | ||
781 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
d74b4949 | 782 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
e32744b0 PW |
783 | { .div = 0 } |
784 | }; | |
785 | ||
786 | static const struct clksel dss2_fck_clksel[] = { | |
787 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
788 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
789 | { .parent = NULL } | |
046d6b28 TL |
790 | }; |
791 | ||
792 | static struct clk dss2_fck = { /* Alt clk used in power management */ | |
793 | .name = "dss2_fck", | |
bc51da4e | 794 | .ops = &clkops_omap2_dflt, |
046d6b28 | 795 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
d1b03f61 | 796 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
797 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
798 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | |
799 | .init = &omap2_init_clksel_parent, | |
800 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
801 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | |
802 | .clksel = dss2_fck_clksel, | |
d4521f67 | 803 | .recalc = &omap2_clksel_recalc, |
046d6b28 TL |
804 | }; |
805 | ||
806 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |
807 | .name = "dss_54m_fck", /* 54m tv clk */ | |
b36ee724 | 808 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 809 | .parent = &func_54m_ck, |
d1b03f61 | 810 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
811 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
812 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
813 | .recalc = &followparent_recalc, | |
046d6b28 TL |
814 | }; |
815 | ||
816 | /* | |
817 | * CORE power domain ICLK & FCLK defines. | |
818 | * Many of the these can have more than one possible parent. Entries | |
819 | * here will likely have an L4 interface parent, and may have multiple | |
820 | * functional clock parents. | |
821 | */ | |
e32744b0 | 822 | static const struct clksel_rate gpt_alt_rates[] = { |
d74b4949 | 823 | { .div = 1, .val = 2, .flags = RATE_IN_24XX }, |
e32744b0 PW |
824 | { .div = 0 } |
825 | }; | |
826 | ||
827 | static const struct clksel omap24xx_gpt_clksel[] = { | |
828 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
829 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
830 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
831 | { .parent = NULL }, | |
832 | }; | |
833 | ||
046d6b28 TL |
834 | static struct clk gpt1_ick = { |
835 | .name = "gpt1_ick", | |
b36ee724 | 836 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 837 | .parent = &l4_ck, |
d1b03f61 | 838 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
839 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
840 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
841 | .recalc = &followparent_recalc, | |
046d6b28 TL |
842 | }; |
843 | ||
844 | static struct clk gpt1_fck = { | |
845 | .name = "gpt1_fck", | |
b36ee724 | 846 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 847 | .parent = &func_32k_ck, |
d1b03f61 | 848 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
849 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
850 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
851 | .init = &omap2_init_clksel_parent, | |
852 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
853 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | |
854 | .clksel = omap24xx_gpt_clksel, | |
855 | .recalc = &omap2_clksel_recalc, | |
856 | .round_rate = &omap2_clksel_round_rate, | |
857 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
858 | }; |
859 | ||
860 | static struct clk gpt2_ick = { | |
861 | .name = "gpt2_ick", | |
b36ee724 | 862 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 863 | .parent = &l4_ck, |
d1b03f61 | 864 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
865 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
866 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
867 | .recalc = &followparent_recalc, | |
046d6b28 TL |
868 | }; |
869 | ||
870 | static struct clk gpt2_fck = { | |
871 | .name = "gpt2_fck", | |
b36ee724 | 872 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 873 | .parent = &func_32k_ck, |
d1b03f61 | 874 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
875 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
876 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
877 | .init = &omap2_init_clksel_parent, | |
878 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
879 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | |
880 | .clksel = omap24xx_gpt_clksel, | |
881 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
882 | }; |
883 | ||
884 | static struct clk gpt3_ick = { | |
885 | .name = "gpt3_ick", | |
b36ee724 | 886 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 887 | .parent = &l4_ck, |
d1b03f61 | 888 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
889 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
890 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
891 | .recalc = &followparent_recalc, | |
046d6b28 TL |
892 | }; |
893 | ||
894 | static struct clk gpt3_fck = { | |
895 | .name = "gpt3_fck", | |
b36ee724 | 896 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 897 | .parent = &func_32k_ck, |
d1b03f61 | 898 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
899 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
900 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
901 | .init = &omap2_init_clksel_parent, | |
902 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
903 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | |
904 | .clksel = omap24xx_gpt_clksel, | |
905 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
906 | }; |
907 | ||
908 | static struct clk gpt4_ick = { | |
909 | .name = "gpt4_ick", | |
b36ee724 | 910 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 911 | .parent = &l4_ck, |
d1b03f61 | 912 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
914 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
915 | .recalc = &followparent_recalc, | |
046d6b28 TL |
916 | }; |
917 | ||
918 | static struct clk gpt4_fck = { | |
919 | .name = "gpt4_fck", | |
b36ee724 | 920 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 921 | .parent = &func_32k_ck, |
d1b03f61 | 922 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
923 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
924 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
925 | .init = &omap2_init_clksel_parent, | |
926 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
927 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | |
928 | .clksel = omap24xx_gpt_clksel, | |
929 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
930 | }; |
931 | ||
932 | static struct clk gpt5_ick = { | |
933 | .name = "gpt5_ick", | |
b36ee724 | 934 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 935 | .parent = &l4_ck, |
d1b03f61 | 936 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
937 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
938 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
939 | .recalc = &followparent_recalc, | |
046d6b28 TL |
940 | }; |
941 | ||
942 | static struct clk gpt5_fck = { | |
943 | .name = "gpt5_fck", | |
b36ee724 | 944 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 945 | .parent = &func_32k_ck, |
d1b03f61 | 946 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
947 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
948 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
949 | .init = &omap2_init_clksel_parent, | |
950 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
951 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | |
952 | .clksel = omap24xx_gpt_clksel, | |
953 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
954 | }; |
955 | ||
956 | static struct clk gpt6_ick = { | |
957 | .name = "gpt6_ick", | |
b36ee724 | 958 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 959 | .parent = &l4_ck, |
d1b03f61 | 960 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
961 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
962 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
963 | .recalc = &followparent_recalc, | |
046d6b28 TL |
964 | }; |
965 | ||
966 | static struct clk gpt6_fck = { | |
967 | .name = "gpt6_fck", | |
b36ee724 | 968 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 969 | .parent = &func_32k_ck, |
d1b03f61 | 970 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
971 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
972 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
973 | .init = &omap2_init_clksel_parent, | |
974 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
975 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | |
976 | .clksel = omap24xx_gpt_clksel, | |
977 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
978 | }; |
979 | ||
980 | static struct clk gpt7_ick = { | |
981 | .name = "gpt7_ick", | |
b36ee724 | 982 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 983 | .parent = &l4_ck, |
e32744b0 PW |
984 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
985 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
986 | .recalc = &followparent_recalc, | |
046d6b28 TL |
987 | }; |
988 | ||
989 | static struct clk gpt7_fck = { | |
990 | .name = "gpt7_fck", | |
b36ee724 | 991 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 992 | .parent = &func_32k_ck, |
d1b03f61 | 993 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
994 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
995 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
996 | .init = &omap2_init_clksel_parent, | |
997 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
998 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | |
999 | .clksel = omap24xx_gpt_clksel, | |
1000 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1001 | }; |
1002 | ||
1003 | static struct clk gpt8_ick = { | |
1004 | .name = "gpt8_ick", | |
b36ee724 | 1005 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1006 | .parent = &l4_ck, |
d1b03f61 | 1007 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1008 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1009 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1010 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1011 | }; |
1012 | ||
1013 | static struct clk gpt8_fck = { | |
1014 | .name = "gpt8_fck", | |
b36ee724 | 1015 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1016 | .parent = &func_32k_ck, |
d1b03f61 | 1017 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1018 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1019 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1020 | .init = &omap2_init_clksel_parent, | |
1021 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1022 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | |
1023 | .clksel = omap24xx_gpt_clksel, | |
1024 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1025 | }; |
1026 | ||
1027 | static struct clk gpt9_ick = { | |
1028 | .name = "gpt9_ick", | |
b36ee724 | 1029 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1030 | .parent = &l4_ck, |
d1b03f61 | 1031 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1032 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1033 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1034 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1035 | }; |
1036 | ||
1037 | static struct clk gpt9_fck = { | |
1038 | .name = "gpt9_fck", | |
b36ee724 | 1039 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1040 | .parent = &func_32k_ck, |
d1b03f61 | 1041 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1042 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1043 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1044 | .init = &omap2_init_clksel_parent, | |
1045 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1046 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | |
1047 | .clksel = omap24xx_gpt_clksel, | |
1048 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1049 | }; |
1050 | ||
1051 | static struct clk gpt10_ick = { | |
1052 | .name = "gpt10_ick", | |
b36ee724 | 1053 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1054 | .parent = &l4_ck, |
d1b03f61 | 1055 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1056 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1057 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1058 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1059 | }; |
1060 | ||
1061 | static struct clk gpt10_fck = { | |
1062 | .name = "gpt10_fck", | |
b36ee724 | 1063 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1064 | .parent = &func_32k_ck, |
d1b03f61 | 1065 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1066 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1067 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1068 | .init = &omap2_init_clksel_parent, | |
1069 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1070 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | |
1071 | .clksel = omap24xx_gpt_clksel, | |
1072 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1073 | }; |
1074 | ||
1075 | static struct clk gpt11_ick = { | |
1076 | .name = "gpt11_ick", | |
b36ee724 | 1077 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1078 | .parent = &l4_ck, |
d1b03f61 | 1079 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1080 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1081 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1082 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1083 | }; |
1084 | ||
1085 | static struct clk gpt11_fck = { | |
1086 | .name = "gpt11_fck", | |
b36ee724 | 1087 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1088 | .parent = &func_32k_ck, |
d1b03f61 | 1089 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1090 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1091 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1092 | .init = &omap2_init_clksel_parent, | |
1093 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1094 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | |
1095 | .clksel = omap24xx_gpt_clksel, | |
1096 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1097 | }; |
1098 | ||
1099 | static struct clk gpt12_ick = { | |
1100 | .name = "gpt12_ick", | |
b36ee724 | 1101 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1102 | .parent = &l4_ck, |
d1b03f61 | 1103 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1104 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1105 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1106 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1107 | }; |
1108 | ||
1109 | static struct clk gpt12_fck = { | |
1110 | .name = "gpt12_fck", | |
b36ee724 | 1111 | .ops = &clkops_omap2_dflt_wait, |
f248076c | 1112 | .parent = &secure_32k_ck, |
d1b03f61 | 1113 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1114 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1115 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1116 | .init = &omap2_init_clksel_parent, | |
1117 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1118 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | |
1119 | .clksel = omap24xx_gpt_clksel, | |
1120 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1121 | }; |
1122 | ||
1123 | static struct clk mcbsp1_ick = { | |
b92c170d | 1124 | .name = "mcbsp1_ick", |
b36ee724 | 1125 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1126 | .parent = &l4_ck, |
d1b03f61 | 1127 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1128 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1129 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1130 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1131 | }; |
1132 | ||
b115b743 PW |
1133 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
1134 | { .div = 1, .val = 0, .flags = RATE_IN_24XX }, | |
1135 | { .div = 0 } | |
1136 | }; | |
1137 | ||
1138 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1139 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
1140 | { .div = 0 } | |
1141 | }; | |
1142 | ||
1143 | static const struct clksel mcbsp_fck_clksel[] = { | |
1144 | { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, | |
1145 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1146 | { .parent = NULL } | |
1147 | }; | |
1148 | ||
046d6b28 | 1149 | static struct clk mcbsp1_fck = { |
b92c170d | 1150 | .name = "mcbsp1_fck", |
b36ee724 | 1151 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1152 | .parent = &func_96m_ck, |
b115b743 | 1153 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1154 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1155 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1156 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
b115b743 PW |
1157 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
1158 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1159 | .clksel = mcbsp_fck_clksel, | |
1160 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1161 | }; |
1162 | ||
1163 | static struct clk mcbsp2_ick = { | |
b92c170d | 1164 | .name = "mcbsp2_ick", |
b36ee724 | 1165 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1166 | .parent = &l4_ck, |
d1b03f61 | 1167 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1168 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1169 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1170 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1171 | }; |
1172 | ||
1173 | static struct clk mcbsp2_fck = { | |
b92c170d | 1174 | .name = "mcbsp2_fck", |
b36ee724 | 1175 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1176 | .parent = &func_96m_ck, |
b115b743 | 1177 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1178 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1179 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1180 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
b115b743 PW |
1181 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
1182 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
1183 | .clksel = mcbsp_fck_clksel, | |
1184 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1185 | }; |
1186 | ||
1187 | static struct clk mcbsp3_ick = { | |
b92c170d | 1188 | .name = "mcbsp3_ick", |
b36ee724 | 1189 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1190 | .parent = &l4_ck, |
d1b03f61 | 1191 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1192 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1193 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1194 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1195 | }; |
1196 | ||
1197 | static struct clk mcbsp3_fck = { | |
b92c170d | 1198 | .name = "mcbsp3_fck", |
b36ee724 | 1199 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1200 | .parent = &func_96m_ck, |
b115b743 | 1201 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1202 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1204 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
b115b743 PW |
1205 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
1206 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
1207 | .clksel = mcbsp_fck_clksel, | |
1208 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1209 | }; |
1210 | ||
1211 | static struct clk mcbsp4_ick = { | |
b92c170d | 1212 | .name = "mcbsp4_ick", |
b36ee724 | 1213 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1214 | .parent = &l4_ck, |
d1b03f61 | 1215 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1216 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1217 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1218 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1219 | }; |
1220 | ||
1221 | static struct clk mcbsp4_fck = { | |
b92c170d | 1222 | .name = "mcbsp4_fck", |
b36ee724 | 1223 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1224 | .parent = &func_96m_ck, |
b115b743 | 1225 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1226 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1228 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
b115b743 PW |
1229 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
1230 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
1231 | .clksel = mcbsp_fck_clksel, | |
1232 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1233 | }; |
1234 | ||
1235 | static struct clk mcbsp5_ick = { | |
b92c170d | 1236 | .name = "mcbsp5_ick", |
b36ee724 | 1237 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1238 | .parent = &l4_ck, |
d1b03f61 | 1239 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1240 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1241 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1242 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1243 | }; |
1244 | ||
1245 | static struct clk mcbsp5_fck = { | |
b92c170d | 1246 | .name = "mcbsp5_fck", |
b36ee724 | 1247 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1248 | .parent = &func_96m_ck, |
b115b743 | 1249 | .init = &omap2_init_clksel_parent, |
d1b03f61 | 1250 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1252 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
b115b743 PW |
1253 | .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), |
1254 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1255 | .clksel = mcbsp_fck_clksel, | |
1256 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1257 | }; |
1258 | ||
1259 | static struct clk mcspi1_ick = { | |
b92c170d | 1260 | .name = "mcspi1_ick", |
b36ee724 | 1261 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1262 | .parent = &l4_ck, |
d1b03f61 | 1263 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1265 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1266 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1267 | }; |
1268 | ||
1269 | static struct clk mcspi1_fck = { | |
b92c170d | 1270 | .name = "mcspi1_fck", |
b36ee724 | 1271 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1272 | .parent = &func_48m_ck, |
d1b03f61 | 1273 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1274 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1275 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1276 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1277 | }; |
1278 | ||
1279 | static struct clk mcspi2_ick = { | |
b92c170d | 1280 | .name = "mcspi2_ick", |
b36ee724 | 1281 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1282 | .parent = &l4_ck, |
d1b03f61 | 1283 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1284 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1285 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1286 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1287 | }; |
1288 | ||
1289 | static struct clk mcspi2_fck = { | |
b92c170d | 1290 | .name = "mcspi2_fck", |
b36ee724 | 1291 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1292 | .parent = &func_48m_ck, |
d1b03f61 | 1293 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1295 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1296 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1297 | }; |
1298 | ||
1299 | static struct clk mcspi3_ick = { | |
b92c170d | 1300 | .name = "mcspi3_ick", |
b36ee724 | 1301 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1302 | .parent = &l4_ck, |
d1b03f61 | 1303 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1304 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1305 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1306 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1307 | }; |
1308 | ||
1309 | static struct clk mcspi3_fck = { | |
b92c170d | 1310 | .name = "mcspi3_fck", |
b36ee724 | 1311 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1312 | .parent = &func_48m_ck, |
d1b03f61 | 1313 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1314 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1315 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1316 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1317 | }; |
1318 | ||
1319 | static struct clk uart1_ick = { | |
1320 | .name = "uart1_ick", | |
b36ee724 | 1321 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1322 | .parent = &l4_ck, |
d1b03f61 | 1323 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1324 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1325 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1326 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1327 | }; |
1328 | ||
1329 | static struct clk uart1_fck = { | |
1330 | .name = "uart1_fck", | |
b36ee724 | 1331 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1332 | .parent = &func_48m_ck, |
d1b03f61 | 1333 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1334 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1335 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1336 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1337 | }; |
1338 | ||
1339 | static struct clk uart2_ick = { | |
1340 | .name = "uart2_ick", | |
b36ee724 | 1341 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1342 | .parent = &l4_ck, |
d1b03f61 | 1343 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1344 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1345 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1346 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1347 | }; |
1348 | ||
1349 | static struct clk uart2_fck = { | |
1350 | .name = "uart2_fck", | |
b36ee724 | 1351 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1352 | .parent = &func_48m_ck, |
d1b03f61 | 1353 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1354 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1355 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1356 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1357 | }; |
1358 | ||
1359 | static struct clk uart3_ick = { | |
1360 | .name = "uart3_ick", | |
b36ee724 | 1361 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1362 | .parent = &l4_ck, |
d1b03f61 | 1363 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1364 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1365 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1366 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1367 | }; |
1368 | ||
1369 | static struct clk uart3_fck = { | |
1370 | .name = "uart3_fck", | |
b36ee724 | 1371 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1372 | .parent = &func_48m_ck, |
d1b03f61 | 1373 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1374 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1375 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1376 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1377 | }; |
1378 | ||
1379 | static struct clk gpios_ick = { | |
1380 | .name = "gpios_ick", | |
b36ee724 | 1381 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1382 | .parent = &l4_ck, |
d1b03f61 | 1383 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1384 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1385 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1386 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1387 | }; |
1388 | ||
1389 | static struct clk gpios_fck = { | |
1390 | .name = "gpios_fck", | |
b36ee724 | 1391 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1392 | .parent = &func_32k_ck, |
d1b03f61 | 1393 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1394 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1395 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1396 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1397 | }; |
1398 | ||
1399 | static struct clk mpu_wdt_ick = { | |
1400 | .name = "mpu_wdt_ick", | |
b36ee724 | 1401 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1402 | .parent = &l4_ck, |
d1b03f61 | 1403 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1404 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1405 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1406 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1407 | }; |
1408 | ||
1409 | static struct clk mpu_wdt_fck = { | |
1410 | .name = "mpu_wdt_fck", | |
b36ee724 | 1411 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1412 | .parent = &func_32k_ck, |
d1b03f61 | 1413 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1414 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1415 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1416 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1417 | }; |
1418 | ||
1419 | static struct clk sync_32k_ick = { | |
1420 | .name = "sync_32k_ick", | |
b36ee724 | 1421 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1422 | .parent = &l4_ck, |
8ad8ff65 | 1423 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1424 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1425 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1426 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1427 | .recalc = &followparent_recalc, | |
046d6b28 | 1428 | }; |
d1b03f61 | 1429 | |
046d6b28 TL |
1430 | static struct clk wdt1_ick = { |
1431 | .name = "wdt1_ick", | |
b36ee724 | 1432 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1433 | .parent = &l4_ck, |
d1b03f61 | 1434 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1435 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1436 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1437 | .recalc = &followparent_recalc, | |
046d6b28 | 1438 | }; |
d1b03f61 | 1439 | |
046d6b28 TL |
1440 | static struct clk omapctrl_ick = { |
1441 | .name = "omapctrl_ick", | |
b36ee724 | 1442 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1443 | .parent = &l4_ck, |
8ad8ff65 | 1444 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1445 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1446 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1447 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1448 | .recalc = &followparent_recalc, | |
046d6b28 | 1449 | }; |
d1b03f61 | 1450 | |
046d6b28 TL |
1451 | static struct clk icr_ick = { |
1452 | .name = "icr_ick", | |
b36ee724 | 1453 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1454 | .parent = &l4_ck, |
d1b03f61 | 1455 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1456 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1457 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | |
1458 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1459 | }; |
1460 | ||
1461 | static struct clk cam_ick = { | |
1462 | .name = "cam_ick", | |
bc51da4e | 1463 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1464 | .parent = &l4_ck, |
d1b03f61 | 1465 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1467 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1468 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1469 | }; |
1470 | ||
d1b03f61 PW |
1471 | /* |
1472 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | |
1473 | * split into two separate clocks, since the parent clocks are different | |
1474 | * and the clockdomains are also different. | |
1475 | */ | |
046d6b28 TL |
1476 | static struct clk cam_fck = { |
1477 | .name = "cam_fck", | |
bc51da4e | 1478 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1479 | .parent = &func_96m_ck, |
d1b03f61 | 1480 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1481 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1482 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1483 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1484 | }; |
1485 | ||
1486 | static struct clk mailboxes_ick = { | |
1487 | .name = "mailboxes_ick", | |
b36ee724 | 1488 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1489 | .parent = &l4_ck, |
d1b03f61 | 1490 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1491 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1492 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1493 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1494 | }; |
1495 | ||
1496 | static struct clk wdt4_ick = { | |
1497 | .name = "wdt4_ick", | |
b36ee724 | 1498 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1499 | .parent = &l4_ck, |
d1b03f61 | 1500 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1501 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1502 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1503 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1504 | }; |
1505 | ||
1506 | static struct clk wdt4_fck = { | |
1507 | .name = "wdt4_fck", | |
b36ee724 | 1508 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1509 | .parent = &func_32k_ck, |
d1b03f61 | 1510 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1511 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1512 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1513 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1514 | }; |
1515 | ||
046d6b28 TL |
1516 | static struct clk mspro_ick = { |
1517 | .name = "mspro_ick", | |
b36ee724 | 1518 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1519 | .parent = &l4_ck, |
d1b03f61 | 1520 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1521 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1522 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1523 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1524 | }; |
1525 | ||
1526 | static struct clk mspro_fck = { | |
1527 | .name = "mspro_fck", | |
b36ee724 | 1528 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1529 | .parent = &func_96m_ck, |
d1b03f61 | 1530 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1531 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1532 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1533 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1534 | }; |
1535 | ||
046d6b28 TL |
1536 | static struct clk fac_ick = { |
1537 | .name = "fac_ick", | |
b36ee724 | 1538 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1539 | .parent = &l4_ck, |
d1b03f61 | 1540 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1541 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1542 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1543 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1544 | }; |
1545 | ||
1546 | static struct clk fac_fck = { | |
1547 | .name = "fac_fck", | |
b36ee724 | 1548 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1549 | .parent = &func_12m_ck, |
d1b03f61 | 1550 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1551 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1552 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1553 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1554 | }; |
1555 | ||
046d6b28 TL |
1556 | static struct clk hdq_ick = { |
1557 | .name = "hdq_ick", | |
b36ee724 | 1558 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1559 | .parent = &l4_ck, |
d1b03f61 | 1560 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1561 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1562 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1563 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1564 | }; |
1565 | ||
1566 | static struct clk hdq_fck = { | |
1567 | .name = "hdq_fck", | |
b36ee724 | 1568 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1569 | .parent = &func_12m_ck, |
d1b03f61 | 1570 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1572 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1573 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1574 | }; |
1575 | ||
81b34fbe PW |
1576 | /* |
1577 | * XXX This is marked as a 2420-only define, but it claims to be present | |
1578 | * on 2430 also. Double-check. | |
1579 | */ | |
046d6b28 | 1580 | static struct clk i2c2_ick = { |
b92c170d | 1581 | .name = "i2c2_ick", |
b36ee724 | 1582 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1583 | .parent = &l4_ck, |
d1b03f61 | 1584 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1586 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1587 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1588 | }; |
1589 | ||
046d6b28 | 1590 | static struct clk i2chs2_fck = { |
b92c170d | 1591 | .name = "i2chs2_fck", |
3dc21975 | 1592 | .ops = &clkops_omap2430_i2chs_wait, |
046d6b28 | 1593 | .parent = &func_96m_ck, |
d1b03f61 | 1594 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1595 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1596 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
1597 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1598 | }; |
1599 | ||
81b34fbe PW |
1600 | /* |
1601 | * XXX This is marked as a 2420-only define, but it claims to be present | |
1602 | * on 2430 also. Double-check. | |
1603 | */ | |
046d6b28 | 1604 | static struct clk i2c1_ick = { |
b92c170d | 1605 | .name = "i2c1_ick", |
b36ee724 | 1606 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1607 | .parent = &l4_ck, |
d1b03f61 | 1608 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1609 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1610 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1611 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1612 | }; |
1613 | ||
046d6b28 | 1614 | static struct clk i2chs1_fck = { |
b92c170d | 1615 | .name = "i2chs1_fck", |
3dc21975 | 1616 | .ops = &clkops_omap2430_i2chs_wait, |
046d6b28 | 1617 | .parent = &func_96m_ck, |
d1b03f61 | 1618 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1619 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1620 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
1621 | .recalc = &followparent_recalc, | |
1622 | }; | |
1623 | ||
1624 | static struct clk gpmc_fck = { | |
1625 | .name = "gpmc_fck", | |
897dcded | 1626 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1627 | .parent = &core_l3_ck, |
8ad8ff65 | 1628 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1629 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1630 | .recalc = &followparent_recalc, |
1631 | }; | |
1632 | ||
1633 | static struct clk sdma_fck = { | |
1634 | .name = "sdma_fck", | |
897dcded | 1635 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1636 | .parent = &core_l3_ck, |
d1b03f61 | 1637 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1638 | .recalc = &followparent_recalc, |
1639 | }; | |
1640 | ||
1641 | static struct clk sdma_ick = { | |
1642 | .name = "sdma_ick", | |
897dcded | 1643 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1644 | .parent = &l4_ck, |
d1b03f61 | 1645 | .clkdm_name = "core_l3_clkdm", |
e32744b0 | 1646 | .recalc = &followparent_recalc, |
046d6b28 TL |
1647 | }; |
1648 | ||
046d6b28 TL |
1649 | static struct clk sdrc_ick = { |
1650 | .name = "sdrc_ick", | |
b36ee724 | 1651 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1652 | .parent = &l4_ck, |
8ad8ff65 | 1653 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1654 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1655 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1656 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | |
1657 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1658 | }; |
1659 | ||
1660 | static struct clk des_ick = { | |
1661 | .name = "des_ick", | |
b36ee724 | 1662 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1663 | .parent = &l4_ck, |
d1b03f61 | 1664 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1666 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
1667 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1668 | }; |
1669 | ||
1670 | static struct clk sha_ick = { | |
1671 | .name = "sha_ick", | |
b36ee724 | 1672 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1673 | .parent = &l4_ck, |
d1b03f61 | 1674 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1676 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1677 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1678 | }; |
1679 | ||
1680 | static struct clk rng_ick = { | |
1681 | .name = "rng_ick", | |
b36ee724 | 1682 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1683 | .parent = &l4_ck, |
d1b03f61 | 1684 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1685 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1686 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1687 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1688 | }; |
1689 | ||
1690 | static struct clk aes_ick = { | |
1691 | .name = "aes_ick", | |
b36ee724 | 1692 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1693 | .parent = &l4_ck, |
d1b03f61 | 1694 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1695 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1696 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
1697 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1698 | }; |
1699 | ||
1700 | static struct clk pka_ick = { | |
1701 | .name = "pka_ick", | |
b36ee724 | 1702 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1703 | .parent = &l4_ck, |
d1b03f61 | 1704 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1705 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1706 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1707 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1708 | }; |
1709 | ||
1710 | static struct clk usb_fck = { | |
1711 | .name = "usb_fck", | |
b36ee724 | 1712 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1713 | .parent = &func_48m_ck, |
d1b03f61 | 1714 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1715 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1716 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1717 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1718 | }; |
1719 | ||
1720 | static struct clk usbhs_ick = { | |
1721 | .name = "usbhs_ick", | |
b36ee724 | 1722 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 1723 | .parent = &core_l3_ck, |
d1b03f61 | 1724 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1725 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1726 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | |
1727 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1728 | }; |
1729 | ||
1730 | static struct clk mmchs1_ick = { | |
b92c170d | 1731 | .name = "mmchs1_ick", |
b36ee724 | 1732 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1733 | .parent = &l4_ck, |
d1b03f61 | 1734 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1735 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1736 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1737 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1738 | }; |
1739 | ||
1740 | static struct clk mmchs1_fck = { | |
b92c170d | 1741 | .name = "mmchs1_fck", |
b36ee724 | 1742 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1743 | .parent = &func_96m_ck, |
d1b03f61 | 1744 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1745 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1746 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1747 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1748 | }; |
1749 | ||
1750 | static struct clk mmchs2_ick = { | |
b92c170d | 1751 | .name = "mmchs2_ick", |
b36ee724 | 1752 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1753 | .parent = &l4_ck, |
d1b03f61 | 1754 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1755 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1756 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1757 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1758 | }; |
1759 | ||
1760 | static struct clk mmchs2_fck = { | |
b92c170d | 1761 | .name = "mmchs2_fck", |
b36ee724 | 1762 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1763 | .parent = &func_96m_ck, |
e32744b0 PW |
1764 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1765 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1766 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1767 | }; |
1768 | ||
1769 | static struct clk gpio5_ick = { | |
1770 | .name = "gpio5_ick", | |
b36ee724 | 1771 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1772 | .parent = &l4_ck, |
d1b03f61 | 1773 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1774 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1775 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1776 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1777 | }; |
1778 | ||
1779 | static struct clk gpio5_fck = { | |
1780 | .name = "gpio5_fck", | |
b36ee724 | 1781 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1782 | .parent = &func_32k_ck, |
d1b03f61 | 1783 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1784 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1785 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1786 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1787 | }; |
1788 | ||
1789 | static struct clk mdm_intc_ick = { | |
1790 | .name = "mdm_intc_ick", | |
b36ee724 | 1791 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1792 | .parent = &l4_ck, |
d1b03f61 | 1793 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1794 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1795 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | |
1796 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1797 | }; |
1798 | ||
1799 | static struct clk mmchsdb1_fck = { | |
b92c170d | 1800 | .name = "mmchsdb1_fck", |
b36ee724 | 1801 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1802 | .parent = &func_32k_ck, |
d1b03f61 | 1803 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1804 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1805 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | |
1806 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1807 | }; |
1808 | ||
1809 | static struct clk mmchsdb2_fck = { | |
b92c170d | 1810 | .name = "mmchsdb2_fck", |
b36ee724 | 1811 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1812 | .parent = &func_32k_ck, |
d1b03f61 | 1813 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1815 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | |
1816 | .recalc = &followparent_recalc, | |
046d6b28 | 1817 | }; |
e32744b0 | 1818 | |
046d6b28 TL |
1819 | /* |
1820 | * This clock is a composite clock which does entire set changes then | |
1821 | * forces a rebalance. It keys on the MPU speed, but it really could | |
1822 | * be any key speed part of a set in the rate table. | |
1823 | * | |
1824 | * to really change a set, you need memory table sets which get changed | |
1825 | * in sram, pre-notifiers & post notifiers, changing the top set, without | |
1826 | * having low level display recalc's won't work... this is why dpm notifiers | |
1827 | * work, isr's off, walk a list of clocks already _off_ and not messing with | |
1828 | * the bus. | |
1829 | * | |
1830 | * This clock should have no parent. It embodies the entire upper level | |
1831 | * active set. A parent will mess up some of the init also. | |
1832 | */ | |
1833 | static struct clk virt_prcm_set = { | |
1834 | .name = "virt_prcm_set", | |
897dcded | 1835 | .ops = &clkops_null, |
046d6b28 | 1836 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
e32744b0 | 1837 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
046d6b28 TL |
1838 | .set_rate = &omap2_select_table_rate, |
1839 | .round_rate = &omap2_round_to_table_rate, | |
1840 | }; | |
e32744b0 | 1841 | |
d8a94458 PW |
1842 | |
1843 | /* | |
1844 | * clkdev integration | |
1845 | */ | |
1846 | ||
81b34fbe | 1847 | static struct omap_clk omap2430_clks[] = { |
d8a94458 | 1848 | /* external root sources */ |
81b34fbe PW |
1849 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), |
1850 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), | |
1851 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), | |
1852 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), | |
1853 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), | |
b115b743 PW |
1854 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), |
1855 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), | |
1856 | CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), | |
1857 | CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), | |
1858 | CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), | |
1859 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), | |
d8a94458 | 1860 | /* internal analog sources */ |
81b34fbe PW |
1861 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
1862 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), | |
1863 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), | |
d8a94458 | 1864 | /* internal prcm root sources */ |
81b34fbe PW |
1865 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
1866 | CLK(NULL, "core_ck", &core_ck, CK_243X), | |
b115b743 PW |
1867 | CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), |
1868 | CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), | |
1869 | CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), | |
1870 | CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), | |
1871 | CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), | |
81b34fbe PW |
1872 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
1873 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), | |
1874 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), | |
1875 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), | |
1876 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), | |
1877 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), | |
1878 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), | |
d8a94458 | 1879 | /* mpu domain clocks */ |
81b34fbe | 1880 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), |
d8a94458 | 1881 | /* dsp domain clocks */ |
81b34fbe PW |
1882 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), |
1883 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X), | |
d8a94458 | 1884 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
d8a94458 | 1885 | /* GFX domain clocks */ |
81b34fbe PW |
1886 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), |
1887 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), | |
1888 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), | |
d8a94458 PW |
1889 | /* Modem domain clocks */ |
1890 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | |
1891 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | |
1892 | /* DSS domain clocks */ | |
81b34fbe PW |
1893 | CLK("omapdss", "ick", &dss_ick, CK_243X), |
1894 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), | |
1895 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), | |
1896 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), | |
d8a94458 | 1897 | /* L3 domain clocks */ |
81b34fbe PW |
1898 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), |
1899 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), | |
1900 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), | |
d8a94458 | 1901 | /* L4 domain clocks */ |
81b34fbe PW |
1902 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), |
1903 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), | |
d8a94458 | 1904 | /* virtual meta-group clock */ |
81b34fbe | 1905 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), |
d8a94458 | 1906 | /* general l4 interface ck, multi-parent functional clk */ |
81b34fbe PW |
1907 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), |
1908 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), | |
1909 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), | |
1910 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), | |
1911 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), | |
1912 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), | |
1913 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), | |
1914 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), | |
1915 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), | |
1916 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), | |
1917 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), | |
1918 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), | |
1919 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), | |
1920 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), | |
1921 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), | |
1922 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), | |
1923 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), | |
1924 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), | |
1925 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), | |
1926 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), | |
1927 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), | |
1928 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), | |
1929 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), | |
1930 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), | |
1931 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), | |
1932 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), | |
1933 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), | |
1934 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), | |
d8a94458 PW |
1935 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
1936 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | |
1937 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | |
1938 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | |
1939 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | |
1940 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | |
81b34fbe PW |
1941 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), |
1942 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), | |
1943 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), | |
1944 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), | |
d8a94458 PW |
1945 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
1946 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | |
81b34fbe PW |
1947 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), |
1948 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), | |
1949 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), | |
1950 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), | |
1951 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), | |
1952 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), | |
1953 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), | |
1954 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), | |
1955 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), | |
1956 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), | |
1957 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), | |
1958 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), | |
1959 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), | |
d8a94458 | 1960 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
81b34fbe PW |
1961 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), |
1962 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), | |
1963 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), | |
1964 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), | |
1965 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), | |
1966 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), | |
1967 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), | |
1968 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), | |
1969 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), | |
1970 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), | |
1971 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), | |
f7bb0d9a BC |
1972 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), |
1973 | CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X), | |
1974 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), | |
1975 | CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X), | |
81b34fbe PW |
1976 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
1977 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), | |
1978 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), | |
d8a94458 | 1979 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
81b34fbe | 1980 | CLK(NULL, "des_ick", &des_ick, CK_243X), |
ee5500c4 | 1981 | CLK("omap-sham", "ick", &sha_ick, CK_243X), |
81b34fbe | 1982 | CLK("omap_rng", "ick", &rng_ick, CK_243X), |
82a0c149 | 1983 | CLK("omap-aes", "ick", &aes_ick, CK_243X), |
81b34fbe PW |
1984 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), |
1985 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), | |
03491761 | 1986 | CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), |
d8a94458 PW |
1987 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
1988 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | |
1989 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | |
1990 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | |
1991 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | |
1992 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | |
1993 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | |
1994 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | |
1995 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | |
1996 | }; | |
1997 | ||
1998 | /* | |
1999 | * init code | |
2000 | */ | |
2001 | ||
81b34fbe | 2002 | int __init omap2430_clk_init(void) |
d8a94458 PW |
2003 | { |
2004 | const struct prcm_config *prcm; | |
2005 | struct omap_clk *c; | |
2006 | u32 clkrate; | |
81b34fbe PW |
2007 | |
2008 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
2009 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); | |
2010 | cpu_mask = RATE_IN_243X; | |
2011 | rate_table = omap2430_rate_table; | |
d8a94458 PW |
2012 | |
2013 | clk_init(&omap2_clk_functions); | |
2014 | ||
81b34fbe PW |
2015 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
2016 | c++) | |
d8a94458 PW |
2017 | clk_preinit(c->lk.clk); |
2018 | ||
2019 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | |
2020 | propagate_rate(&osc_ck); | |
44da0a51 | 2021 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
d8a94458 PW |
2022 | propagate_rate(&sys_ck); |
2023 | ||
81b34fbe PW |
2024 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); |
2025 | c++) { | |
2026 | clkdev_add(&c->lk); | |
2027 | clk_register(c->lk.clk); | |
2028 | omap2_init_clk_clkdm(c->lk.clk); | |
2029 | } | |
d8a94458 PW |
2030 | |
2031 | /* Check the MPU rate set by bootloader */ | |
2032 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | |
2033 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
2034 | if (!(prcm->flags & cpu_mask)) | |
2035 | continue; | |
2036 | if (prcm->xtal_speed != sys_ck.rate) | |
2037 | continue; | |
2038 | if (prcm->dpll_speed <= clkrate) | |
2039 | break; | |
2040 | } | |
2041 | curr_prcm_set = prcm; | |
2042 | ||
2043 | recalculate_root_clocks(); | |
2044 | ||
81b34fbe PW |
2045 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
2046 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
2047 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
d8a94458 PW |
2048 | |
2049 | /* | |
2050 | * Only enable those clocks we will need, let the drivers | |
2051 | * enable other clocks as necessary | |
2052 | */ | |
2053 | clk_enable_init_clocks(); | |
2054 | ||
2055 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | |
2056 | vclk = clk_get(NULL, "virt_prcm_set"); | |
2057 | sclk = clk_get(NULL, "sys_ck"); | |
2058 | dclk = clk_get(NULL, "dpll_ck"); | |
2059 | ||
2060 | return 0; | |
2061 | } | |
6b8858a9 | 2062 |