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[ARM] 5590/1: Add basic support for ST Nomadik 8815 SoC and evaluation board
[deliverable/linux.git] / arch / arm / mach-omap2 / clock24xx.c
CommitLineData
046d6b28
TL		 1/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
a16e9703
TL		 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
046d6b28 6 *
a16e9703
TL		 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
046d6b28 10 *
a16e9703
TL		 11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
046d6b28
TL		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
6b8858a9
PW		 18#undef DEBUG
19
046d6b28
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/device.h>
23#include <linux/list.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
f8ce2547 26#include <linux/clk.h>
6b8858a9
PW		 27#include <linux/io.h>
28#include <linux/cpufreq.h>
fbd3bdb2 29#include <linux/bitops.h>
046d6b28 30
a09e64fb
RK		 31#include <mach/clock.h>
32#include <mach/sram.h>
76631486 33#include <asm/div64.h>
8ad8ff65 34#include <asm/clkdev.h>
046d6b28 35
f8de9b2c 36#include <mach/sdrc.h>
6b8858a9 37#include "clock.h"
6b8858a9
PW		 38#include "prm.h"
39#include "prm-regbits-24xx.h"
40#include "cm.h"
41#include "cm-regbits-24xx.h"
046d6b28 42
548d8495
RK		 43static const struct clkops clkops_oscck;
44static const struct clkops clkops_fixed;
45
46#include "clock24xx.h"
47
8ad8ff65
RK		 48struct omap_clk {
49 u32 cpu;
50 struct clk_lookup lk;
51};
52
53#define CLK(dev, con, ck, cp) \
54 { \
55 .cpu = cp, \
56 .lk = { \
57 .dev_id = dev, \
58 .con_id = con, \
59 .clk = ck, \
60 }, \
61 }
62
15ca78f7
PW		 63#define CK_243X RATE_IN_243X
64#define CK_242X RATE_IN_242X
8ad8ff65
RK		 65
66static struct omap_clk omap24xx_clks[] = {
67 /* external root sources */
68 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
f248076c 69 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
8ad8ff65
RK		 70 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
71 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
72 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
73 /* internal analog sources */
74 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
75 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
76 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
77 /* internal prcm root sources */
78 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
79 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
80 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
81 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
82 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
83 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
84 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
85 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
86 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
87 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
88 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
89 /* mpu domain clocks */
90 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
91 /* dsp domain clocks */
92 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
93 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
94 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
95 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
96 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
97 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
98 /* GFX domain clocks */
99 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
100 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
101 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
102 /* Modem domain clocks */
103 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
104 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
105 /* DSS domain clocks */
005187ee
TL		 106 CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X),
107 CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
108 CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
109 CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
8ad8ff65
RK		 110 /* L3 domain clocks */
111 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
112 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
113 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
114 /* L4 domain clocks */
115 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
9299fd85 116 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
8ad8ff65
RK		 117 /* virtual meta-group clock */
118 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
119 /* general l4 interface ck, multi-parent functional clk */
120 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
121 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
122 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
123 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
124 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
125 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
126 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
127 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
128 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
129 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
130 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
131 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
132 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
133 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
134 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
135 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
136 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
137 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
138 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
139 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
140 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
141 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
142 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
143 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
b820ce4e
RK		 144 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
145 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
146 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
147 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
148 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
149 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
150 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
151 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
152 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
153 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
1b5715ec
RK		 154 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
155 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
156 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
157 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
158 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
159 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
8ad8ff65
RK		 160 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
161 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
162 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
163 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
164 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
165 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
166 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
167 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
39a80c7f
RK		 168 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
169 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
8ad8ff65
RK		 170 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
171 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
172 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
173 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
6c5dbb40
RK		 174 CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
175 CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
8ad8ff65
RK		 176 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
177 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
178 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
179 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
180 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
181 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
182 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
5c9e02b1
RK		 183 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
184 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
8ad8ff65
RK		 185 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
186 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
187 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
188 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
cc51c9d4
RK		 189 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
190 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
1d14de08
RK		 191 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
192 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
193 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
194 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
195 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
196 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
8ad8ff65
RK		 197 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
198 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
199 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
200 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
201 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
202 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
203 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
204 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
eeec7c8d 205 CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
8ad8ff65
RK		 206 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
207 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
208 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
4ea60b0c 209 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
6f7607cc
RK		 210 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
211 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
212 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
213 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
8ad8ff65
RK		 214 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
215 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
216 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
217 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
218 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
219};
220
6b8858a9
PW		 221/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
222#define EN_APLL_STOPPED 0
223#define EN_APLL_LOCKED 3
ddc32a87 224
6b8858a9
PW		 225/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
226#define APLLS_CLKIN_19_2MHZ 0
227#define APLLS_CLKIN_13MHZ 2
228#define APLLS_CLKIN_12MHZ 3
229
230/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
046d6b28
TL		 231
232static struct prcm_config *curr_prcm_set;
ae78dcf7
TL		 233static struct clk *vclk;
234static struct clk *sclk;
046d6b28 235
8e3bd351
TL		 236static void __iomem *prcm_clksrc_ctrl;
237
046d6b28 238/*-------------------------------------------------------------------------
6b8858a9 239 * Omap24xx specific clock functions
046d6b28
TL		 240 *-------------------------------------------------------------------------*/
241
c0bf3132
RK		 242/**
243 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
244 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
245 *
246 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
247 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
248 * (the latter is unusual). This currently should be called with
249 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
250 * core_ck.
251 */
252static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
a16e9703 253{
c0bf3132
RK		 254 long long core_clk;
255 u32 v;
a16e9703 256
c0bf3132 257 core_clk = omap2_get_dpll_rate(clk);
a16e9703 258
c0bf3132
RK		 259 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
260 v &= OMAP24XX_CORE_CLK_SRC_MASK;
261
262 if (v == CORE_CLK_SRC_32K)
263 core_clk = 32768;
264 else
265 core_clk *= v;
a16e9703 266
c0bf3132 267 return core_clk;
a16e9703
TL		 268}
269
6b8858a9
PW		 270static int omap2_enable_osc_ck(struct clk *clk)
271{
272 u32 pcc;
273
8e3bd351 274 pcc = __raw_readl(prcm_clksrc_ctrl);
6b8858a9 275
8e3bd351 276 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
6b8858a9
PW		 277
278 return 0;
279}
280
281static void omap2_disable_osc_ck(struct clk *clk)
282{
283 u32 pcc;
284
8e3bd351 285 pcc = __raw_readl(prcm_clksrc_ctrl);
6b8858a9 286
8e3bd351 287 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
6b8858a9
PW		 288}
289
548d8495
RK		 290static const struct clkops clkops_oscck = {
291 .enable = &omap2_enable_osc_ck,
292 .disable = &omap2_disable_osc_ck,
293};
294
6b8858a9 295#ifdef OLD_CK
046d6b28
TL		 296/* Recalculate SYST_CLK */
297static void omap2_sys_clk_recalc(struct clk * clk)
298{
299 u32 div = PRCM_CLKSRC_CTRL;
300 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
301 div >>= clk->rate_offset;
302 clk->rate = (clk->parent->rate / div);
303 propagate_rate(clk);
304}
6b8858a9 305#endif /* OLD_CK */
046d6b28 306
046d6b28 307/* Enable an APLL if off */
6b8858a9 308static int omap2_clk_fixed_enable(struct clk *clk)
046d6b28 309{
6b8858a9 310 u32 cval, apll_mask;
046d6b28 311
6b8858a9 312 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
046d6b28 313
6b8858a9 314 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
046d6b28 315
6b8858a9
PW		 316 if ((cval & apll_mask) == apll_mask)
317 return 0; /* apll already enabled */
046d6b28 318
6b8858a9
PW		 319 cval &= ~apll_mask;
320 cval |= apll_mask;
321 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28
TL		 322
323 if (clk == &apll96_ck)
6b8858a9 324 cval = OMAP24XX_ST_96M_APLL;
046d6b28 325 else if (clk == &apll54_ck)
6b8858a9 326 cval = OMAP24XX_ST_54M_APLL;
046d6b28 327
6b8858a9
PW		 328 omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
329 clk->name);
330
331 /*
332 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
333 * fails?
334 */
335 return 0;
046d6b28
TL		 336}
337
046d6b28
TL		 338/* Stop APLL */
339static void omap2_clk_fixed_disable(struct clk *clk)
340{
341 u32 cval;
342
6b8858a9
PW		 343 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
344 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
345 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28
TL		 346}
347
548d8495
RK		 348static const struct clkops clkops_fixed = {
349 .enable = &omap2_clk_fixed_enable,
350 .disable = &omap2_clk_fixed_disable,
351};
352
046d6b28
TL		 353/*
354 * Uses the current prcm set to tell if a rate is valid.
355 * You can go slower, but not faster within a given rate set.
356 */
fecb494b 357static long omap2_dpllcore_round_rate(unsigned long target_rate)
046d6b28 358{
6b8858a9 359 u32 high, low, core_clk_src;
046d6b28 360
6b8858a9
PW		 361 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
362 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
363
364 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
046d6b28
TL		 365 high = curr_prcm_set->dpll_speed * 2;
366 low = curr_prcm_set->dpll_speed;
367 } else { /* DPLL clockout x 2 */
368 high = curr_prcm_set->dpll_speed;
369 low = curr_prcm_set->dpll_speed / 2;
370 }
371
372#ifdef DOWN_VARIABLE_DPLL
373 if (target_rate > high)
374 return high;
375 else
376 return target_rate;
377#else
378 if (target_rate > low)
379 return high;
380 else
381 return low;
382#endif
383
384}
385
8b9dbc16 386static unsigned long omap2_dpllcore_recalc(struct clk *clk)
6b8858a9 387{
c0bf3132 388 return omap2xxx_clk_get_core_rate(clk);
6b8858a9 389}
046d6b28 390
88b8ba90 391static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
046d6b28 392{
6b8858a9 393 u32 cur_rate, low, mult, div, valid_rate, done_rate;
046d6b28
TL		 394 u32 bypass = 0;
395 struct prcm_config tmpset;
6b8858a9 396 const struct dpll_data *dd;
046d6b28 397
c0bf3132 398 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
6b8858a9
PW		 399 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
400 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28
TL		 401
402 if ((rate == (cur_rate / 2)) && (mult == 2)) {
f2ab9977 403 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
046d6b28 404 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
f2ab9977 405 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28 406 } else if (rate != cur_rate) {
88b8ba90 407 valid_rate = omap2_dpllcore_round_rate(rate);
046d6b28 408 if (valid_rate != rate)
883992bd 409 return -EINVAL;
046d6b28 410
6b8858a9 411 if (mult == 1)
046d6b28
TL		 412 low = curr_prcm_set->dpll_speed;
413 else
414 low = curr_prcm_set->dpll_speed / 2;
415
6b8858a9
PW		 416 dd = clk->dpll_data;
417 if (!dd)
883992bd 418 return -EINVAL;
6b8858a9
PW		 419
420 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
421 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
422 dd->div1_mask);
046d6b28 423 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
6b8858a9
PW		 424 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
425 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28 426 if (rate > low) {
6b8858a9 427 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
046d6b28 428 mult = ((rate / 2) / 1000000);
6b8858a9 429 done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28 430 } else {
6b8858a9 431 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
046d6b28 432 mult = (rate / 1000000);
6b8858a9 433 done_rate = CORE_CLK_SRC_DPLL;
046d6b28 434 }
6b8858a9
PW		 435 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
436 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
046d6b28
TL		 437
438 /* Worst case */
6b8858a9 439 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
046d6b28
TL		 440
441 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
442 bypass = 1;
443
f2ab9977
PW		 444 /* For omap2xxx_sdrc_init_params() */
445 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 446
447 /* Force dll lock mode */
448 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
449 bypass);
450
451 /* Errata: ret dll entry state */
f2ab9977
PW		 452 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
453 omap2xxx_sdrc_reprogram(done_rate, 0);
046d6b28 454 }
046d6b28 455
883992bd 456 return 0;
046d6b28
TL		 457}
458
6b8858a9
PW		 459/**
460 * omap2_table_mpu_recalc - just return the MPU speed
461 * @clk: virt_prcm_set struct clk
462 *
463 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
464 */
8b9dbc16 465static unsigned long omap2_table_mpu_recalc(struct clk *clk)
046d6b28 466{
8b9dbc16 467 return curr_prcm_set->mpu_speed;
046d6b28
TL		 468}
469
470/*
471 * Look for a rate equal or less than the target rate given a configuration set.
472 *
473 * What's not entirely clear is "which" field represents the key field.
474 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
475 * just uses the ARM rates.
476 */
6b8858a9 477static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
046d6b28 478{
6b8858a9 479 struct prcm_config *ptr;
046d6b28
TL		 480 long highest_rate;
481
482 if (clk != &virt_prcm_set)
483 return -EINVAL;
484
485 highest_rate = -EINVAL;
486
487 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
6b8858a9
PW		 488 if (!(ptr->flags & cpu_mask))
489 continue;
046d6b28
TL		 490 if (ptr->xtal_speed != sys_ck.rate)
491 continue;
492
493 highest_rate = ptr->mpu_speed;
494
495 /* Can check only after xtal frequency check */
496 if (ptr->mpu_speed <= rate)
497 break;
498 }
499 return highest_rate;
500}
501
046d6b28 502/* Sets basic clocks based on the specified rate */
6b8858a9 503static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
046d6b28 504{
6b8858a9 505 u32 cur_rate, done_rate, bypass = 0, tmp;
046d6b28
TL		 506 struct prcm_config *prcm;
507 unsigned long found_speed = 0;
6b8858a9 508 unsigned long flags;
046d6b28
TL		 509
510 if (clk != &virt_prcm_set)
511 return -EINVAL;
512
046d6b28
TL		 513 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
514 if (!(prcm->flags & cpu_mask))
515 continue;
516
517 if (prcm->xtal_speed != sys_ck.rate)
518 continue;
519
520 if (prcm->mpu_speed <= rate) {
521 found_speed = prcm->mpu_speed;
522 break;
523 }
524 }
525
526 if (!found_speed) {
527 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
a16e9703 528 rate / 1000000);
046d6b28
TL		 529 return -EINVAL;
530 }
531
532 curr_prcm_set = prcm;
c0bf3132 533 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
046d6b28
TL		 534
535 if (prcm->dpll_speed == cur_rate / 2) {
f2ab9977 536 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
046d6b28 537 } else if (prcm->dpll_speed == cur_rate * 2) {
f2ab9977 538 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 539 } else if (prcm->dpll_speed != cur_rate) {
540 local_irq_save(flags);
541
542 if (prcm->dpll_speed == prcm->xtal_speed)
543 bypass = 1;
544
6b8858a9
PW		 545 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
546 CORE_CLK_SRC_DPLL_X2)
547 done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28 548 else
6b8858a9 549 done_rate = CORE_CLK_SRC_DPLL;
046d6b28
TL		 550
551 /* MPU divider */
6b8858a9 552 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
046d6b28
TL		 553
554 /* dsp + iva1 div(2420), iva2.1(2430) */
6b8858a9
PW		 555 cm_write_mod_reg(prcm->cm_clksel_dsp,
556 OMAP24XX_DSP_MOD, CM_CLKSEL);
046d6b28 557
6b8858a9 558 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
046d6b28
TL		 559
560 /* Major subsystem dividers */
6b8858a9 561 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
fecb494b
PW		 562 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
563 CM_CLKSEL1);
564
046d6b28 565 if (cpu_is_omap2430())
6b8858a9
PW		 566 cm_write_mod_reg(prcm->cm_clksel_mdm,
567 OMAP2430_MDM_MOD, CM_CLKSEL);
046d6b28 568
f2ab9977
PW		 569 /* x2 to enter omap2xxx_sdrc_init_params() */
570 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 571
572 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
573 bypass);
574
f2ab9977
PW		 575 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
576 omap2xxx_sdrc_reprogram(done_rate, 0);
046d6b28
TL		 577
578 local_irq_restore(flags);
579 }
046d6b28
TL		 580
581 return 0;
582}
583
aeec2990
KH		 584#ifdef CONFIG_CPU_FREQ
585/*
586 * Walk PRCM rate table and fillout cpufreq freq_table
587 */
588static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
589
590void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
591{
592 struct prcm_config *prcm;
593 int i = 0;
594
595 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
596 if (!(prcm->flags & cpu_mask))
597 continue;
598 if (prcm->xtal_speed != sys_ck.rate)
599 continue;
600
601 /* don't put bypass rates in table */
602 if (prcm->dpll_speed == prcm->xtal_speed)
603 continue;
604
605 freq_table[i].index = i;
606 freq_table[i].frequency = prcm->mpu_speed / 1000;
607 i++;
608 }
609
610 if (i == 0) {
611 printk(KERN_WARNING "%s: failed to initialize frequency "
612 "table\n", __func__);
613 return;
614 }
615
616 freq_table[i].index = i;
617 freq_table[i].frequency = CPUFREQ_TABLE_END;
618
619 *table = &freq_table[0];
620}
621#endif
622
046d6b28
TL		 623static struct clk_functions omap2_clk_functions = {
624 .clk_enable = omap2_clk_enable,
625 .clk_disable = omap2_clk_disable,
046d6b28
TL		 626 .clk_round_rate = omap2_clk_round_rate,
627 .clk_set_rate = omap2_clk_set_rate,
628 .clk_set_parent = omap2_clk_set_parent,
90afd5cb 629 .clk_disable_unused = omap2_clk_disable_unused,
aeec2990
KH		 630#ifdef CONFIG_CPU_FREQ
631 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
632#endif
046d6b28
TL		 633};
634
6b8858a9 635static u32 omap2_get_apll_clkin(void)
046d6b28 636{
fecb494b 637 u32 aplls, srate = 0;
046d6b28 638
6b8858a9
PW		 639 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
640 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
641 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
046d6b28 642
6b8858a9 643 if (aplls == APLLS_CLKIN_19_2MHZ)
fecb494b 644 srate = 19200000;
6b8858a9 645 else if (aplls == APLLS_CLKIN_13MHZ)
fecb494b 646 srate = 13000000;
6b8858a9 647 else if (aplls == APLLS_CLKIN_12MHZ)
fecb494b 648 srate = 12000000;
046d6b28 649
fecb494b 650 return srate;
6b8858a9
PW		 651}
652
653static u32 omap2_get_sysclkdiv(void)
654{
655 u32 div;
656
8e3bd351 657 div = __raw_readl(prcm_clksrc_ctrl);
6b8858a9
PW		 658 div &= OMAP_SYSCLKDIV_MASK;
659 div >>= OMAP_SYSCLKDIV_SHIFT;
046d6b28 660
6b8858a9
PW		 661 return div;
662}
663
8b9dbc16 664static unsigned long omap2_osc_clk_recalc(struct clk *clk)
6b8858a9 665{
8b9dbc16 666 return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
6b8858a9
PW		 667}
668
8b9dbc16 669static unsigned long omap2_sys_clk_recalc(struct clk *clk)
6b8858a9 670{
8b9dbc16 671 return clk->parent->rate / omap2_get_sysclkdiv();
046d6b28
TL		 672}
673
ae78dcf7
TL		 674/*
675 * Set clocks for bypass mode for reboot to work.
676 */
677void omap2_clk_prepare_for_reboot(void)
678{
679 u32 rate;
680
681 if (vclk == NULL || sclk == NULL)
682 return;
683
684 rate = clk_get_rate(sclk);
685 clk_set_rate(vclk, rate);
686}
687
046d6b28
TL		 688/*
689 * Switch the MPU rate if specified on cmdline.
690 * We cannot do this early until cmdline is parsed.
691 */
692static int __init omap2_clk_arch_init(void)
693{
694 if (!mpurate)
695 return -EINVAL;
696
7b0f89d7 697 if (clk_set_rate(&virt_prcm_set, mpurate))
046d6b28
TL		 698 printk(KERN_ERR "Could not find matching MPU rate\n");
699
6b8858a9 700 recalculate_root_clocks();
046d6b28
TL		 701
702 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
703 "%ld.%01ld/%ld/%ld MHz\n",
704 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
705 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
706
707 return 0;
708}
709arch_initcall(omap2_clk_arch_init);
710
711int __init omap2_clk_init(void)
712{
713 struct prcm_config *prcm;
8ad8ff65 714 struct omap_clk *c;
15ca78f7 715 u32 clkrate;
046d6b28 716
8e3bd351
TL		 717 if (cpu_is_omap242x()) {
718 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
6b8858a9 719 cpu_mask = RATE_IN_242X;
8e3bd351
TL		 720 } else if (cpu_is_omap2430()) {
721 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
6b8858a9 722 cpu_mask = RATE_IN_243X;
8e3bd351 723 }
6b8858a9 724
046d6b28 725 clk_init(&omap2_clk_functions);
046d6b28 726
c8088112 727 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
79716870 728 clk_preinit(c->lk.clk);
c8088112 729
8b9dbc16 730 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
9a5fedac 731 propagate_rate(&osc_ck);
8b9dbc16 732 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
9a5fedac 733 propagate_rate(&sys_ck);
6b8858a9 734
8ad8ff65
RK		 735 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
736 if (c->cpu & cpu_mask) {
737 clkdev_add(&c->lk);
738 clk_register(c->lk.clk);
046d6b28
TL		 739 }
740
046d6b28 741 /* Check the MPU rate set by bootloader */
c0bf3132 742 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
046d6b28 743 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
6b8858a9
PW		 744 if (!(prcm->flags & cpu_mask))
745 continue;
046d6b28
TL		 746 if (prcm->xtal_speed != sys_ck.rate)
747 continue;
748 if (prcm->dpll_speed <= clkrate)
749 break;
750 }
751 curr_prcm_set = prcm;
752
6b8858a9 753 recalculate_root_clocks();
046d6b28
TL		 754
755 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
756 "%ld.%01ld/%ld/%ld MHz\n",
757 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
758 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
759
760 /*
761 * Only enable those clocks we will need, let the drivers
762 * enable other clocks as necessary
763 */
6b8858a9 764 clk_enable_init_clocks();
046d6b28 765
ae78dcf7
TL		 766 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
767 vclk = clk_get(NULL, "virt_prcm_set");
768 sclk = clk_get(NULL, "sys_ck");
769
046d6b28
TL		 770 return 0;
771}
Linux kernel - Deliverables
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