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OMAP3 clock: convert clock34xx.h to clock34xx_data.c
[deliverable/linux.git] / arch / arm / mach-omap2 / clock24xx.c
CommitLineData
046d6b28
TL		 1/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
a16e9703
TL		 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
046d6b28 6 *
a16e9703
TL		 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
046d6b28 10 *
a16e9703
TL		 11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
046d6b28
TL		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
6b8858a9
PW		 18#undef DEBUG
19
046d6b28
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/device.h>
23#include <linux/list.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
f8ce2547 26#include <linux/clk.h>
6b8858a9
PW		 27#include <linux/io.h>
28#include <linux/cpufreq.h>
fbd3bdb2 29#include <linux/bitops.h>
046d6b28 30
ce491cf8
TL		 31#include <plat/clock.h>
32#include <plat/sram.h>
33#include <plat/prcm.h>
82e9bd58 34#include <plat/clkdev_omap.h>
76631486 35#include <asm/div64.h>
8ad8ff65 36#include <asm/clkdev.h>
046d6b28 37
ce491cf8 38#include <plat/sdrc.h>
6b8858a9 39#include "clock.h"
6b8858a9
PW		 40#include "prm.h"
41#include "prm-regbits-24xx.h"
42#include "cm.h"
43#include "cm-regbits-24xx.h"
046d6b28 44
548d8495 45static const struct clkops clkops_oscck;
06b16939
PW		 46static const struct clkops clkops_apll96;
47static const struct clkops clkops_apll54;
548d8495 48
3dc21975
PW		 49static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
50 void __iomem **idlest_reg,
51 u8 *idlest_bit);
52
53/* 2430 I2CHS has non-standard IDLEST register */
54static const struct clkops clkops_omap2430_i2chs_wait = {
55 .enable = omap2_dflt_clk_enable,
56 .disable = omap2_dflt_clk_disable,
57 .find_idlest = omap2430_clk_i2chs_find_idlest,
58 .find_companion = omap2_clk_dflt_find_companion,
59};
60
548d8495
RK		 61#include "clock24xx.h"
62
8ad8ff65
RK		 63static struct omap_clk omap24xx_clks[] = {
64 /* external root sources */
65 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
f248076c 66 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
8ad8ff65
RK		 67 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
68 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
69 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
70 /* internal analog sources */
71 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
72 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
73 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
74 /* internal prcm root sources */
75 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
76 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
77 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
78 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
79 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
80 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
81 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
82 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
83 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
84 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
85 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
86 /* mpu domain clocks */
87 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
88 /* dsp domain clocks */
89 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
90 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
91 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
92 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
93 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
94 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
95 /* GFX domain clocks */
96 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
97 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
98 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
99 /* Modem domain clocks */
100 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
101 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
102 /* DSS domain clocks */
dadd2bb9
TV		 103 CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
104 CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
105 CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
106 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
8ad8ff65
RK		 107 /* L3 domain clocks */
108 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
109 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
110 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
111 /* L4 domain clocks */
112 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
9299fd85 113 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
8ad8ff65
RK		 114 /* virtual meta-group clock */
115 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
116 /* general l4 interface ck, multi-parent functional clk */
117 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
118 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
119 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
120 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
121 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
122 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
123 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
124 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
125 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
126 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
127 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
128 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
129 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
130 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
131 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
132 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
133 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
134 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
135 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
136 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
137 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
138 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
139 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
140 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
b820ce4e
RK		 141 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
142 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
143 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
144 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
145 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
146 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
147 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
148 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
149 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
150 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
1b5715ec
RK		 151 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
152 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
153 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
154 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
155 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
156 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
8ad8ff65
RK		 157 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
158 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
159 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
160 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
161 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
162 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
163 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
164 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
39a80c7f
RK		 165 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
166 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
8ad8ff65
RK		 167 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
168 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
169 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
170 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
6c5dbb40
RK		 171 CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
172 CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
8ad8ff65
RK		 173 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
174 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
175 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
176 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
177 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
178 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
179 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
5c9e02b1
RK		 180 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
181 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
8ad8ff65
RK		 182 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
183 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
184 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
185 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
cc51c9d4
RK		 186 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
187 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
1d14de08
RK		 188 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
189 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
190 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
191 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
192 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
193 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
8ad8ff65
RK		 194 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
195 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
196 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
197 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
198 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
199 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
200 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
201 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
eeec7c8d 202 CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
8ad8ff65
RK		 203 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
204 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
205 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
4ea60b0c 206 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
6f7607cc
RK		 207 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
208 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
209 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
210 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
8ad8ff65
RK		 211 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
212 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
213 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
214 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
215 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
216};
217
6b8858a9
PW		 218/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
219#define EN_APLL_STOPPED 0
220#define EN_APLL_LOCKED 3
ddc32a87 221
6b8858a9
PW		 222/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
223#define APLLS_CLKIN_19_2MHZ 0
224#define APLLS_CLKIN_13MHZ 2
225#define APLLS_CLKIN_12MHZ 3
226
227/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
046d6b28
TL		 228
229static struct prcm_config *curr_prcm_set;
ae78dcf7
TL		 230static struct clk *vclk;
231static struct clk *sclk;
046d6b28 232
8e3bd351
TL		 233static void __iomem *prcm_clksrc_ctrl;
234
046d6b28 235/*-------------------------------------------------------------------------
6b8858a9 236 * Omap24xx specific clock functions
046d6b28
TL		 237 *-------------------------------------------------------------------------*/
238
3dc21975
PW		 239/**
240 * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
241 * @clk: struct clk * being enabled
242 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
243 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
244 *
245 * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
246 * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
247 * passes back the correct CM_IDLEST register address for I2CHS
248 * modules. No return value.
249 */
250static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
251 void __iomem **idlest_reg,
252 u8 *idlest_bit)
253{
254 *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
255 *idlest_bit = clk->enable_bit;
256}
257
258
c0bf3132
RK		 259/**
260 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
261 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
262 *
263 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
264 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
265 * (the latter is unusual). This currently should be called with
266 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
267 * core_ck.
268 */
269static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
a16e9703 270{
c0bf3132
RK		 271 long long core_clk;
272 u32 v;
a16e9703 273
c0bf3132 274 core_clk = omap2_get_dpll_rate(clk);
a16e9703 275
c0bf3132
RK		 276 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
277 v &= OMAP24XX_CORE_CLK_SRC_MASK;
278
279 if (v == CORE_CLK_SRC_32K)
280 core_clk = 32768;
281 else
282 core_clk *= v;
a16e9703 283
c0bf3132 284 return core_clk;
a16e9703
TL		 285}
286
6b8858a9
PW		 287static int omap2_enable_osc_ck(struct clk *clk)
288{
289 u32 pcc;
290
8e3bd351 291 pcc = __raw_readl(prcm_clksrc_ctrl);
6b8858a9 292
8e3bd351 293 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
6b8858a9
PW		 294
295 return 0;
296}
297
298static void omap2_disable_osc_ck(struct clk *clk)
299{
300 u32 pcc;
301
8e3bd351 302 pcc = __raw_readl(prcm_clksrc_ctrl);
6b8858a9 303
8e3bd351 304 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
6b8858a9
PW		 305}
306
548d8495
RK		 307static const struct clkops clkops_oscck = {
308 .enable = &omap2_enable_osc_ck,
309 .disable = &omap2_disable_osc_ck,
310};
311
6b8858a9 312#ifdef OLD_CK
046d6b28
TL		 313/* Recalculate SYST_CLK */
314static void omap2_sys_clk_recalc(struct clk * clk)
315{
316 u32 div = PRCM_CLKSRC_CTRL;
317 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
318 div >>= clk->rate_offset;
319 clk->rate = (clk->parent->rate / div);
320 propagate_rate(clk);
321}
6b8858a9 322#endif /* OLD_CK */
046d6b28 323
046d6b28 324/* Enable an APLL if off */
06b16939 325static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
046d6b28 326{
6b8858a9 327 u32 cval, apll_mask;
046d6b28 328
6b8858a9 329 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
046d6b28 330
6b8858a9 331 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
046d6b28 332
6b8858a9
PW		 333 if ((cval & apll_mask) == apll_mask)
334 return 0; /* apll already enabled */
046d6b28 335
6b8858a9
PW		 336 cval &= ~apll_mask;
337 cval |= apll_mask;
338 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28 339
06b16939 340 omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
3dc21975 341 clk->name);
6b8858a9
PW		 342
343 /*
344 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
345 * fails?
346 */
347 return 0;
046d6b28
TL		 348}
349
06b16939
PW		 350static int omap2_clk_apll96_enable(struct clk *clk)
351{
352 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
353}
354
355static int omap2_clk_apll54_enable(struct clk *clk)
356{
357 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
358}
359
046d6b28 360/* Stop APLL */
06b16939 361static void omap2_clk_apll_disable(struct clk *clk)
046d6b28
TL		 362{
363 u32 cval;
364
6b8858a9
PW		 365 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
366 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
367 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
046d6b28
TL		 368}
369
06b16939
PW		 370static const struct clkops clkops_apll96 = {
371 .enable = &omap2_clk_apll96_enable,
372 .disable = &omap2_clk_apll_disable,
373};
374
375static const struct clkops clkops_apll54 = {
376 .enable = &omap2_clk_apll54_enable,
377 .disable = &omap2_clk_apll_disable,
548d8495
RK		 378};
379
046d6b28
TL		 380/*
381 * Uses the current prcm set to tell if a rate is valid.
382 * You can go slower, but not faster within a given rate set.
383 */
fecb494b 384static long omap2_dpllcore_round_rate(unsigned long target_rate)
046d6b28 385{
6b8858a9 386 u32 high, low, core_clk_src;
046d6b28 387
6b8858a9
PW		 388 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
389 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
390
391 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
046d6b28
TL		 392 high = curr_prcm_set->dpll_speed * 2;
393 low = curr_prcm_set->dpll_speed;
394 } else { /* DPLL clockout x 2 */
395 high = curr_prcm_set->dpll_speed;
396 low = curr_prcm_set->dpll_speed / 2;
397 }
398
399#ifdef DOWN_VARIABLE_DPLL
400 if (target_rate > high)
401 return high;
402 else
403 return target_rate;
404#else
405 if (target_rate > low)
406 return high;
407 else
408 return low;
409#endif
410
411}
412
8b9dbc16 413static unsigned long omap2_dpllcore_recalc(struct clk *clk)
6b8858a9 414{
c0bf3132 415 return omap2xxx_clk_get_core_rate(clk);
6b8858a9 416}
046d6b28 417
88b8ba90 418static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
046d6b28 419{
6b8858a9 420 u32 cur_rate, low, mult, div, valid_rate, done_rate;
046d6b28
TL		 421 u32 bypass = 0;
422 struct prcm_config tmpset;
6b8858a9 423 const struct dpll_data *dd;
046d6b28 424
c0bf3132 425 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
6b8858a9
PW		 426 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
427 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28
TL		 428
429 if ((rate == (cur_rate / 2)) && (mult == 2)) {
f2ab9977 430 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
046d6b28 431 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
f2ab9977 432 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28 433 } else if (rate != cur_rate) {
88b8ba90 434 valid_rate = omap2_dpllcore_round_rate(rate);
046d6b28 435 if (valid_rate != rate)
883992bd 436 return -EINVAL;
046d6b28 437
6b8858a9 438 if (mult == 1)
046d6b28
TL		 439 low = curr_prcm_set->dpll_speed;
440 else
441 low = curr_prcm_set->dpll_speed / 2;
442
6b8858a9
PW		 443 dd = clk->dpll_data;
444 if (!dd)
883992bd 445 return -EINVAL;
6b8858a9
PW		 446
447 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
448 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
449 dd->div1_mask);
046d6b28 450 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
6b8858a9
PW		 451 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
452 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
046d6b28 453 if (rate > low) {
6b8858a9 454 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
046d6b28 455 mult = ((rate / 2) / 1000000);
6b8858a9 456 done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28 457 } else {
6b8858a9 458 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
046d6b28 459 mult = (rate / 1000000);
6b8858a9 460 done_rate = CORE_CLK_SRC_DPLL;
046d6b28 461 }
6b8858a9
PW		 462 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
463 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
046d6b28
TL		 464
465 /* Worst case */
6b8858a9 466 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
046d6b28
TL		 467
468 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
469 bypass = 1;
470
f2ab9977
PW		 471 /* For omap2xxx_sdrc_init_params() */
472 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 473
474 /* Force dll lock mode */
475 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
476 bypass);
477
478 /* Errata: ret dll entry state */
f2ab9977
PW		 479 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
480 omap2xxx_sdrc_reprogram(done_rate, 0);
046d6b28 481 }
046d6b28 482
883992bd 483 return 0;
046d6b28
TL		 484}
485
6b8858a9
PW		 486/**
487 * omap2_table_mpu_recalc - just return the MPU speed
488 * @clk: virt_prcm_set struct clk
489 *
490 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
491 */
8b9dbc16 492static unsigned long omap2_table_mpu_recalc(struct clk *clk)
046d6b28 493{
8b9dbc16 494 return curr_prcm_set->mpu_speed;
046d6b28
TL		 495}
496
497/*
498 * Look for a rate equal or less than the target rate given a configuration set.
499 *
500 * What's not entirely clear is "which" field represents the key field.
501 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
502 * just uses the ARM rates.
503 */
6b8858a9 504static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
046d6b28 505{
6b8858a9 506 struct prcm_config *ptr;
046d6b28
TL		 507 long highest_rate;
508
046d6b28
TL		 509 highest_rate = -EINVAL;
510
511 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
6b8858a9
PW		 512 if (!(ptr->flags & cpu_mask))
513 continue;
046d6b28
TL		 514 if (ptr->xtal_speed != sys_ck.rate)
515 continue;
516
517 highest_rate = ptr->mpu_speed;
518
519 /* Can check only after xtal frequency check */
520 if (ptr->mpu_speed <= rate)
521 break;
522 }
523 return highest_rate;
524}
525
046d6b28 526/* Sets basic clocks based on the specified rate */
6b8858a9 527static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
046d6b28 528{
6b8858a9 529 u32 cur_rate, done_rate, bypass = 0, tmp;
046d6b28
TL		 530 struct prcm_config *prcm;
531 unsigned long found_speed = 0;
6b8858a9 532 unsigned long flags;
046d6b28 533
046d6b28
TL		 534 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
535 if (!(prcm->flags & cpu_mask))
536 continue;
537
538 if (prcm->xtal_speed != sys_ck.rate)
539 continue;
540
541 if (prcm->mpu_speed <= rate) {
542 found_speed = prcm->mpu_speed;
543 break;
544 }
545 }
546
547 if (!found_speed) {
548 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
a16e9703 549 rate / 1000000);
046d6b28
TL		 550 return -EINVAL;
551 }
552
553 curr_prcm_set = prcm;
c0bf3132 554 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
046d6b28
TL		 555
556 if (prcm->dpll_speed == cur_rate / 2) {
f2ab9977 557 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
046d6b28 558 } else if (prcm->dpll_speed == cur_rate * 2) {
f2ab9977 559 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 560 } else if (prcm->dpll_speed != cur_rate) {
561 local_irq_save(flags);
562
563 if (prcm->dpll_speed == prcm->xtal_speed)
564 bypass = 1;
565
6b8858a9
PW		 566 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
567 CORE_CLK_SRC_DPLL_X2)
568 done_rate = CORE_CLK_SRC_DPLL_X2;
046d6b28 569 else
6b8858a9 570 done_rate = CORE_CLK_SRC_DPLL;
046d6b28
TL		 571
572 /* MPU divider */
6b8858a9 573 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
046d6b28
TL		 574
575 /* dsp + iva1 div(2420), iva2.1(2430) */
6b8858a9
PW		 576 cm_write_mod_reg(prcm->cm_clksel_dsp,
577 OMAP24XX_DSP_MOD, CM_CLKSEL);
046d6b28 578
6b8858a9 579 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
046d6b28
TL		 580
581 /* Major subsystem dividers */
6b8858a9 582 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
fecb494b
PW		 583 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
584 CM_CLKSEL1);
585
046d6b28 586 if (cpu_is_omap2430())
6b8858a9
PW		 587 cm_write_mod_reg(prcm->cm_clksel_mdm,
588 OMAP2430_MDM_MOD, CM_CLKSEL);
046d6b28 589
f2ab9977
PW		 590 /* x2 to enter omap2xxx_sdrc_init_params() */
591 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
046d6b28
TL		 592
593 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
594 bypass);
595
f2ab9977
PW		 596 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
597 omap2xxx_sdrc_reprogram(done_rate, 0);
046d6b28
TL		 598
599 local_irq_restore(flags);
600 }
046d6b28
TL		 601
602 return 0;
603}
604
aeec2990
KH		 605#ifdef CONFIG_CPU_FREQ
606/*
607 * Walk PRCM rate table and fillout cpufreq freq_table
608 */
609static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
610
611void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
612{
613 struct prcm_config *prcm;
614 int i = 0;
615
616 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
617 if (!(prcm->flags & cpu_mask))
618 continue;
619 if (prcm->xtal_speed != sys_ck.rate)
620 continue;
621
622 /* don't put bypass rates in table */
623 if (prcm->dpll_speed == prcm->xtal_speed)
624 continue;
625
626 freq_table[i].index = i;
627 freq_table[i].frequency = prcm->mpu_speed / 1000;
628 i++;
629 }
630
631 if (i == 0) {
632 printk(KERN_WARNING "%s: failed to initialize frequency "
633 "table\n", __func__);
634 return;
635 }
636
637 freq_table[i].index = i;
638 freq_table[i].frequency = CPUFREQ_TABLE_END;
639
640 *table = &freq_table[0];
641}
642#endif
643
82e9bd58 644struct clk_functions omap2_clk_functions = {
046d6b28
TL		 645 .clk_enable = omap2_clk_enable,
646 .clk_disable = omap2_clk_disable,
046d6b28
TL		 647 .clk_round_rate = omap2_clk_round_rate,
648 .clk_set_rate = omap2_clk_set_rate,
649 .clk_set_parent = omap2_clk_set_parent,
90afd5cb 650 .clk_disable_unused = omap2_clk_disable_unused,
aeec2990
KH		 651#ifdef CONFIG_CPU_FREQ
652 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
653#endif
046d6b28
TL		 654};
655
6b8858a9 656static u32 omap2_get_apll_clkin(void)
046d6b28 657{
fecb494b 658 u32 aplls, srate = 0;
046d6b28 659
6b8858a9
PW		 660 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
661 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
662 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
046d6b28 663
6b8858a9 664 if (aplls == APLLS_CLKIN_19_2MHZ)
fecb494b 665 srate = 19200000;
6b8858a9 666 else if (aplls == APLLS_CLKIN_13MHZ)
fecb494b 667 srate = 13000000;
6b8858a9 668 else if (aplls == APLLS_CLKIN_12MHZ)
fecb494b 669 srate = 12000000;
046d6b28 670
fecb494b 671 return srate;
6b8858a9
PW		 672}
673
674static u32 omap2_get_sysclkdiv(void)
675{
676 u32 div;
677
8e3bd351 678 div = __raw_readl(prcm_clksrc_ctrl);
6b8858a9
PW		 679 div &= OMAP_SYSCLKDIV_MASK;
680 div >>= OMAP_SYSCLKDIV_SHIFT;
046d6b28 681
6b8858a9
PW		 682 return div;
683}
684
8b9dbc16 685static unsigned long omap2_osc_clk_recalc(struct clk *clk)
6b8858a9 686{
8b9dbc16 687 return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
6b8858a9
PW		 688}
689
8b9dbc16 690static unsigned long omap2_sys_clk_recalc(struct clk *clk)
6b8858a9 691{
8b9dbc16 692 return clk->parent->rate / omap2_get_sysclkdiv();
046d6b28
TL		 693}
694
ae78dcf7
TL		 695/*
696 * Set clocks for bypass mode for reboot to work.
697 */
698void omap2_clk_prepare_for_reboot(void)
699{
700 u32 rate;
701
702 if (vclk == NULL || sclk == NULL)
703 return;
704
705 rate = clk_get_rate(sclk);
706 clk_set_rate(vclk, rate);
707}
708
046d6b28
TL		 709/*
710 * Switch the MPU rate if specified on cmdline.
711 * We cannot do this early until cmdline is parsed.
712 */
713static int __init omap2_clk_arch_init(void)
714{
715 if (!mpurate)
716 return -EINVAL;
717
7b0f89d7 718 if (clk_set_rate(&virt_prcm_set, mpurate))
046d6b28
TL		 719 printk(KERN_ERR "Could not find matching MPU rate\n");
720
6b8858a9 721 recalculate_root_clocks();
046d6b28
TL		 722
723 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
724 "%ld.%01ld/%ld/%ld MHz\n",
725 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
726 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
727
728 return 0;
729}
730arch_initcall(omap2_clk_arch_init);
731
732int __init omap2_clk_init(void)
733{
734 struct prcm_config *prcm;
8ad8ff65 735 struct omap_clk *c;
15ca78f7 736 u32 clkrate;
75d43340 737 u16 cpu_clkflg;
046d6b28 738
8e3bd351
TL		 739 if (cpu_is_omap242x()) {
740 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
6b8858a9 741 cpu_mask = RATE_IN_242X;
75d43340 742 cpu_clkflg = CK_242X;
8e3bd351
TL		 743 } else if (cpu_is_omap2430()) {
744 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
6b8858a9 745 cpu_mask = RATE_IN_243X;
75d43340 746 cpu_clkflg = CK_243X;
8e3bd351 747 }
6b8858a9 748
046d6b28 749 clk_init(&omap2_clk_functions);
046d6b28 750
c8088112 751 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
79716870 752 clk_preinit(c->lk.clk);
c8088112 753
8b9dbc16 754 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
9a5fedac 755 propagate_rate(&osc_ck);
8b9dbc16 756 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
9a5fedac 757 propagate_rate(&sys_ck);
6b8858a9 758
8ad8ff65 759 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
75d43340 760 if (c->cpu & cpu_clkflg) {
8ad8ff65
RK		 761 clkdev_add(&c->lk);
762 clk_register(c->lk.clk);
a7f20b26 763 omap2_init_clk_clkdm(c->lk.clk);
046d6b28
TL		 764 }
765
046d6b28 766 /* Check the MPU rate set by bootloader */
c0bf3132 767 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
046d6b28 768 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
6b8858a9
PW		 769 if (!(prcm->flags & cpu_mask))
770 continue;
046d6b28
TL		 771 if (prcm->xtal_speed != sys_ck.rate)
772 continue;
773 if (prcm->dpll_speed <= clkrate)
774 break;
775 }
776 curr_prcm_set = prcm;
777
6b8858a9 778 recalculate_root_clocks();
046d6b28
TL		 779
780 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
781 "%ld.%01ld/%ld/%ld MHz\n",
782 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
783 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
784
785 /*
786 * Only enable those clocks we will need, let the drivers
787 * enable other clocks as necessary
788 */
6b8858a9 789 clk_enable_init_clocks();
046d6b28 790
ae78dcf7
TL		 791 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
792 vclk = clk_get(NULL, "virt_prcm_set");
793 sclk = clk_get(NULL, "sys_ck");
794
046d6b28
TL		 795 return 0;
796}
Linux kernel - Deliverables
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