Commit | Line | Data |
---|---|---|
046d6b28 | 1 | /* |
d8a94458 | 2 | * linux/arch/arm/mach-omap2/clock2xxx_data.c |
046d6b28 | 3 | * |
d8a94458 PW |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2009 Nokia Corporation | |
046d6b28 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 TL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
d8a94458 PW |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | |
18 | #include <linux/clk.h> | |
046d6b28 | 19 | |
d8a94458 | 20 | #include <plat/clkdev_omap.h> |
6b8858a9 | 21 | |
d8a94458 PW |
22 | #include "clock.h" |
23 | #include "clock2xxx.h" | |
24 | #include "opp2xxx.h" | |
6b8858a9 PW |
25 | #include "prm.h" |
26 | #include "cm.h" | |
27 | #include "prm-regbits-24xx.h" | |
28 | #include "cm-regbits-24xx.h" | |
29 | #include "sdrc.h" | |
30 | ||
046d6b28 TL |
31 | /*------------------------------------------------------------------------- |
32 | * 24xx clock tree. | |
33 | * | |
34 | * NOTE:In many cases here we are assigning a 'default' parent. In many | |
35 | * cases the parent is selectable. The get/set parent calls will also | |
36 | * switch sources. | |
37 | * | |
38 | * Many some clocks say always_enabled, but they can be auto idled for | |
39 | * power savings. They will always be available upon clock request. | |
40 | * | |
41 | * Several sources are given initial rates which may be wrong, this will | |
42 | * be fixed up in the init func. | |
43 | * | |
44 | * Things are broadly separated below by clock domains. It is | |
45 | * noteworthy that most periferals have dependencies on multiple clock | |
46 | * domains. Many get their interface clocks from the L4 domain, but get | |
47 | * functional clocks from fixed sources or other core domain derived | |
48 | * clocks. | |
49 | *-------------------------------------------------------------------------*/ | |
50 | ||
51 | /* Base external input clocks */ | |
52 | static struct clk func_32k_ck = { | |
53 | .name = "func_32k_ck", | |
897dcded | 54 | .ops = &clkops_null, |
046d6b28 | 55 | .rate = 32000, |
3f0a820c | 56 | .flags = RATE_FIXED, |
d1b03f61 | 57 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 58 | }; |
e32744b0 | 59 | |
f248076c PW |
60 | static struct clk secure_32k_ck = { |
61 | .name = "secure_32k_ck", | |
62 | .ops = &clkops_null, | |
63 | .rate = 32768, | |
64 | .flags = RATE_FIXED, | |
65 | .clkdm_name = "wkup_clkdm", | |
66 | }; | |
67 | ||
046d6b28 TL |
68 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
69 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |
70 | .name = "osc_ck", | |
548d8495 | 71 | .ops = &clkops_oscck, |
d1b03f61 | 72 | .clkdm_name = "wkup_clkdm", |
e32744b0 | 73 | .recalc = &omap2_osc_clk_recalc, |
046d6b28 TL |
74 | }; |
75 | ||
d1b03f61 | 76 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
046d6b28 TL |
77 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
78 | .name = "sys_ck", /* ~ ref_clk also */ | |
897dcded | 79 | .ops = &clkops_null, |
046d6b28 | 80 | .parent = &osc_ck, |
d1b03f61 | 81 | .clkdm_name = "wkup_clkdm", |
44da0a51 | 82 | .recalc = &omap2xxx_sys_clk_recalc, |
046d6b28 | 83 | }; |
e32744b0 | 84 | |
046d6b28 TL |
85 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
86 | .name = "alt_ck", | |
897dcded | 87 | .ops = &clkops_null, |
046d6b28 | 88 | .rate = 54000000, |
3f0a820c | 89 | .flags = RATE_FIXED, |
d1b03f61 | 90 | .clkdm_name = "wkup_clkdm", |
046d6b28 | 91 | }; |
e32744b0 | 92 | |
046d6b28 TL |
93 | /* |
94 | * Analog domain root source clocks | |
95 | */ | |
96 | ||
97 | /* dpll_ck, is broken out in to special cases through clksel */ | |
6b8858a9 PW |
98 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
99 | * deal with this | |
100 | */ | |
101 | ||
88b8ba90 | 102 | static struct dpll_data dpll_dd = { |
6b8858a9 PW |
103 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
104 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | |
105 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | |
c0bf3132 RK |
106 | .clk_bypass = &sys_ck, |
107 | .clk_ref = &sys_ck, | |
108 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
109 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | |
88b8ba90 | 110 | .max_multiplier = 1024, |
95f538ac | 111 | .min_divider = 1, |
88b8ba90 PW |
112 | .max_divider = 16, |
113 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
6b8858a9 PW |
114 | }; |
115 | ||
88b8ba90 PW |
116 | /* |
117 | * XXX Cannot add round_rate here yet, as this is still a composite clock, | |
118 | * not just a DPLL | |
119 | */ | |
046d6b28 TL |
120 | static struct clk dpll_ck = { |
121 | .name = "dpll_ck", | |
897dcded | 122 | .ops = &clkops_null, |
046d6b28 | 123 | .parent = &sys_ck, /* Can be func_32k also */ |
6b8858a9 | 124 | .dpll_data = &dpll_dd, |
d1b03f61 | 125 | .clkdm_name = "wkup_clkdm", |
88b8ba90 PW |
126 | .recalc = &omap2_dpllcore_recalc, |
127 | .set_rate = &omap2_reprogram_dpllcore, | |
046d6b28 TL |
128 | }; |
129 | ||
130 | static struct clk apll96_ck = { | |
131 | .name = "apll96_ck", | |
06b16939 | 132 | .ops = &clkops_apll96, |
046d6b28 TL |
133 | .parent = &sys_ck, |
134 | .rate = 96000000, | |
3f0a820c | 135 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
d1b03f61 | 136 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
137 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
138 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | |
046d6b28 TL |
139 | }; |
140 | ||
141 | static struct clk apll54_ck = { | |
142 | .name = "apll54_ck", | |
06b16939 | 143 | .ops = &clkops_apll54, |
046d6b28 TL |
144 | .parent = &sys_ck, |
145 | .rate = 54000000, | |
3f0a820c | 146 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
d1b03f61 | 147 | .clkdm_name = "wkup_clkdm", |
6b8858a9 PW |
148 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
149 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | |
046d6b28 TL |
150 | }; |
151 | ||
152 | /* | |
153 | * PRCM digital base sources | |
154 | */ | |
e32744b0 PW |
155 | |
156 | /* func_54m_ck */ | |
157 | ||
158 | static const struct clksel_rate func_54m_apll54_rates[] = { | |
159 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
160 | { .div = 0 }, | |
161 | }; | |
162 | ||
163 | static const struct clksel_rate func_54m_alt_rates[] = { | |
164 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
165 | { .div = 0 }, | |
166 | }; | |
167 | ||
168 | static const struct clksel func_54m_clksel[] = { | |
169 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | |
170 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | |
171 | { .parent = NULL }, | |
172 | }; | |
173 | ||
046d6b28 TL |
174 | static struct clk func_54m_ck = { |
175 | .name = "func_54m_ck", | |
57137181 | 176 | .ops = &clkops_null, |
046d6b28 | 177 | .parent = &apll54_ck, /* can also be alt_clk */ |
d1b03f61 | 178 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
179 | .init = &omap2_init_clksel_parent, |
180 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
181 | .clksel_mask = OMAP24XX_54M_SOURCE, | |
182 | .clksel = func_54m_clksel, | |
183 | .recalc = &omap2_clksel_recalc, | |
046d6b28 | 184 | }; |
e32744b0 | 185 | |
046d6b28 TL |
186 | static struct clk core_ck = { |
187 | .name = "core_ck", | |
897dcded | 188 | .ops = &clkops_null, |
046d6b28 | 189 | .parent = &dpll_ck, /* can also be 32k */ |
d1b03f61 | 190 | .clkdm_name = "wkup_clkdm", |
6b8858a9 | 191 | .recalc = &followparent_recalc, |
046d6b28 | 192 | }; |
e32744b0 PW |
193 | |
194 | /* func_96m_ck */ | |
195 | static const struct clksel_rate func_96m_apll96_rates[] = { | |
196 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
197 | { .div = 0 }, | |
046d6b28 TL |
198 | }; |
199 | ||
e32744b0 PW |
200 | static const struct clksel_rate func_96m_alt_rates[] = { |
201 | { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, | |
202 | { .div = 0 }, | |
203 | }; | |
204 | ||
205 | static const struct clksel func_96m_clksel[] = { | |
206 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, | |
207 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, | |
208 | { .parent = NULL } | |
209 | }; | |
210 | ||
211 | /* The parent of this clock is not selectable on 2420. */ | |
046d6b28 TL |
212 | static struct clk func_96m_ck = { |
213 | .name = "func_96m_ck", | |
57137181 | 214 | .ops = &clkops_null, |
046d6b28 | 215 | .parent = &apll96_ck, |
d1b03f61 | 216 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
217 | .init = &omap2_init_clksel_parent, |
218 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
219 | .clksel_mask = OMAP2430_96M_SOURCE, | |
220 | .clksel = func_96m_clksel, | |
221 | .recalc = &omap2_clksel_recalc, | |
222 | .round_rate = &omap2_clksel_round_rate, | |
223 | .set_rate = &omap2_clksel_set_rate | |
224 | }; | |
225 | ||
226 | /* func_48m_ck */ | |
227 | ||
228 | static const struct clksel_rate func_48m_apll96_rates[] = { | |
229 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
230 | { .div = 0 }, | |
231 | }; | |
232 | ||
233 | static const struct clksel_rate func_48m_alt_rates[] = { | |
234 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
235 | { .div = 0 }, | |
236 | }; | |
237 | ||
238 | static const struct clksel func_48m_clksel[] = { | |
239 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | |
240 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | |
241 | { .parent = NULL } | |
046d6b28 TL |
242 | }; |
243 | ||
244 | static struct clk func_48m_ck = { | |
245 | .name = "func_48m_ck", | |
57137181 | 246 | .ops = &clkops_null, |
046d6b28 | 247 | .parent = &apll96_ck, /* 96M or Alt */ |
d1b03f61 | 248 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
249 | .init = &omap2_init_clksel_parent, |
250 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
251 | .clksel_mask = OMAP24XX_48M_SOURCE, | |
252 | .clksel = func_48m_clksel, | |
253 | .recalc = &omap2_clksel_recalc, | |
254 | .round_rate = &omap2_clksel_round_rate, | |
255 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
256 | }; |
257 | ||
258 | static struct clk func_12m_ck = { | |
259 | .name = "func_12m_ck", | |
57137181 | 260 | .ops = &clkops_null, |
046d6b28 | 261 | .parent = &func_48m_ck, |
e32744b0 | 262 | .fixed_div = 4, |
d1b03f61 | 263 | .clkdm_name = "wkup_clkdm", |
e9b98f60 | 264 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
265 | }; |
266 | ||
267 | /* Secure timer, only available in secure mode */ | |
268 | static struct clk wdt1_osc_ck = { | |
269 | .name = "ck_wdt1_osc", | |
897dcded | 270 | .ops = &clkops_null, /* RMK: missing? */ |
046d6b28 | 271 | .parent = &osc_ck, |
e32744b0 PW |
272 | .recalc = &followparent_recalc, |
273 | }; | |
274 | ||
275 | /* | |
276 | * The common_clkout* clksel_rate structs are common to | |
277 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | |
278 | * sys_clkout2_* are 2420-only, so the | |
279 | * clksel_rate flags fields are inaccurate for those clocks. This is | |
280 | * harmless since access to those clocks are gated by the struct clk | |
281 | * flags fields, which mark them as 2420-only. | |
282 | */ | |
283 | static const struct clksel_rate common_clkout_src_core_rates[] = { | |
284 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
285 | { .div = 0 } | |
286 | }; | |
287 | ||
288 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | |
289 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
290 | { .div = 0 } | |
291 | }; | |
292 | ||
293 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | |
294 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
295 | { .div = 0 } | |
296 | }; | |
297 | ||
298 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | |
299 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
300 | { .div = 0 } | |
301 | }; | |
302 | ||
303 | static const struct clksel common_clkout_src_clksel[] = { | |
304 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | |
305 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | |
306 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | |
307 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | |
308 | { .parent = NULL } | |
309 | }; | |
310 | ||
311 | static struct clk sys_clkout_src = { | |
312 | .name = "sys_clkout_src", | |
c1168dc3 | 313 | .ops = &clkops_omap2_dflt, |
e32744b0 | 314 | .parent = &func_54m_ck, |
d1b03f61 | 315 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
316 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
317 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | |
318 | .init = &omap2_init_clksel_parent, | |
319 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | |
320 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | |
321 | .clksel = common_clkout_src_clksel, | |
322 | .recalc = &omap2_clksel_recalc, | |
323 | .round_rate = &omap2_clksel_round_rate, | |
324 | .set_rate = &omap2_clksel_set_rate | |
325 | }; | |
326 | ||
327 | static const struct clksel_rate common_clkout_rates[] = { | |
328 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
329 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, | |
330 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | |
331 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | |
332 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | |
333 | { .div = 0 }, | |
334 | }; | |
335 | ||
336 | static const struct clksel sys_clkout_clksel[] = { | |
337 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | |
338 | { .parent = NULL } | |
046d6b28 TL |
339 | }; |
340 | ||
341 | static struct clk sys_clkout = { | |
342 | .name = "sys_clkout", | |
57137181 | 343 | .ops = &clkops_null, |
e32744b0 | 344 | .parent = &sys_clkout_src, |
d1b03f61 | 345 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
346 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
347 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | |
348 | .clksel = sys_clkout_clksel, | |
349 | .recalc = &omap2_clksel_recalc, | |
350 | .round_rate = &omap2_clksel_round_rate, | |
351 | .set_rate = &omap2_clksel_set_rate | |
352 | }; | |
353 | ||
354 | /* In 2430, new in 2420 ES2 */ | |
355 | static struct clk sys_clkout2_src = { | |
356 | .name = "sys_clkout2_src", | |
c1168dc3 | 357 | .ops = &clkops_omap2_dflt, |
e32744b0 | 358 | .parent = &func_54m_ck, |
d1b03f61 | 359 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
360 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
361 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | |
362 | .init = &omap2_init_clksel_parent, | |
363 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | |
364 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | |
365 | .clksel = common_clkout_src_clksel, | |
046d6b28 | 366 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
367 | .round_rate = &omap2_clksel_round_rate, |
368 | .set_rate = &omap2_clksel_set_rate | |
369 | }; | |
370 | ||
371 | static const struct clksel sys_clkout2_clksel[] = { | |
372 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | |
373 | { .parent = NULL } | |
046d6b28 TL |
374 | }; |
375 | ||
376 | /* In 2430, new in 2420 ES2 */ | |
377 | static struct clk sys_clkout2 = { | |
378 | .name = "sys_clkout2", | |
57137181 | 379 | .ops = &clkops_null, |
e32744b0 | 380 | .parent = &sys_clkout2_src, |
d1b03f61 | 381 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
382 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
383 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | |
384 | .clksel = sys_clkout2_clksel, | |
046d6b28 | 385 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
386 | .round_rate = &omap2_clksel_round_rate, |
387 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
388 | }; |
389 | ||
b824efae TL |
390 | static struct clk emul_ck = { |
391 | .name = "emul_ck", | |
c1168dc3 | 392 | .ops = &clkops_omap2_dflt, |
b824efae | 393 | .parent = &func_54m_ck, |
d1b03f61 | 394 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
395 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, |
396 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | |
397 | .recalc = &followparent_recalc, | |
b824efae TL |
398 | |
399 | }; | |
e32744b0 | 400 | |
046d6b28 TL |
401 | /* |
402 | * MPU clock domain | |
403 | * Clocks: | |
404 | * MPU_FCLK, MPU_ICLK | |
405 | * INT_M_FCLK, INT_M_I_CLK | |
406 | * | |
407 | * - Individual clocks are hardware managed. | |
408 | * - Base divider comes from: CM_CLKSEL_MPU | |
409 | * | |
410 | */ | |
e32744b0 PW |
411 | static const struct clksel_rate mpu_core_rates[] = { |
412 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
413 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
414 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
415 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
416 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
417 | { .div = 0 }, | |
418 | }; | |
419 | ||
420 | static const struct clksel mpu_clksel[] = { | |
421 | { .parent = &core_ck, .rates = mpu_core_rates }, | |
422 | { .parent = NULL } | |
423 | }; | |
424 | ||
046d6b28 TL |
425 | static struct clk mpu_ck = { /* Control cpu */ |
426 | .name = "mpu_ck", | |
897dcded | 427 | .ops = &clkops_null, |
046d6b28 | 428 | .parent = &core_ck, |
3f0a820c | 429 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
d1b03f61 | 430 | .clkdm_name = "mpu_clkdm", |
6b8858a9 PW |
431 | .init = &omap2_init_clksel_parent, |
432 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | |
433 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | |
e32744b0 | 434 | .clksel = mpu_clksel, |
046d6b28 | 435 | .recalc = &omap2_clksel_recalc, |
d1b03f61 | 436 | .round_rate = &omap2_clksel_round_rate, |
6b8858a9 | 437 | .set_rate = &omap2_clksel_set_rate |
046d6b28 | 438 | }; |
e32744b0 | 439 | |
046d6b28 TL |
440 | /* |
441 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | |
442 | * Clocks: | |
e32744b0 | 443 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK |
046d6b28 | 444 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
e32744b0 PW |
445 | * |
446 | * Won't be too specific here. The core clock comes into this block | |
447 | * it is divided then tee'ed. One branch goes directly to xyz enable | |
448 | * controls. The other branch gets further divided by 2 then possibly | |
449 | * routed into a synchronizer and out of clocks abc. | |
046d6b28 | 450 | */ |
e32744b0 PW |
451 | static const struct clksel_rate dsp_fck_core_rates[] = { |
452 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
453 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
454 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
455 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
456 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
457 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
458 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
459 | { .div = 0 }, | |
460 | }; | |
461 | ||
462 | static const struct clksel dsp_fck_clksel[] = { | |
463 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | |
464 | { .parent = NULL } | |
465 | }; | |
466 | ||
467 | static struct clk dsp_fck = { | |
468 | .name = "dsp_fck", | |
b36ee724 | 469 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 470 | .parent = &core_ck, |
3f0a820c | 471 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
d1b03f61 | 472 | .clkdm_name = "dsp_clkdm", |
e32744b0 PW |
473 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
474 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
475 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
476 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | |
477 | .clksel = dsp_fck_clksel, | |
046d6b28 | 478 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
479 | .round_rate = &omap2_clksel_round_rate, |
480 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
481 | }; |
482 | ||
e32744b0 PW |
483 | /* DSP interface clock */ |
484 | static const struct clksel_rate dsp_irate_ick_rates[] = { | |
485 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
486 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
487 | { .div = 3, .val = 3, .flags = RATE_IN_243X }, | |
488 | { .div = 0 }, | |
489 | }; | |
490 | ||
491 | static const struct clksel dsp_irate_ick_clksel[] = { | |
492 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | |
493 | { .parent = NULL } | |
046d6b28 TL |
494 | }; |
495 | ||
d1b03f61 | 496 | /* This clock does not exist as such in the TRM. */ |
e32744b0 PW |
497 | static struct clk dsp_irate_ick = { |
498 | .name = "dsp_irate_ick", | |
57137181 | 499 | .ops = &clkops_null, |
e32744b0 | 500 | .parent = &dsp_fck, |
8ad8ff65 | 501 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
e32744b0 PW |
502 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
503 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | |
504 | .clksel = dsp_irate_ick_clksel, | |
046d6b28 | 505 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
506 | .round_rate = &omap2_clksel_round_rate, |
507 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
508 | }; |
509 | ||
e32744b0 | 510 | /* 2420 only */ |
046d6b28 TL |
511 | static struct clk dsp_ick = { |
512 | .name = "dsp_ick", /* apparently ipi and isp */ | |
b36ee724 | 513 | .ops = &clkops_omap2_dflt_wait, |
e32744b0 | 514 | .parent = &dsp_irate_ick, |
8ad8ff65 | 515 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
e32744b0 PW |
516 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
517 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | |
518 | }; | |
519 | ||
520 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | |
521 | static struct clk iva2_1_ick = { | |
522 | .name = "iva2_1_ick", | |
b36ee724 | 523 | .ops = &clkops_omap2_dflt_wait, |
e32744b0 | 524 | .parent = &dsp_irate_ick, |
8ad8ff65 | 525 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
e32744b0 PW |
526 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
527 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | |
046d6b28 TL |
528 | }; |
529 | ||
d1b03f61 PW |
530 | /* |
531 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | |
532 | * the C54x, but which is contained in the DSP powerdomain. Does not | |
533 | * exist on later OMAPs. | |
534 | */ | |
046d6b28 TL |
535 | static struct clk iva1_ifck = { |
536 | .name = "iva1_ifck", | |
b36ee724 | 537 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 538 | .parent = &core_ck, |
3f0a820c | 539 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, |
d1b03f61 | 540 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
541 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
542 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | |
543 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | |
544 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | |
545 | .clksel = dsp_fck_clksel, | |
046d6b28 | 546 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
547 | .round_rate = &omap2_clksel_round_rate, |
548 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
549 | }; |
550 | ||
551 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | |
552 | static struct clk iva1_mpu_int_ifck = { | |
553 | .name = "iva1_mpu_int_ifck", | |
b36ee724 | 554 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 555 | .parent = &iva1_ifck, |
d1b03f61 | 556 | .clkdm_name = "iva1_clkdm", |
e32744b0 PW |
557 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
558 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | |
559 | .fixed_div = 2, | |
e9b98f60 | 560 | .recalc = &omap_fixed_divisor_recalc, |
046d6b28 TL |
561 | }; |
562 | ||
563 | /* | |
564 | * L3 clock domain | |
565 | * L3 clocks are used for both interface and functional clocks to | |
566 | * multiple entities. Some of these clocks are completely managed | |
567 | * by hardware, and some others allow software control. Hardware | |
568 | * managed ones general are based on directly CLK_REQ signals and | |
569 | * various auto idle settings. The functional spec sets many of these | |
570 | * as 'tie-high' for their enables. | |
571 | * | |
572 | * I-CLOCKS: | |
573 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | |
574 | * CAM, HS-USB. | |
575 | * F-CLOCK | |
576 | * SSI. | |
577 | * | |
578 | * GPMC memories and SDRC have timing and clock sensitive registers which | |
579 | * may very well need notification when the clock changes. Currently for low | |
580 | * operating points, these are taken care of in sleep.S. | |
581 | */ | |
e32744b0 PW |
582 | static const struct clksel_rate core_l3_core_rates[] = { |
583 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
584 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
585 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
586 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
587 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
588 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
589 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | |
590 | { .div = 0 } | |
591 | }; | |
592 | ||
593 | static const struct clksel core_l3_clksel[] = { | |
594 | { .parent = &core_ck, .rates = core_l3_core_rates }, | |
595 | { .parent = NULL } | |
596 | }; | |
597 | ||
046d6b28 TL |
598 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
599 | .name = "core_l3_ck", | |
897dcded | 600 | .ops = &clkops_null, |
046d6b28 | 601 | .parent = &core_ck, |
3f0a820c | 602 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
d1b03f61 | 603 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
604 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
605 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | |
606 | .clksel = core_l3_clksel, | |
046d6b28 | 607 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
608 | .round_rate = &omap2_clksel_round_rate, |
609 | .set_rate = &omap2_clksel_set_rate | |
610 | }; | |
611 | ||
612 | /* usb_l4_ick */ | |
613 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | |
614 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
615 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
616 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
617 | { .div = 0 } | |
618 | }; | |
619 | ||
620 | static const struct clksel usb_l4_ick_clksel[] = { | |
621 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | |
622 | { .parent = NULL }, | |
046d6b28 TL |
623 | }; |
624 | ||
d1b03f61 | 625 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
046d6b28 TL |
626 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
627 | .name = "usb_l4_ick", | |
b36ee724 | 628 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 629 | .parent = &core_l3_ck, |
8ad8ff65 | 630 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
d1b03f61 | 631 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
633 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
634 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
635 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | |
636 | .clksel = usb_l4_ick_clksel, | |
046d6b28 | 637 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
638 | .round_rate = &omap2_clksel_round_rate, |
639 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
640 | }; |
641 | ||
d1b03f61 PW |
642 | /* |
643 | * L4 clock management domain | |
644 | * | |
645 | * This domain contains lots of interface clocks from the L4 interface, some | |
646 | * functional clocks. Fixed APLL functional source clocks are managed in | |
647 | * this domain. | |
648 | */ | |
649 | static const struct clksel_rate l4_core_l3_rates[] = { | |
650 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
651 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
652 | { .div = 0 } | |
653 | }; | |
654 | ||
655 | static const struct clksel l4_clksel[] = { | |
656 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | |
657 | { .parent = NULL } | |
658 | }; | |
659 | ||
660 | static struct clk l4_ck = { /* used both as an ick and fck */ | |
661 | .name = "l4_ck", | |
897dcded | 662 | .ops = &clkops_null, |
d1b03f61 | 663 | .parent = &core_l3_ck, |
3f0a820c | 664 | .flags = DELAYED_APP, |
d1b03f61 PW |
665 | .clkdm_name = "core_l4_clkdm", |
666 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
667 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | |
668 | .clksel = l4_clksel, | |
669 | .recalc = &omap2_clksel_recalc, | |
670 | .round_rate = &omap2_clksel_round_rate, | |
671 | .set_rate = &omap2_clksel_set_rate | |
672 | }; | |
673 | ||
046d6b28 TL |
674 | /* |
675 | * SSI is in L3 management domain, its direct parent is core not l3, | |
676 | * many core power domain entities are grouped into the L3 clock | |
677 | * domain. | |
d1b03f61 | 678 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
046d6b28 TL |
679 | * |
680 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | |
681 | */ | |
e32744b0 PW |
682 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
683 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
684 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
685 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
686 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
687 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | |
688 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
689 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
690 | { .div = 0 } | |
691 | }; | |
692 | ||
693 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |
694 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | |
695 | { .parent = NULL } | |
696 | }; | |
697 | ||
046d6b28 TL |
698 | static struct clk ssi_ssr_sst_fck = { |
699 | .name = "ssi_fck", | |
b36ee724 | 700 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 701 | .parent = &core_ck, |
8ad8ff65 | 702 | .flags = DELAYED_APP, |
d1b03f61 | 703 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
704 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
705 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
706 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
707 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | |
708 | .clksel = ssi_ssr_sst_fck_clksel, | |
046d6b28 | 709 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
710 | .round_rate = &omap2_clksel_round_rate, |
711 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
712 | }; |
713 | ||
9299fd85 PW |
714 | /* |
715 | * Presumably this is the same as SSI_ICLK. | |
716 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | |
717 | */ | |
718 | static struct clk ssi_l4_ick = { | |
719 | .name = "ssi_l4_ick", | |
720 | .ops = &clkops_omap2_dflt_wait, | |
721 | .parent = &l4_ck, | |
722 | .clkdm_name = "core_l4_clkdm", | |
723 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
724 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | |
725 | .recalc = &followparent_recalc, | |
726 | }; | |
727 | ||
d1b03f61 | 728 | |
046d6b28 TL |
729 | /* |
730 | * GFX clock domain | |
731 | * Clocks: | |
732 | * GFX_FCLK, GFX_ICLK | |
733 | * GFX_CG1(2d), GFX_CG2(3d) | |
734 | * | |
735 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | |
736 | * The 2d and 3d clocks run at a hardware determined | |
737 | * divided value of fclk. | |
738 | * | |
739 | */ | |
e32744b0 PW |
740 | /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ |
741 | ||
742 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | |
743 | static const struct clksel gfx_fck_clksel[] = { | |
744 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | |
745 | { .parent = NULL }, | |
746 | }; | |
747 | ||
046d6b28 TL |
748 | static struct clk gfx_3d_fck = { |
749 | .name = "gfx_3d_fck", | |
b36ee724 | 750 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 751 | .parent = &core_l3_ck, |
d1b03f61 | 752 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
753 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
754 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | |
755 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
756 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
757 | .clksel = gfx_fck_clksel, | |
046d6b28 | 758 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
759 | .round_rate = &omap2_clksel_round_rate, |
760 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
761 | }; |
762 | ||
763 | static struct clk gfx_2d_fck = { | |
764 | .name = "gfx_2d_fck", | |
b36ee724 | 765 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 766 | .parent = &core_l3_ck, |
d1b03f61 | 767 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
768 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
769 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | |
770 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
771 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
772 | .clksel = gfx_fck_clksel, | |
046d6b28 | 773 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
774 | .round_rate = &omap2_clksel_round_rate, |
775 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
776 | }; |
777 | ||
778 | static struct clk gfx_ick = { | |
779 | .name = "gfx_ick", /* From l3 */ | |
b36ee724 | 780 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 781 | .parent = &core_l3_ck, |
d1b03f61 | 782 | .clkdm_name = "gfx_clkdm", |
e32744b0 PW |
783 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
784 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
785 | .recalc = &followparent_recalc, | |
046d6b28 TL |
786 | }; |
787 | ||
788 | /* | |
789 | * Modem clock domain (2430) | |
790 | * CLOCKS: | |
791 | * MDM_OSC_CLK | |
792 | * MDM_ICLK | |
e32744b0 | 793 | * These clocks are usable in chassis mode only. |
046d6b28 | 794 | */ |
e32744b0 PW |
795 | static const struct clksel_rate mdm_ick_core_rates[] = { |
796 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, | |
797 | { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, | |
798 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, | |
799 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, | |
800 | { .div = 0 } | |
801 | }; | |
802 | ||
803 | static const struct clksel mdm_ick_clksel[] = { | |
804 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, | |
805 | { .parent = NULL } | |
806 | }; | |
807 | ||
046d6b28 TL |
808 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
809 | .name = "mdm_ick", | |
b36ee724 | 810 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 811 | .parent = &core_ck, |
8ad8ff65 | 812 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
d1b03f61 | 813 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
814 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
815 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | |
816 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | |
817 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | |
818 | .clksel = mdm_ick_clksel, | |
046d6b28 | 819 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
820 | .round_rate = &omap2_clksel_round_rate, |
821 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
822 | }; |
823 | ||
824 | static struct clk mdm_osc_ck = { | |
825 | .name = "mdm_osc_ck", | |
b36ee724 | 826 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 827 | .parent = &osc_ck, |
d1b03f61 | 828 | .clkdm_name = "mdm_clkdm", |
e32744b0 PW |
829 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
830 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | |
831 | .recalc = &followparent_recalc, | |
046d6b28 TL |
832 | }; |
833 | ||
046d6b28 TL |
834 | /* |
835 | * DSS clock domain | |
836 | * CLOCKs: | |
837 | * DSS_L4_ICLK, DSS_L3_ICLK, | |
838 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | |
839 | * | |
840 | * DSS is both initiator and target. | |
841 | */ | |
e32744b0 PW |
842 | /* XXX Add RATE_NOT_VALIDATED */ |
843 | ||
844 | static const struct clksel_rate dss1_fck_sys_rates[] = { | |
845 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
846 | { .div = 0 } | |
847 | }; | |
848 | ||
849 | static const struct clksel_rate dss1_fck_core_rates[] = { | |
850 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | |
851 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | |
852 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | |
853 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | |
854 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | |
855 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | |
856 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | |
857 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | |
858 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | |
859 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
860 | { .div = 0 } | |
861 | }; | |
862 | ||
863 | static const struct clksel dss1_fck_clksel[] = { | |
864 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | |
865 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | |
866 | { .parent = NULL }, | |
867 | }; | |
868 | ||
046d6b28 TL |
869 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
870 | .name = "dss_ick", | |
bc51da4e | 871 | .ops = &clkops_omap2_dflt, |
046d6b28 | 872 | .parent = &l4_ck, /* really both l3 and l4 */ |
d1b03f61 | 873 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
875 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
876 | .recalc = &followparent_recalc, | |
046d6b28 TL |
877 | }; |
878 | ||
879 | static struct clk dss1_fck = { | |
880 | .name = "dss1_fck", | |
bc51da4e | 881 | .ops = &clkops_omap2_dflt, |
046d6b28 | 882 | .parent = &core_ck, /* Core or sys */ |
8ad8ff65 | 883 | .flags = DELAYED_APP, |
d1b03f61 | 884 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
886 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | |
887 | .init = &omap2_init_clksel_parent, | |
888 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
889 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | |
890 | .clksel = dss1_fck_clksel, | |
046d6b28 | 891 | .recalc = &omap2_clksel_recalc, |
e32744b0 PW |
892 | .round_rate = &omap2_clksel_round_rate, |
893 | .set_rate = &omap2_clksel_set_rate | |
894 | }; | |
895 | ||
896 | static const struct clksel_rate dss2_fck_sys_rates[] = { | |
897 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
898 | { .div = 0 } | |
899 | }; | |
900 | ||
901 | static const struct clksel_rate dss2_fck_48m_rates[] = { | |
902 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
903 | { .div = 0 } | |
904 | }; | |
905 | ||
906 | static const struct clksel dss2_fck_clksel[] = { | |
907 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | |
908 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | |
909 | { .parent = NULL } | |
046d6b28 TL |
910 | }; |
911 | ||
912 | static struct clk dss2_fck = { /* Alt clk used in power management */ | |
913 | .name = "dss2_fck", | |
bc51da4e | 914 | .ops = &clkops_omap2_dflt, |
046d6b28 | 915 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
8ad8ff65 | 916 | .flags = DELAYED_APP, |
d1b03f61 | 917 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
918 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
919 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | |
920 | .init = &omap2_init_clksel_parent, | |
921 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
922 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | |
923 | .clksel = dss2_fck_clksel, | |
924 | .recalc = &followparent_recalc, | |
046d6b28 TL |
925 | }; |
926 | ||
927 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |
928 | .name = "dss_54m_fck", /* 54m tv clk */ | |
b36ee724 | 929 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 930 | .parent = &func_54m_ck, |
d1b03f61 | 931 | .clkdm_name = "dss_clkdm", |
e32744b0 PW |
932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
933 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | |
934 | .recalc = &followparent_recalc, | |
046d6b28 TL |
935 | }; |
936 | ||
937 | /* | |
938 | * CORE power domain ICLK & FCLK defines. | |
939 | * Many of the these can have more than one possible parent. Entries | |
940 | * here will likely have an L4 interface parent, and may have multiple | |
941 | * functional clock parents. | |
942 | */ | |
e32744b0 PW |
943 | static const struct clksel_rate gpt_alt_rates[] = { |
944 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | |
945 | { .div = 0 } | |
946 | }; | |
947 | ||
948 | static const struct clksel omap24xx_gpt_clksel[] = { | |
949 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | |
950 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
951 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | |
952 | { .parent = NULL }, | |
953 | }; | |
954 | ||
046d6b28 TL |
955 | static struct clk gpt1_ick = { |
956 | .name = "gpt1_ick", | |
b36ee724 | 957 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 958 | .parent = &l4_ck, |
d1b03f61 | 959 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
960 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
961 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
962 | .recalc = &followparent_recalc, | |
046d6b28 TL |
963 | }; |
964 | ||
965 | static struct clk gpt1_fck = { | |
966 | .name = "gpt1_fck", | |
b36ee724 | 967 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 968 | .parent = &func_32k_ck, |
d1b03f61 | 969 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
970 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
971 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | |
972 | .init = &omap2_init_clksel_parent, | |
973 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | |
974 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | |
975 | .clksel = omap24xx_gpt_clksel, | |
976 | .recalc = &omap2_clksel_recalc, | |
977 | .round_rate = &omap2_clksel_round_rate, | |
978 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
979 | }; |
980 | ||
981 | static struct clk gpt2_ick = { | |
982 | .name = "gpt2_ick", | |
b36ee724 | 983 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 984 | .parent = &l4_ck, |
d1b03f61 | 985 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
986 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
987 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
988 | .recalc = &followparent_recalc, | |
046d6b28 TL |
989 | }; |
990 | ||
991 | static struct clk gpt2_fck = { | |
992 | .name = "gpt2_fck", | |
b36ee724 | 993 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 994 | .parent = &func_32k_ck, |
d1b03f61 | 995 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
996 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
997 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | |
998 | .init = &omap2_init_clksel_parent, | |
999 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1000 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | |
1001 | .clksel = omap24xx_gpt_clksel, | |
1002 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1003 | }; |
1004 | ||
1005 | static struct clk gpt3_ick = { | |
1006 | .name = "gpt3_ick", | |
b36ee724 | 1007 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1008 | .parent = &l4_ck, |
d1b03f61 | 1009 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1010 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1011 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
1012 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1013 | }; |
1014 | ||
1015 | static struct clk gpt3_fck = { | |
1016 | .name = "gpt3_fck", | |
b36ee724 | 1017 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1018 | .parent = &func_32k_ck, |
d1b03f61 | 1019 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1020 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1021 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | |
1022 | .init = &omap2_init_clksel_parent, | |
1023 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1024 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | |
1025 | .clksel = omap24xx_gpt_clksel, | |
1026 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1027 | }; |
1028 | ||
1029 | static struct clk gpt4_ick = { | |
1030 | .name = "gpt4_ick", | |
b36ee724 | 1031 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1032 | .parent = &l4_ck, |
d1b03f61 | 1033 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1034 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1035 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
1036 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1037 | }; |
1038 | ||
1039 | static struct clk gpt4_fck = { | |
1040 | .name = "gpt4_fck", | |
b36ee724 | 1041 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1042 | .parent = &func_32k_ck, |
d1b03f61 | 1043 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1044 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1045 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | |
1046 | .init = &omap2_init_clksel_parent, | |
1047 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1048 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | |
1049 | .clksel = omap24xx_gpt_clksel, | |
1050 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1051 | }; |
1052 | ||
1053 | static struct clk gpt5_ick = { | |
1054 | .name = "gpt5_ick", | |
b36ee724 | 1055 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1056 | .parent = &l4_ck, |
d1b03f61 | 1057 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1058 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1059 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
1060 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1061 | }; |
1062 | ||
1063 | static struct clk gpt5_fck = { | |
1064 | .name = "gpt5_fck", | |
b36ee724 | 1065 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1066 | .parent = &func_32k_ck, |
d1b03f61 | 1067 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1068 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1069 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | |
1070 | .init = &omap2_init_clksel_parent, | |
1071 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1072 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | |
1073 | .clksel = omap24xx_gpt_clksel, | |
1074 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1075 | }; |
1076 | ||
1077 | static struct clk gpt6_ick = { | |
1078 | .name = "gpt6_ick", | |
b36ee724 | 1079 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1080 | .parent = &l4_ck, |
d1b03f61 | 1081 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1082 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1083 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
1084 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1085 | }; |
1086 | ||
1087 | static struct clk gpt6_fck = { | |
1088 | .name = "gpt6_fck", | |
b36ee724 | 1089 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1090 | .parent = &func_32k_ck, |
d1b03f61 | 1091 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1092 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1093 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | |
1094 | .init = &omap2_init_clksel_parent, | |
1095 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1096 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | |
1097 | .clksel = omap24xx_gpt_clksel, | |
1098 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1099 | }; |
1100 | ||
1101 | static struct clk gpt7_ick = { | |
1102 | .name = "gpt7_ick", | |
b36ee724 | 1103 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1104 | .parent = &l4_ck, |
e32744b0 PW |
1105 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1106 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
1107 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1108 | }; |
1109 | ||
1110 | static struct clk gpt7_fck = { | |
1111 | .name = "gpt7_fck", | |
b36ee724 | 1112 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1113 | .parent = &func_32k_ck, |
d1b03f61 | 1114 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1115 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1116 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | |
1117 | .init = &omap2_init_clksel_parent, | |
1118 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1119 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | |
1120 | .clksel = omap24xx_gpt_clksel, | |
1121 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1122 | }; |
1123 | ||
1124 | static struct clk gpt8_ick = { | |
1125 | .name = "gpt8_ick", | |
b36ee724 | 1126 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1127 | .parent = &l4_ck, |
d1b03f61 | 1128 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1129 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1130 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1131 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1132 | }; |
1133 | ||
1134 | static struct clk gpt8_fck = { | |
1135 | .name = "gpt8_fck", | |
b36ee724 | 1136 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1137 | .parent = &func_32k_ck, |
d1b03f61 | 1138 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1139 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1140 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | |
1141 | .init = &omap2_init_clksel_parent, | |
1142 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1143 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | |
1144 | .clksel = omap24xx_gpt_clksel, | |
1145 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1146 | }; |
1147 | ||
1148 | static struct clk gpt9_ick = { | |
1149 | .name = "gpt9_ick", | |
b36ee724 | 1150 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1151 | .parent = &l4_ck, |
d1b03f61 | 1152 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1154 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1155 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1156 | }; |
1157 | ||
1158 | static struct clk gpt9_fck = { | |
1159 | .name = "gpt9_fck", | |
b36ee724 | 1160 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1161 | .parent = &func_32k_ck, |
d1b03f61 | 1162 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1164 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | |
1165 | .init = &omap2_init_clksel_parent, | |
1166 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1167 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | |
1168 | .clksel = omap24xx_gpt_clksel, | |
1169 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1170 | }; |
1171 | ||
1172 | static struct clk gpt10_ick = { | |
1173 | .name = "gpt10_ick", | |
b36ee724 | 1174 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1175 | .parent = &l4_ck, |
d1b03f61 | 1176 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1177 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1178 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1179 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1180 | }; |
1181 | ||
1182 | static struct clk gpt10_fck = { | |
1183 | .name = "gpt10_fck", | |
b36ee724 | 1184 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1185 | .parent = &func_32k_ck, |
d1b03f61 | 1186 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1187 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1188 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | |
1189 | .init = &omap2_init_clksel_parent, | |
1190 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1191 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | |
1192 | .clksel = omap24xx_gpt_clksel, | |
1193 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1194 | }; |
1195 | ||
1196 | static struct clk gpt11_ick = { | |
1197 | .name = "gpt11_ick", | |
b36ee724 | 1198 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1199 | .parent = &l4_ck, |
d1b03f61 | 1200 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1202 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1203 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1204 | }; |
1205 | ||
1206 | static struct clk gpt11_fck = { | |
1207 | .name = "gpt11_fck", | |
b36ee724 | 1208 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1209 | .parent = &func_32k_ck, |
d1b03f61 | 1210 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1212 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | |
1213 | .init = &omap2_init_clksel_parent, | |
1214 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1215 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | |
1216 | .clksel = omap24xx_gpt_clksel, | |
1217 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1218 | }; |
1219 | ||
1220 | static struct clk gpt12_ick = { | |
1221 | .name = "gpt12_ick", | |
b36ee724 | 1222 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1223 | .parent = &l4_ck, |
d1b03f61 | 1224 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1225 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1226 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1227 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1228 | }; |
1229 | ||
1230 | static struct clk gpt12_fck = { | |
1231 | .name = "gpt12_fck", | |
b36ee724 | 1232 | .ops = &clkops_omap2_dflt_wait, |
f248076c | 1233 | .parent = &secure_32k_ck, |
d1b03f61 | 1234 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1235 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1236 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | |
1237 | .init = &omap2_init_clksel_parent, | |
1238 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | |
1239 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | |
1240 | .clksel = omap24xx_gpt_clksel, | |
1241 | .recalc = &omap2_clksel_recalc, | |
046d6b28 TL |
1242 | }; |
1243 | ||
1244 | static struct clk mcbsp1_ick = { | |
44ec9a33 | 1245 | .name = "mcbsp_ick", |
b36ee724 | 1246 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1247 | .id = 1, |
046d6b28 | 1248 | .parent = &l4_ck, |
d1b03f61 | 1249 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1250 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1251 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1252 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1253 | }; |
1254 | ||
1255 | static struct clk mcbsp1_fck = { | |
44ec9a33 | 1256 | .name = "mcbsp_fck", |
b36ee724 | 1257 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1258 | .id = 1, |
046d6b28 | 1259 | .parent = &func_96m_ck, |
d1b03f61 | 1260 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1262 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1263 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1264 | }; |
1265 | ||
1266 | static struct clk mcbsp2_ick = { | |
44ec9a33 | 1267 | .name = "mcbsp_ick", |
b36ee724 | 1268 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1269 | .id = 2, |
046d6b28 | 1270 | .parent = &l4_ck, |
d1b03f61 | 1271 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1273 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1274 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1275 | }; |
1276 | ||
1277 | static struct clk mcbsp2_fck = { | |
44ec9a33 | 1278 | .name = "mcbsp_fck", |
b36ee724 | 1279 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1280 | .id = 2, |
046d6b28 | 1281 | .parent = &func_96m_ck, |
d1b03f61 | 1282 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1284 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1285 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1286 | }; |
1287 | ||
1288 | static struct clk mcbsp3_ick = { | |
44ec9a33 | 1289 | .name = "mcbsp_ick", |
b36ee724 | 1290 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1291 | .id = 3, |
046d6b28 | 1292 | .parent = &l4_ck, |
d1b03f61 | 1293 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1295 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1296 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1297 | }; |
1298 | ||
1299 | static struct clk mcbsp3_fck = { | |
44ec9a33 | 1300 | .name = "mcbsp_fck", |
b36ee724 | 1301 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1302 | .id = 3, |
046d6b28 | 1303 | .parent = &func_96m_ck, |
d1b03f61 | 1304 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1305 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1306 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1307 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1308 | }; |
1309 | ||
1310 | static struct clk mcbsp4_ick = { | |
44ec9a33 | 1311 | .name = "mcbsp_ick", |
b36ee724 | 1312 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1313 | .id = 4, |
046d6b28 | 1314 | .parent = &l4_ck, |
d1b03f61 | 1315 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1316 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1317 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1318 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1319 | }; |
1320 | ||
1321 | static struct clk mcbsp4_fck = { | |
44ec9a33 | 1322 | .name = "mcbsp_fck", |
b36ee724 | 1323 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1324 | .id = 4, |
046d6b28 | 1325 | .parent = &func_96m_ck, |
d1b03f61 | 1326 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1328 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1329 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1330 | }; |
1331 | ||
1332 | static struct clk mcbsp5_ick = { | |
44ec9a33 | 1333 | .name = "mcbsp_ick", |
b36ee724 | 1334 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1335 | .id = 5, |
046d6b28 | 1336 | .parent = &l4_ck, |
d1b03f61 | 1337 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1339 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1340 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1341 | }; |
1342 | ||
1343 | static struct clk mcbsp5_fck = { | |
44ec9a33 | 1344 | .name = "mcbsp_fck", |
b36ee724 | 1345 | .ops = &clkops_omap2_dflt_wait, |
44ec9a33 | 1346 | .id = 5, |
046d6b28 | 1347 | .parent = &func_96m_ck, |
d1b03f61 | 1348 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1350 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1351 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1352 | }; |
1353 | ||
1354 | static struct clk mcspi1_ick = { | |
90afd5cb | 1355 | .name = "mcspi_ick", |
b36ee724 | 1356 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1357 | .id = 1, |
046d6b28 | 1358 | .parent = &l4_ck, |
d1b03f61 | 1359 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1361 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1362 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1363 | }; |
1364 | ||
1365 | static struct clk mcspi1_fck = { | |
90afd5cb | 1366 | .name = "mcspi_fck", |
b36ee724 | 1367 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1368 | .id = 1, |
046d6b28 | 1369 | .parent = &func_48m_ck, |
d1b03f61 | 1370 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1372 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1373 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1374 | }; |
1375 | ||
1376 | static struct clk mcspi2_ick = { | |
90afd5cb | 1377 | .name = "mcspi_ick", |
b36ee724 | 1378 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1379 | .id = 2, |
046d6b28 | 1380 | .parent = &l4_ck, |
d1b03f61 | 1381 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1383 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1384 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1385 | }; |
1386 | ||
1387 | static struct clk mcspi2_fck = { | |
90afd5cb | 1388 | .name = "mcspi_fck", |
b36ee724 | 1389 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1390 | .id = 2, |
046d6b28 | 1391 | .parent = &func_48m_ck, |
d1b03f61 | 1392 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1394 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1395 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1396 | }; |
1397 | ||
1398 | static struct clk mcspi3_ick = { | |
90afd5cb | 1399 | .name = "mcspi_ick", |
b36ee724 | 1400 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1401 | .id = 3, |
046d6b28 | 1402 | .parent = &l4_ck, |
d1b03f61 | 1403 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1405 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1406 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1407 | }; |
1408 | ||
1409 | static struct clk mcspi3_fck = { | |
90afd5cb | 1410 | .name = "mcspi_fck", |
b36ee724 | 1411 | .ops = &clkops_omap2_dflt_wait, |
90afd5cb | 1412 | .id = 3, |
046d6b28 | 1413 | .parent = &func_48m_ck, |
d1b03f61 | 1414 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1416 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1417 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1418 | }; |
1419 | ||
1420 | static struct clk uart1_ick = { | |
1421 | .name = "uart1_ick", | |
b36ee724 | 1422 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1423 | .parent = &l4_ck, |
d1b03f61 | 1424 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1425 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1426 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1427 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1428 | }; |
1429 | ||
1430 | static struct clk uart1_fck = { | |
1431 | .name = "uart1_fck", | |
b36ee724 | 1432 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1433 | .parent = &func_48m_ck, |
d1b03f61 | 1434 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1435 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1436 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | |
1437 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1438 | }; |
1439 | ||
1440 | static struct clk uart2_ick = { | |
1441 | .name = "uart2_ick", | |
b36ee724 | 1442 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1443 | .parent = &l4_ck, |
d1b03f61 | 1444 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1445 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1446 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1447 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1448 | }; |
1449 | ||
1450 | static struct clk uart2_fck = { | |
1451 | .name = "uart2_fck", | |
b36ee724 | 1452 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1453 | .parent = &func_48m_ck, |
d1b03f61 | 1454 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1455 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1456 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | |
1457 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1458 | }; |
1459 | ||
1460 | static struct clk uart3_ick = { | |
1461 | .name = "uart3_ick", | |
b36ee724 | 1462 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1463 | .parent = &l4_ck, |
d1b03f61 | 1464 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1465 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1466 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1467 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1468 | }; |
1469 | ||
1470 | static struct clk uart3_fck = { | |
1471 | .name = "uart3_fck", | |
b36ee724 | 1472 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1473 | .parent = &func_48m_ck, |
d1b03f61 | 1474 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1475 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1476 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | |
1477 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1478 | }; |
1479 | ||
1480 | static struct clk gpios_ick = { | |
1481 | .name = "gpios_ick", | |
b36ee724 | 1482 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1483 | .parent = &l4_ck, |
d1b03f61 | 1484 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1485 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1486 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1487 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1488 | }; |
1489 | ||
1490 | static struct clk gpios_fck = { | |
1491 | .name = "gpios_fck", | |
b36ee724 | 1492 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1493 | .parent = &func_32k_ck, |
d1b03f61 | 1494 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1495 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1496 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1497 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1498 | }; |
1499 | ||
1500 | static struct clk mpu_wdt_ick = { | |
1501 | .name = "mpu_wdt_ick", | |
b36ee724 | 1502 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1503 | .parent = &l4_ck, |
d1b03f61 | 1504 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1505 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1506 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1507 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1508 | }; |
1509 | ||
1510 | static struct clk mpu_wdt_fck = { | |
1511 | .name = "mpu_wdt_fck", | |
b36ee724 | 1512 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1513 | .parent = &func_32k_ck, |
d1b03f61 | 1514 | .clkdm_name = "wkup_clkdm", |
e32744b0 PW |
1515 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1516 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
1517 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1518 | }; |
1519 | ||
1520 | static struct clk sync_32k_ick = { | |
1521 | .name = "sync_32k_ick", | |
b36ee724 | 1522 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1523 | .parent = &l4_ck, |
8ad8ff65 | 1524 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1525 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1526 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1527 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | |
1528 | .recalc = &followparent_recalc, | |
046d6b28 | 1529 | }; |
d1b03f61 | 1530 | |
046d6b28 TL |
1531 | static struct clk wdt1_ick = { |
1532 | .name = "wdt1_ick", | |
b36ee724 | 1533 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1534 | .parent = &l4_ck, |
d1b03f61 | 1535 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1536 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1537 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | |
1538 | .recalc = &followparent_recalc, | |
046d6b28 | 1539 | }; |
d1b03f61 | 1540 | |
046d6b28 TL |
1541 | static struct clk omapctrl_ick = { |
1542 | .name = "omapctrl_ick", | |
b36ee724 | 1543 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1544 | .parent = &l4_ck, |
8ad8ff65 | 1545 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1546 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1547 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1548 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | |
1549 | .recalc = &followparent_recalc, | |
046d6b28 | 1550 | }; |
d1b03f61 | 1551 | |
046d6b28 TL |
1552 | static struct clk icr_ick = { |
1553 | .name = "icr_ick", | |
b36ee724 | 1554 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1555 | .parent = &l4_ck, |
d1b03f61 | 1556 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1557 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1558 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | |
1559 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1560 | }; |
1561 | ||
1562 | static struct clk cam_ick = { | |
1563 | .name = "cam_ick", | |
bc51da4e | 1564 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1565 | .parent = &l4_ck, |
d1b03f61 | 1566 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1567 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1568 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1569 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1570 | }; |
1571 | ||
d1b03f61 PW |
1572 | /* |
1573 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | |
1574 | * split into two separate clocks, since the parent clocks are different | |
1575 | * and the clockdomains are also different. | |
1576 | */ | |
046d6b28 TL |
1577 | static struct clk cam_fck = { |
1578 | .name = "cam_fck", | |
bc51da4e | 1579 | .ops = &clkops_omap2_dflt, |
046d6b28 | 1580 | .parent = &func_96m_ck, |
d1b03f61 | 1581 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1582 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1583 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | |
1584 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1585 | }; |
1586 | ||
1587 | static struct clk mailboxes_ick = { | |
1588 | .name = "mailboxes_ick", | |
b36ee724 | 1589 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1590 | .parent = &l4_ck, |
d1b03f61 | 1591 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1592 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1593 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1594 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1595 | }; |
1596 | ||
1597 | static struct clk wdt4_ick = { | |
1598 | .name = "wdt4_ick", | |
b36ee724 | 1599 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1600 | .parent = &l4_ck, |
d1b03f61 | 1601 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1602 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1603 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1604 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1605 | }; |
1606 | ||
1607 | static struct clk wdt4_fck = { | |
1608 | .name = "wdt4_fck", | |
b36ee724 | 1609 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1610 | .parent = &func_32k_ck, |
d1b03f61 | 1611 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1612 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1613 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | |
1614 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1615 | }; |
1616 | ||
1617 | static struct clk wdt3_ick = { | |
1618 | .name = "wdt3_ick", | |
b36ee724 | 1619 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1620 | .parent = &l4_ck, |
d1b03f61 | 1621 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1623 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1624 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1625 | }; |
1626 | ||
1627 | static struct clk wdt3_fck = { | |
1628 | .name = "wdt3_fck", | |
b36ee724 | 1629 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1630 | .parent = &func_32k_ck, |
d1b03f61 | 1631 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1633 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | |
1634 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1635 | }; |
1636 | ||
1637 | static struct clk mspro_ick = { | |
1638 | .name = "mspro_ick", | |
b36ee724 | 1639 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1640 | .parent = &l4_ck, |
d1b03f61 | 1641 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1642 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1643 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1644 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1645 | }; |
1646 | ||
1647 | static struct clk mspro_fck = { | |
1648 | .name = "mspro_fck", | |
b36ee724 | 1649 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1650 | .parent = &func_96m_ck, |
d1b03f61 | 1651 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1653 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | |
1654 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1655 | }; |
1656 | ||
1657 | static struct clk mmc_ick = { | |
1658 | .name = "mmc_ick", | |
b36ee724 | 1659 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1660 | .parent = &l4_ck, |
d1b03f61 | 1661 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1662 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1663 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1664 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1665 | }; |
1666 | ||
1667 | static struct clk mmc_fck = { | |
1668 | .name = "mmc_fck", | |
b36ee724 | 1669 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1670 | .parent = &func_96m_ck, |
d1b03f61 | 1671 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1673 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | |
1674 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1675 | }; |
1676 | ||
1677 | static struct clk fac_ick = { | |
1678 | .name = "fac_ick", | |
b36ee724 | 1679 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1680 | .parent = &l4_ck, |
d1b03f61 | 1681 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1682 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1683 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1684 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1685 | }; |
1686 | ||
1687 | static struct clk fac_fck = { | |
1688 | .name = "fac_fck", | |
b36ee724 | 1689 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1690 | .parent = &func_12m_ck, |
d1b03f61 | 1691 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1692 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1693 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | |
1694 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1695 | }; |
1696 | ||
1697 | static struct clk eac_ick = { | |
1698 | .name = "eac_ick", | |
b36ee724 | 1699 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1700 | .parent = &l4_ck, |
d1b03f61 | 1701 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1703 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1704 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1705 | }; |
1706 | ||
1707 | static struct clk eac_fck = { | |
1708 | .name = "eac_fck", | |
b36ee724 | 1709 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1710 | .parent = &func_96m_ck, |
d1b03f61 | 1711 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1713 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | |
1714 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1715 | }; |
1716 | ||
1717 | static struct clk hdq_ick = { | |
1718 | .name = "hdq_ick", | |
b36ee724 | 1719 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1720 | .parent = &l4_ck, |
d1b03f61 | 1721 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1723 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1724 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1725 | }; |
1726 | ||
1727 | static struct clk hdq_fck = { | |
1728 | .name = "hdq_fck", | |
b36ee724 | 1729 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1730 | .parent = &func_12m_ck, |
d1b03f61 | 1731 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1732 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1733 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | |
1734 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1735 | }; |
1736 | ||
1737 | static struct clk i2c2_ick = { | |
b824efae | 1738 | .name = "i2c_ick", |
b36ee724 | 1739 | .ops = &clkops_omap2_dflt_wait, |
b824efae | 1740 | .id = 2, |
046d6b28 | 1741 | .parent = &l4_ck, |
d1b03f61 | 1742 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1743 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1744 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1745 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1746 | }; |
1747 | ||
1748 | static struct clk i2c2_fck = { | |
b824efae | 1749 | .name = "i2c_fck", |
b36ee724 | 1750 | .ops = &clkops_omap2_dflt_wait, |
b824efae | 1751 | .id = 2, |
046d6b28 | 1752 | .parent = &func_12m_ck, |
d1b03f61 | 1753 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1754 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1755 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | |
1756 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1757 | }; |
1758 | ||
1759 | static struct clk i2chs2_fck = { | |
4574eb68 | 1760 | .name = "i2c_fck", |
3dc21975 | 1761 | .ops = &clkops_omap2430_i2chs_wait, |
e32744b0 | 1762 | .id = 2, |
046d6b28 | 1763 | .parent = &func_96m_ck, |
d1b03f61 | 1764 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1766 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
1767 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1768 | }; |
1769 | ||
1770 | static struct clk i2c1_ick = { | |
b824efae | 1771 | .name = "i2c_ick", |
b36ee724 | 1772 | .ops = &clkops_omap2_dflt_wait, |
b824efae | 1773 | .id = 1, |
046d6b28 | 1774 | .parent = &l4_ck, |
d1b03f61 | 1775 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1777 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1778 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1779 | }; |
1780 | ||
1781 | static struct clk i2c1_fck = { | |
b824efae | 1782 | .name = "i2c_fck", |
b36ee724 | 1783 | .ops = &clkops_omap2_dflt_wait, |
b824efae | 1784 | .id = 1, |
046d6b28 | 1785 | .parent = &func_12m_ck, |
d1b03f61 | 1786 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1787 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1788 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | |
1789 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1790 | }; |
1791 | ||
1792 | static struct clk i2chs1_fck = { | |
4574eb68 | 1793 | .name = "i2c_fck", |
3dc21975 | 1794 | .ops = &clkops_omap2430_i2chs_wait, |
e32744b0 | 1795 | .id = 1, |
046d6b28 | 1796 | .parent = &func_96m_ck, |
d1b03f61 | 1797 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1799 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
1800 | .recalc = &followparent_recalc, | |
1801 | }; | |
1802 | ||
1803 | static struct clk gpmc_fck = { | |
1804 | .name = "gpmc_fck", | |
897dcded | 1805 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1806 | .parent = &core_l3_ck, |
8ad8ff65 | 1807 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1808 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1809 | .recalc = &followparent_recalc, |
1810 | }; | |
1811 | ||
1812 | static struct clk sdma_fck = { | |
1813 | .name = "sdma_fck", | |
897dcded | 1814 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1815 | .parent = &core_l3_ck, |
d1b03f61 | 1816 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1817 | .recalc = &followparent_recalc, |
1818 | }; | |
1819 | ||
1820 | static struct clk sdma_ick = { | |
1821 | .name = "sdma_ick", | |
897dcded | 1822 | .ops = &clkops_null, /* RMK: missing? */ |
e32744b0 | 1823 | .parent = &l4_ck, |
d1b03f61 | 1824 | .clkdm_name = "core_l3_clkdm", |
e32744b0 | 1825 | .recalc = &followparent_recalc, |
046d6b28 TL |
1826 | }; |
1827 | ||
1828 | static struct clk vlynq_ick = { | |
1829 | .name = "vlynq_ick", | |
b36ee724 | 1830 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1831 | .parent = &core_l3_ck, |
d1b03f61 | 1832 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1833 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1834 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1835 | .recalc = &followparent_recalc, | |
1836 | }; | |
1837 | ||
1838 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | |
1839 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | |
1840 | { .div = 0 } | |
1841 | }; | |
1842 | ||
1843 | static const struct clksel_rate vlynq_fck_core_rates[] = { | |
1844 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | |
1845 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | |
1846 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | |
1847 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | |
1848 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | |
1849 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | |
1850 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | |
1851 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | |
1852 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | |
1853 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | |
1854 | { .div = 0 } | |
1855 | }; | |
1856 | ||
1857 | static const struct clksel vlynq_fck_clksel[] = { | |
1858 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | |
1859 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | |
1860 | { .parent = NULL } | |
046d6b28 TL |
1861 | }; |
1862 | ||
1863 | static struct clk vlynq_fck = { | |
1864 | .name = "vlynq_fck", | |
b36ee724 | 1865 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1866 | .parent = &func_96m_ck, |
8ad8ff65 | 1867 | .flags = DELAYED_APP, |
d1b03f61 | 1868 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1870 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | |
1871 | .init = &omap2_init_clksel_parent, | |
1872 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | |
1873 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | |
1874 | .clksel = vlynq_fck_clksel, | |
1875 | .recalc = &omap2_clksel_recalc, | |
1876 | .round_rate = &omap2_clksel_round_rate, | |
1877 | .set_rate = &omap2_clksel_set_rate | |
046d6b28 TL |
1878 | }; |
1879 | ||
1880 | static struct clk sdrc_ick = { | |
1881 | .name = "sdrc_ick", | |
b36ee724 | 1882 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1883 | .parent = &l4_ck, |
8ad8ff65 | 1884 | .flags = ENABLE_ON_INIT, |
d1b03f61 | 1885 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1886 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1887 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | |
1888 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1889 | }; |
1890 | ||
1891 | static struct clk des_ick = { | |
1892 | .name = "des_ick", | |
b36ee724 | 1893 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1894 | .parent = &l4_ck, |
d1b03f61 | 1895 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1896 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1897 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | |
1898 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1899 | }; |
1900 | ||
1901 | static struct clk sha_ick = { | |
1902 | .name = "sha_ick", | |
b36ee724 | 1903 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1904 | .parent = &l4_ck, |
d1b03f61 | 1905 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1906 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1907 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | |
1908 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1909 | }; |
1910 | ||
1911 | static struct clk rng_ick = { | |
1912 | .name = "rng_ick", | |
b36ee724 | 1913 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1914 | .parent = &l4_ck, |
d1b03f61 | 1915 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1916 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1917 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | |
1918 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1919 | }; |
1920 | ||
1921 | static struct clk aes_ick = { | |
1922 | .name = "aes_ick", | |
b36ee724 | 1923 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1924 | .parent = &l4_ck, |
d1b03f61 | 1925 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1926 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1927 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | |
1928 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1929 | }; |
1930 | ||
1931 | static struct clk pka_ick = { | |
1932 | .name = "pka_ick", | |
b36ee724 | 1933 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1934 | .parent = &l4_ck, |
d1b03f61 | 1935 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1936 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
1937 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | |
1938 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1939 | }; |
1940 | ||
1941 | static struct clk usb_fck = { | |
1942 | .name = "usb_fck", | |
b36ee724 | 1943 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1944 | .parent = &func_48m_ck, |
d1b03f61 | 1945 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1946 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1947 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | |
1948 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1949 | }; |
1950 | ||
1951 | static struct clk usbhs_ick = { | |
1952 | .name = "usbhs_ick", | |
b36ee724 | 1953 | .ops = &clkops_omap2_dflt_wait, |
fde0fd49 | 1954 | .parent = &core_l3_ck, |
d1b03f61 | 1955 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1956 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1957 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | |
1958 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1959 | }; |
1960 | ||
1961 | static struct clk mmchs1_ick = { | |
e32744b0 | 1962 | .name = "mmchs_ick", |
b36ee724 | 1963 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1964 | .parent = &l4_ck, |
d1b03f61 | 1965 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1966 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1967 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1968 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1969 | }; |
1970 | ||
1971 | static struct clk mmchs1_fck = { | |
e32744b0 | 1972 | .name = "mmchs_fck", |
b36ee724 | 1973 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 1974 | .parent = &func_96m_ck, |
d1b03f61 | 1975 | .clkdm_name = "core_l3_clkdm", |
e32744b0 PW |
1976 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1977 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1978 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1979 | }; |
1980 | ||
1981 | static struct clk mmchs2_ick = { | |
e32744b0 | 1982 | .name = "mmchs_ick", |
b36ee724 | 1983 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1984 | .id = 1, |
046d6b28 | 1985 | .parent = &l4_ck, |
d1b03f61 | 1986 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
1987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1988 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1989 | .recalc = &followparent_recalc, | |
046d6b28 TL |
1990 | }; |
1991 | ||
1992 | static struct clk mmchs2_fck = { | |
e32744b0 | 1993 | .name = "mmchs_fck", |
b36ee724 | 1994 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1995 | .id = 1, |
046d6b28 | 1996 | .parent = &func_96m_ck, |
e32744b0 PW |
1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1998 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1999 | .recalc = &followparent_recalc, | |
046d6b28 TL |
2000 | }; |
2001 | ||
2002 | static struct clk gpio5_ick = { | |
2003 | .name = "gpio5_ick", | |
b36ee724 | 2004 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 2005 | .parent = &l4_ck, |
d1b03f61 | 2006 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
2007 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2008 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
2009 | .recalc = &followparent_recalc, | |
046d6b28 TL |
2010 | }; |
2011 | ||
2012 | static struct clk gpio5_fck = { | |
2013 | .name = "gpio5_fck", | |
b36ee724 | 2014 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 2015 | .parent = &func_32k_ck, |
d1b03f61 | 2016 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
2017 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2018 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | |
2019 | .recalc = &followparent_recalc, | |
046d6b28 TL |
2020 | }; |
2021 | ||
2022 | static struct clk mdm_intc_ick = { | |
2023 | .name = "mdm_intc_ick", | |
b36ee724 | 2024 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 2025 | .parent = &l4_ck, |
d1b03f61 | 2026 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
2027 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2028 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | |
2029 | .recalc = &followparent_recalc, | |
046d6b28 TL |
2030 | }; |
2031 | ||
2032 | static struct clk mmchsdb1_fck = { | |
e32744b0 | 2033 | .name = "mmchsdb_fck", |
b36ee724 | 2034 | .ops = &clkops_omap2_dflt_wait, |
046d6b28 | 2035 | .parent = &func_32k_ck, |
d1b03f61 | 2036 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
2037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2038 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | |
2039 | .recalc = &followparent_recalc, | |
046d6b28 TL |
2040 | }; |
2041 | ||
2042 | static struct clk mmchsdb2_fck = { | |
e32744b0 | 2043 | .name = "mmchsdb_fck", |
b36ee724 | 2044 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 2045 | .id = 1, |
046d6b28 | 2046 | .parent = &func_32k_ck, |
d1b03f61 | 2047 | .clkdm_name = "core_l4_clkdm", |
e32744b0 PW |
2048 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2049 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | |
2050 | .recalc = &followparent_recalc, | |
046d6b28 | 2051 | }; |
e32744b0 | 2052 | |
046d6b28 TL |
2053 | /* |
2054 | * This clock is a composite clock which does entire set changes then | |
2055 | * forces a rebalance. It keys on the MPU speed, but it really could | |
2056 | * be any key speed part of a set in the rate table. | |
2057 | * | |
2058 | * to really change a set, you need memory table sets which get changed | |
2059 | * in sram, pre-notifiers & post notifiers, changing the top set, without | |
2060 | * having low level display recalc's won't work... this is why dpm notifiers | |
2061 | * work, isr's off, walk a list of clocks already _off_ and not messing with | |
2062 | * the bus. | |
2063 | * | |
2064 | * This clock should have no parent. It embodies the entire upper level | |
2065 | * active set. A parent will mess up some of the init also. | |
2066 | */ | |
2067 | static struct clk virt_prcm_set = { | |
2068 | .name = "virt_prcm_set", | |
897dcded | 2069 | .ops = &clkops_null, |
8ad8ff65 | 2070 | .flags = DELAYED_APP, |
046d6b28 | 2071 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
e32744b0 | 2072 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
046d6b28 TL |
2073 | .set_rate = &omap2_select_table_rate, |
2074 | .round_rate = &omap2_round_to_table_rate, | |
2075 | }; | |
e32744b0 | 2076 | |
d8a94458 PW |
2077 | |
2078 | /* | |
2079 | * clkdev integration | |
2080 | */ | |
2081 | ||
2082 | static struct omap_clk omap24xx_clks[] = { | |
2083 | /* external root sources */ | |
2084 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | |
2085 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), | |
2086 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | |
2087 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | |
2088 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | |
2089 | /* internal analog sources */ | |
2090 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | |
2091 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | |
2092 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | |
2093 | /* internal prcm root sources */ | |
2094 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | |
2095 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | |
2096 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | |
2097 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | |
2098 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | |
2099 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | |
2100 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | |
2101 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | |
2102 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | |
2103 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | |
2104 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | |
2105 | /* mpu domain clocks */ | |
2106 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | |
2107 | /* dsp domain clocks */ | |
2108 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | |
2109 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | |
2110 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | |
2111 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | |
2112 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | |
2113 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | |
2114 | /* GFX domain clocks */ | |
2115 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | |
2116 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | |
2117 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | |
2118 | /* Modem domain clocks */ | |
2119 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | |
2120 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | |
2121 | /* DSS domain clocks */ | |
2122 | CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), | |
2123 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | |
2124 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | |
2125 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | |
2126 | /* L3 domain clocks */ | |
2127 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | |
2128 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | |
2129 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | |
2130 | /* L4 domain clocks */ | |
2131 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | |
2132 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | |
2133 | /* virtual meta-group clock */ | |
2134 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | |
2135 | /* general l4 interface ck, multi-parent functional clk */ | |
2136 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | |
2137 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | |
2138 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | |
2139 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | |
2140 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | |
2141 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | |
2142 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | |
2143 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | |
2144 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | |
2145 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | |
2146 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | |
2147 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | |
2148 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | |
2149 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | |
2150 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | |
2151 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | |
2152 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | |
2153 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | |
2154 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | |
2155 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | |
2156 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | |
2157 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | |
2158 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | |
2159 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | |
2160 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | |
2161 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | |
2162 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | |
2163 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | |
2164 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | |
2165 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | |
2166 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | |
2167 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | |
2168 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | |
2169 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | |
2170 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | |
2171 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | |
2172 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | |
2173 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | |
2174 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | |
2175 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | |
2176 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | |
2177 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | |
2178 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | |
2179 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | |
2180 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | |
2181 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | |
2182 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | |
2183 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | |
2184 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | |
2185 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | |
2186 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | |
2187 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | |
2188 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | |
2189 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | |
2190 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | |
2191 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | |
2192 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | |
2193 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | |
2194 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | |
2195 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | |
2196 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | |
2197 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | |
2198 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | |
2199 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | |
2200 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | |
2201 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | |
2202 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | |
2203 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | |
2204 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | |
2205 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | |
2206 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | |
2207 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | |
2208 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | |
2209 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | |
2210 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | |
2211 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | |
2212 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | |
2213 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | |
2214 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | |
2215 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | |
2216 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | |
2217 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | |
2218 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | |
2219 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | |
2220 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | |
2221 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | |
2222 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | |
2223 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | |
2224 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | |
2225 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | |
2226 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | |
2227 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | |
2228 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | |
2229 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | |
2230 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | |
2231 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | |
2232 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | |
2233 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | |
2234 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | |
2235 | }; | |
2236 | ||
2237 | /* | |
2238 | * init code | |
2239 | */ | |
2240 | ||
e80a9729 | 2241 | int __init omap2xxx_clk_init(void) |
d8a94458 PW |
2242 | { |
2243 | const struct prcm_config *prcm; | |
2244 | struct omap_clk *c; | |
2245 | u32 clkrate; | |
2246 | u16 cpu_clkflg; | |
2247 | ||
2248 | if (cpu_is_omap242x()) { | |
2249 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | |
2250 | cpu_mask = RATE_IN_242X; | |
2251 | cpu_clkflg = CK_242X; | |
2252 | rate_table = omap2420_rate_table; | |
2253 | } else if (cpu_is_omap2430()) { | |
2254 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
2255 | cpu_mask = RATE_IN_243X; | |
2256 | cpu_clkflg = CK_243X; | |
2257 | rate_table = omap2430_rate_table; | |
2258 | } | |
2259 | ||
2260 | clk_init(&omap2_clk_functions); | |
2261 | ||
2262 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | |
2263 | clk_preinit(c->lk.clk); | |
2264 | ||
2265 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | |
2266 | propagate_rate(&osc_ck); | |
44da0a51 | 2267 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
d8a94458 PW |
2268 | propagate_rate(&sys_ck); |
2269 | ||
2270 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | |
2271 | if (c->cpu & cpu_clkflg) { | |
2272 | clkdev_add(&c->lk); | |
2273 | clk_register(c->lk.clk); | |
2274 | omap2_init_clk_clkdm(c->lk.clk); | |
2275 | } | |
2276 | ||
2277 | /* Check the MPU rate set by bootloader */ | |
2278 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | |
2279 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
2280 | if (!(prcm->flags & cpu_mask)) | |
2281 | continue; | |
2282 | if (prcm->xtal_speed != sys_ck.rate) | |
2283 | continue; | |
2284 | if (prcm->dpll_speed <= clkrate) | |
2285 | break; | |
2286 | } | |
2287 | curr_prcm_set = prcm; | |
2288 | ||
2289 | recalculate_root_clocks(); | |
2290 | ||
2291 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | |
2292 | "%ld.%01ld/%ld/%ld MHz\n", | |
2293 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
2294 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
2295 | ||
2296 | /* | |
2297 | * Only enable those clocks we will need, let the drivers | |
2298 | * enable other clocks as necessary | |
2299 | */ | |
2300 | clk_enable_init_clocks(); | |
2301 | ||
2302 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | |
2303 | vclk = clk_get(NULL, "virt_prcm_set"); | |
2304 | sclk = clk_get(NULL, "sys_ck"); | |
2305 | dclk = clk_get(NULL, "dpll_ck"); | |
2306 | ||
2307 | return 0; | |
2308 | } | |
6b8858a9 | 2309 |