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[ARM] 5590/1: Add basic support for ST Nomadik 8815 SoC and evaluation board
[deliverable/linux.git] / arch / arm / mach-omap2 / clock34xx.c
CommitLineData
02e19a96
PW		 1/*
2 * OMAP3-specific clock framework functions
3 *
542313cc
PW		 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
02e19a96
PW		 6 *
7 * Written by Paul Walmsley
542313cc 8 * Testing and integration fixes by Jouni Högander
02e19a96
PW		 9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/device.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
542313cc 27#include <linux/limits.h>
fbd3bdb2 28#include <linux/bitops.h>
02e19a96 29
a09e64fb
RK		 30#include <mach/clock.h>
31#include <mach/sram.h>
02e19a96 32#include <asm/div64.h>
44dc9d02 33#include <asm/clkdev.h>
02e19a96 34
f8de9b2c 35#include <mach/sdrc.h>
02e19a96 36#include "clock.h"
02e19a96
PW		 37#include "prm.h"
38#include "prm-regbits-34xx.h"
39#include "cm.h"
40#include "cm-regbits-34xx.h"
41
548d8495
RK		 42static const struct clkops clkops_noncore_dpll_ops;
43
44#include "clock34xx.h"
45
44dc9d02
RK		 46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
44dc9d02
RK		 96 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
98 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
99 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
100 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
101 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
102 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
103 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
104 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
105 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
106 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
107 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
108 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
109 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
110 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
111 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
44dc9d02
RK		 112 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
113 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
114 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
115 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
116 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
117 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
118 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
119 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
120 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
121 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
122 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
123 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
124 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
125 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
126 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
127 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
128 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
129 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
130 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
131 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
8111b221
KH		 132 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
133 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
134 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
44dc9d02
RK		 135 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
136 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
137 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
138 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
139 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
140 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
6f7607cc
RK		 141 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
142 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
44dc9d02 143 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
6f7607cc 144 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
1d14de08
RK		 145 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
146 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
147 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
b820ce4e
RK		 148 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
149 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
44dc9d02 150 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
1b5715ec
RK		 151 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
152 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
153 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
154 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
44dc9d02
RK		 155 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
156 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
157 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
158 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
cc51c9d4 159 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
44dc9d02
RK		 160 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
161 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
162 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
4ea60b0c 163 CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
44dc9d02
RK		 164 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
165 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
166 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
167 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
168 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
169 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
6f7607cc 170 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
44dc9d02
RK		 171 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
172 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
173 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
174 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
6f7607cc
RK		 175 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
176 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
44dc9d02 177 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
cc51c9d4 178 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
1b5715ec
RK		 179 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
180 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
181 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
182 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
1d14de08
RK		 183 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
184 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
185 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
44dc9d02
RK		 186 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
187 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
188 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
189 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
b820ce4e
RK		 190 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
191 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
44dc9d02
RK		 192 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
193 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
194 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
195 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
196 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
197 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
198 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
199 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
eeec7c8d 200 CLK("omap_rng", "ick", &rng_ick, CK_343X),
44dc9d02
RK		 201 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
202 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
005187ee
TL		 203 CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
204 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
205 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
206 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
207 CLK("omapfb", "ick", &dss_ick, CK_343X),
44dc9d02
RK		 208 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
209 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
6c8fe0b9 210 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
44dc9d02
RK		 211 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
212 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
213 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
44dc9d02
RK		 214 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
215 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
216 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
217 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
39a80c7f 218 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
44dc9d02
RK		 219 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
220 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
39a80c7f 221 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
44dc9d02
RK		 222 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
223 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
224 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
225 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
226 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
227 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
228 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
229 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
230 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
231 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
232 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
233 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
234 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
235 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
236 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
237 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
238 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
239 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
240 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
241 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
242 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
243 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
244 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
245 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
246 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
247 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
248 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
249 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
250 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
251 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
252 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
253 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
254 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
255 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
256 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
257 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
258 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
259 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
260 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
b820ce4e
RK		 261 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
262 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
263 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
264 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
265 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
266 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
44dc9d02
RK		 267 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
268 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
269 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
270 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
271 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
272 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
273 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
274 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
275 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
276 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
277 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
278 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
279};
280
542313cc
PW		 281/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
282#define DPLL_AUTOIDLE_DISABLE 0x0
283#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
284
285#define MAX_DPLL_WAIT_TRIES 1000000
02e19a96 286
4519c2bf
PW		 287#define MIN_SDRC_DLL_LOCK_FREQ 83000000
288
c9812d04
PW		 289#define CYCLES_PER_MHZ 1000000
290
291/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
292#define SDRC_MPURATE_SCALE 8
293
294/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
295#define SDRC_MPURATE_BASE_SHIFT 9
296
297/*
298 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
299 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
300 */
301#define SDRC_MPURATE_LOOPS 96
302
02e19a96
PW		 303/**
304 * omap3_dpll_recalc - recalculate DPLL rate
305 * @clk: DPLL struct clk
306 *
307 * Recalculate and propagate the DPLL rate.
308 */
8b9dbc16 309static unsigned long omap3_dpll_recalc(struct clk *clk)
02e19a96 310{
8b9dbc16 311 return omap2_get_dpll_rate(clk);
02e19a96
PW		 312}
313
542313cc
PW		 314/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
315static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
316{
317 const struct dpll_data *dd;
ad67ef68 318 u32 v;
542313cc
PW		 319
320 dd = clk->dpll_data;
321
ad67ef68
PW		 322 v = __raw_readl(dd->control_reg);
323 v &= ~dd->enable_mask;
324 v |= clken_bits << __ffs(dd->enable_mask);
325 __raw_writel(v, dd->control_reg);
542313cc
PW		 326}
327
328/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
329static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
330{
331 const struct dpll_data *dd;
332 int i = 0;
333 int ret = -EINVAL;
542313cc
PW		 334
335 dd = clk->dpll_data;
336
c1bd7aaf 337 state <<= __ffs(dd->idlest_mask);
542313cc 338
c1bd7aaf 339 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
542313cc
PW		 340 i < MAX_DPLL_WAIT_TRIES) {
341 i++;
342 udelay(1);
343 }
344
345 if (i == MAX_DPLL_WAIT_TRIES) {
346 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
347 clk->name, (state) ? "locked" : "bypassed");
348 } else {
349 pr_debug("clock: %s transition to '%s' in %d loops\n",
350 clk->name, (state) ? "locked" : "bypassed", i);
351
352 ret = 0;
353 }
354
355 return ret;
356}
357
16c90f02
PW		 358/* From 3430 TRM ES2 4.7.6.2 */
359static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
360{
361 unsigned long fint;
362 u16 f = 0;
363
c0bf3132 364 fint = clk->dpll_data->clk_ref->rate / (n + 1);
16c90f02
PW		 365
366 pr_debug("clock: fint is %lu\n", fint);
367
368 if (fint >= 750000 && fint <= 1000000)
369 f = 0x3;
370 else if (fint > 1000000 && fint <= 1250000)
371 f = 0x4;
372 else if (fint > 1250000 && fint <= 1500000)
373 f = 0x5;
374 else if (fint > 1500000 && fint <= 1750000)
375 f = 0x6;
376 else if (fint > 1750000 && fint <= 2100000)
377 f = 0x7;
378 else if (fint > 7500000 && fint <= 10000000)
379 f = 0xB;
380 else if (fint > 10000000 && fint <= 12500000)
381 f = 0xC;
382 else if (fint > 12500000 && fint <= 15000000)
383 f = 0xD;
384 else if (fint > 15000000 && fint <= 17500000)
385 f = 0xE;
386 else if (fint > 17500000 && fint <= 21000000)
387 f = 0xF;
388 else
389 pr_debug("clock: unknown freqsel setting for %d\n", n);
390
391 return f;
392}
393
542313cc
PW		 394/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
395
396/*
397 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
398 * @clk: pointer to a DPLL struct clk
399 *
400 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
401 * readiness before returning. Will save and restore the DPLL's
402 * autoidle state across the enable, per the CDP code. If the DPLL
403 * locked successfully, return 0; if the DPLL did not lock in the time
404 * allotted, or DPLL3 was passed in, return -EINVAL.
405 */
406static int _omap3_noncore_dpll_lock(struct clk *clk)
407{
408 u8 ai;
409 int r;
410
411 if (clk == &dpll3_ck)
412 return -EINVAL;
413
414 pr_debug("clock: locking DPLL %s\n", clk->name);
415
416 ai = omap3_dpll_autoidle_read(clk);
417
416db864
PW		 418 omap3_dpll_deny_idle(clk);
419
542313cc
PW		 420 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
421
416db864
PW		 422 r = _omap3_wait_dpll_status(clk, 1);
423
424 if (ai)
542313cc 425 omap3_dpll_allow_idle(clk);
542313cc
PW		 426
427 return r;
428}
429
430/*
c0bf3132 431 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
542313cc
PW		 432 * @clk: pointer to a DPLL struct clk
433 *
434 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
435 * bypass mode, the DPLL's rate is set equal to its parent clock's
436 * rate. Waits for the DPLL to report readiness before returning.
437 * Will save and restore the DPLL's autoidle state across the enable,
438 * per the CDP code. If the DPLL entered bypass mode successfully,
439 * return 0; if the DPLL did not enter bypass in the time allotted, or
440 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
441 * return -EINVAL.
442 */
443static int _omap3_noncore_dpll_bypass(struct clk *clk)
444{
445 int r;
446 u8 ai;
447
448 if (clk == &dpll3_ck)
449 return -EINVAL;
450
451 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
452 return -EINVAL;
453
454 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
455 clk->name);
456
457 ai = omap3_dpll_autoidle_read(clk);
458
459 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
460
461 r = _omap3_wait_dpll_status(clk, 0);
462
463 if (ai)
464 omap3_dpll_allow_idle(clk);
465 else
466 omap3_dpll_deny_idle(clk);
467
468 return r;
469}
470
471/*
472 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
473 * @clk: pointer to a DPLL struct clk
474 *
475 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
476 * restore the DPLL's autoidle state across the stop, per the CDP
477 * code. If DPLL3 was passed in, or the DPLL does not support
478 * low-power stop, return -EINVAL; otherwise, return 0.
479 */
480static int _omap3_noncore_dpll_stop(struct clk *clk)
481{
482 u8 ai;
483
484 if (clk == &dpll3_ck)
485 return -EINVAL;
486
487 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
488 return -EINVAL;
489
490 pr_debug("clock: stopping DPLL %s\n", clk->name);
491
492 ai = omap3_dpll_autoidle_read(clk);
493
494 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
495
496 if (ai)
497 omap3_dpll_allow_idle(clk);
498 else
499 omap3_dpll_deny_idle(clk);
500
501 return 0;
502}
503
504/**
505 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
506 * @clk: pointer to a DPLL struct clk
507 *
508 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
509 * The choice of modes depends on the DPLL's programmed rate: if it is
510 * the same as the DPLL's parent clock, it will enter bypass;
511 * otherwise, it will enter lock. This code will wait for the DPLL to
512 * indicate readiness before returning, unless the DPLL takes too long
513 * to enter the target state. Intended to be used as the struct clk's
514 * enable function. If DPLL3 was passed in, or the DPLL does not
515 * support low-power stop, or if the DPLL took too long to enter
516 * bypass or lock, return -EINVAL; otherwise, return 0.
517 */
518static int omap3_noncore_dpll_enable(struct clk *clk)
519{
520 int r;
c0bf3132 521 struct dpll_data *dd;
542313cc
PW		 522
523 if (clk == &dpll3_ck)
524 return -EINVAL;
525
c0bf3132
RK		 526 dd = clk->dpll_data;
527 if (!dd)
528 return -EINVAL;
529
530 if (clk->rate == dd->clk_bypass->rate) {
531 WARN_ON(clk->parent != dd->clk_bypass);
542313cc 532 r = _omap3_noncore_dpll_bypass(clk);
c0bf3132
RK		 533 } else {
534 WARN_ON(clk->parent != dd->clk_ref);
542313cc 535 r = _omap3_noncore_dpll_lock(clk);
c0bf3132
RK		 536 }
537 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
538 if (!r)
539 clk->rate = omap2_get_dpll_rate(clk);
542313cc
PW		 540
541 return r;
542}
543
544/**
545 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
546 * @clk: pointer to a DPLL struct clk
547 *
548 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
549 * The choice of modes depends on the DPLL's programmed rate: if it is
550 * the same as the DPLL's parent clock, it will enter bypass;
551 * otherwise, it will enter lock. This code will wait for the DPLL to
552 * indicate readiness before returning, unless the DPLL takes too long
553 * to enter the target state. Intended to be used as the struct clk's
554 * enable function. If DPLL3 was passed in, or the DPLL does not
555 * support low-power stop, or if the DPLL took too long to enter
556 * bypass or lock, return -EINVAL; otherwise, return 0.
557 */
558static void omap3_noncore_dpll_disable(struct clk *clk)
559{
560 if (clk == &dpll3_ck)
561 return;
562
563 _omap3_noncore_dpll_stop(clk);
564}
565
16c90f02
PW		 566
567/* Non-CORE DPLL rate set code */
568
569/*
570 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
571 * @clk: struct clk * of DPLL to set
572 * @m: DPLL multiplier to set
573 * @n: DPLL divider to set
574 * @freqsel: FREQSEL value to set
575 *
576 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
577 * lock.. Returns -EINVAL upon error, or 0 upon success.
578 */
579static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
580{
581 struct dpll_data *dd = clk->dpll_data;
582 u32 v;
583
584 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
585 _omap3_noncore_dpll_bypass(clk);
586
f0587b63
PW		 587 /* Set jitter correction */
588 v = __raw_readl(dd->control_reg);
589 v &= ~dd->freqsel_mask;
590 v |= freqsel << __ffs(dd->freqsel_mask);
591 __raw_writel(v, dd->control_reg);
592
593 /* Set DPLL multiplier, divider */
16c90f02
PW		 594 v = __raw_readl(dd->mult_div1_reg);
595 v &= ~(dd->mult_mask | dd->div1_mask);
16c90f02 596 v |= m << __ffs(dd->mult_mask);
f0587b63 597 v |= (n - 1) << __ffs(dd->div1_mask);
16c90f02
PW		 598 __raw_writel(v, dd->mult_div1_reg);
599
600 /* We let the clock framework set the other output dividers later */
601
602 /* REVISIT: Set ramp-up delay? */
603
604 _omap3_noncore_dpll_lock(clk);
605
606 return 0;
607}
608
609/**
610 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
611 * @clk: struct clk * of DPLL to set
612 * @rate: rounded target rate
613 *
c0bf3132
RK		 614 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
615 * low-power bypass, and the target rate is the bypass source clock
616 * rate, then configure the DPLL for bypass. Otherwise, round the
617 * target rate if it hasn't been done already, then program and lock
618 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
16c90f02
PW		 619 */
620static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
621{
c0bf3132 622 struct clk *new_parent = NULL;
16c90f02
PW		 623 u16 freqsel;
624 struct dpll_data *dd;
c0bf3132 625 int ret;
16c90f02
PW		 626
627 if (!clk || !rate)
628 return -EINVAL;
629
630 dd = clk->dpll_data;
631 if (!dd)
632 return -EINVAL;
633
634 if (rate == omap2_get_dpll_rate(clk))
635 return 0;
636
c0bf3132
RK		 637 /*
638 * Ensure both the bypass and ref clocks are enabled prior to
639 * doing anything; we need the bypass clock running to reprogram
640 * the DPLL.
641 */
642 omap2_clk_enable(dd->clk_bypass);
643 omap2_clk_enable(dd->clk_ref);
16c90f02 644
c0bf3132
RK		 645 if (dd->clk_bypass->rate == rate &&
646 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
647 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
648
649 ret = _omap3_noncore_dpll_bypass(clk);
650 if (!ret)
651 new_parent = dd->clk_bypass;
652 } else {
653 if (dd->last_rounded_rate != rate)
654 omap2_dpll_round_rate(clk, rate);
16c90f02 655
c0bf3132
RK		 656 if (dd->last_rounded_rate == 0)
657 return -EINVAL;
16c90f02 658
c0bf3132
RK		 659 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
660 if (!freqsel)
661 WARN_ON(1);
662
663 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
664 clk->name, rate);
665
666 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
667 dd->last_rounded_n, freqsel);
668 if (!ret)
669 new_parent = dd->clk_ref;
670 }
671 if (!ret) {
672 /*
673 * Switch the parent clock in the heirarchy, and make sure
674 * that the new parent's usecount is correct. Note: we
675 * enable the new parent before disabling the old to avoid
676 * any unnecessary hardware disable->enable transitions.
677 */
678 if (clk->usecount) {
679 omap2_clk_enable(new_parent);
680 omap2_clk_disable(clk->parent);
681 }
682 clk_reparent(clk, new_parent);
683 clk->rate = rate;
684 }
685 omap2_clk_disable(dd->clk_ref);
686 omap2_clk_disable(dd->clk_bypass);
16c90f02 687
16c90f02
PW		 688 return 0;
689}
690
691static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
692{
693 /*
694 * According to the 12-5 CDP code from TI, "Limitation 2.5"
695 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
696 * on DPLL4.
697 */
698 if (omap_rev() == OMAP3430_REV_ES1_0) {
699 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
700 "silicon 'Limitation 2.5' on 3430ES1.\n");
701 return -EINVAL;
702 }
703 return omap3_noncore_dpll_set_rate(clk, rate);
704}
705
0eafd472
PW		 706
707/*
708 * CORE DPLL (DPLL3) rate programming functions
709 *
710 * These call into SRAM code to do the actual CM writes, since the SDRAM
711 * is clocked from DPLL3.
712 */
713
714/**
715 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
716 * @clk: struct clk * of DPLL to set
717 * @rate: rounded target rate
718 *
719 * Program the DPLL M2 divider with the rounded target rate. Returns
720 * -EINVAL upon error, or 0 upon success.
721 */
722static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
723{
724 u32 new_div = 0;
4519c2bf 725 u32 unlock_dll = 0;
c9812d04
PW		 726 u32 c;
727 unsigned long validrate, sdrcrate, mpurate;
0eafd472
PW		 728 struct omap_sdrc_params *sp;
729
730 if (!clk || !rate)
731 return -EINVAL;
732
733 if (clk != &dpll3_m2_ck)
734 return -EINVAL;
735
0eafd472
PW		 736 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
737 if (validrate != rate)
738 return -EINVAL;
739
740 sdrcrate = sdrc_ick.rate;
741 if (rate > clk->rate)
3afec633 742 sdrcrate <<= ((rate / clk->rate) >> 1);
0eafd472 743 else
3afec633 744 sdrcrate >>= ((clk->rate / rate) >> 1);
0eafd472
PW		 745
746 sp = omap2_sdrc_get_params(sdrcrate);
747 if (!sp)
748 return -EINVAL;
749
4519c2bf
PW		 750 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
751 pr_debug("clock: will unlock SDRC DLL\n");
752 unlock_dll = 1;
753 }
754
c9812d04
PW		 755 /*
756 * XXX This only needs to be done when the CPU frequency changes
757 */
758 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
759 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
760 c += 1; /* for safety */
761 c *= SDRC_MPURATE_LOOPS;
762 c >>= SDRC_MPURATE_SCALE;
763 if (c == 0)
764 c = 1;
765
b7aee4bf
PW		 766 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
767 validrate);
768 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
769 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
0eafd472 770
0eafd472 771 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
d0ba3922 772 sp->actim_ctrlb, new_div, unlock_dll, c,
3afec633 773 sp->mr, rate > clk->rate);
0eafd472 774
0eafd472
PW		 775 return 0;
776}
777
778
548d8495
RK		 779static const struct clkops clkops_noncore_dpll_ops = {
780 .enable = &omap3_noncore_dpll_enable,
781 .disable = &omap3_noncore_dpll_disable,
782};
783
16c90f02
PW		 784/* DPLL autoidle read/set code */
785
786
542313cc
PW		 787/**
788 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
789 * @clk: struct clk * of the DPLL to read
790 *
791 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
792 * -EINVAL if passed a null pointer or if the struct clk does not
793 * appear to refer to a DPLL.
794 */
795static u32 omap3_dpll_autoidle_read(struct clk *clk)
796{
797 const struct dpll_data *dd;
798 u32 v;
799
800 if (!clk || !clk->dpll_data)
801 return -EINVAL;
802
803 dd = clk->dpll_data;
804
ad67ef68 805 v = __raw_readl(dd->autoidle_reg);
542313cc
PW		 806 v &= dd->autoidle_mask;
807 v >>= __ffs(dd->autoidle_mask);
808
809 return v;
810}
811
812/**
813 * omap3_dpll_allow_idle - enable DPLL autoidle bits
814 * @clk: struct clk * of the DPLL to operate on
815 *
816 * Enable DPLL automatic idle control. This automatic idle mode
817 * switching takes effect only when the DPLL is locked, at least on
818 * OMAP3430. The DPLL will enter low-power stop when its downstream
819 * clocks are gated. No return value.
820 */
821static void omap3_dpll_allow_idle(struct clk *clk)
822{
823 const struct dpll_data *dd;
ad67ef68 824 u32 v;
542313cc
PW		 825
826 if (!clk || !clk->dpll_data)
827 return;
828
829 dd = clk->dpll_data;
830
831 /*
832 * REVISIT: CORE DPLL can optionally enter low-power bypass
833 * by writing 0x5 instead of 0x1. Add some mechanism to
834 * optionally enter this mode.
835 */
ad67ef68
PW		 836 v = __raw_readl(dd->autoidle_reg);
837 v &= ~dd->autoidle_mask;
838 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
839 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 840}
841
842/**
843 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
844 * @clk: struct clk * of the DPLL to operate on
845 *
846 * Disable DPLL automatic idle control. No return value.
847 */
848static void omap3_dpll_deny_idle(struct clk *clk)
849{
850 const struct dpll_data *dd;
ad67ef68 851 u32 v;
542313cc
PW		 852
853 if (!clk || !clk->dpll_data)
854 return;
855
856 dd = clk->dpll_data;
857
ad67ef68
PW		 858 v = __raw_readl(dd->autoidle_reg);
859 v &= ~dd->autoidle_mask;
860 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
861 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 862}
863
864/* Clock control for DPLL outputs */
865
02e19a96
PW		 866/**
867 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
868 * @clk: DPLL output struct clk
869 *
870 * Using parent clock DPLL data, look up DPLL state. If locked, set our
871 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
872 */
8b9dbc16 873static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
02e19a96
PW		 874{
875 const struct dpll_data *dd;
8b9dbc16 876 unsigned long rate;
02e19a96
PW		 877 u32 v;
878 struct clk *pclk;
879
880 /* Walk up the parents of clk, looking for a DPLL */
881 pclk = clk->parent;
882 while (pclk && !pclk->dpll_data)
883 pclk = pclk->parent;
884
885 /* clk does not have a DPLL as a parent? */
886 WARN_ON(!pclk);
887
888 dd = pclk->dpll_data;
889
c0bf3132 890 WARN_ON(!dd->enable_mask);
02e19a96
PW		 891
892 v = __raw_readl(dd->control_reg) & dd->enable_mask;
893 v >>= __ffs(dd->enable_mask);
c0bf3132 894 if (v != OMAP3XXX_EN_DPLL_LOCKED)
8b9dbc16 895 rate = clk->parent->rate;
02e19a96 896 else
8b9dbc16
RK		 897 rate = clk->parent->rate * 2;
898 return rate;
02e19a96
PW		 899}
900
542313cc
PW		 901/* Common clock code */
902
02e19a96
PW		 903/*
904 * As it is structured now, this will prevent an OMAP2/3 multiboot
905 * kernel from compiling. This will need further attention.
906 */
907#if defined(CONFIG_ARCH_OMAP3)
908
909static struct clk_functions omap2_clk_functions = {
910 .clk_enable = omap2_clk_enable,
911 .clk_disable = omap2_clk_disable,
912 .clk_round_rate = omap2_clk_round_rate,
913 .clk_set_rate = omap2_clk_set_rate,
914 .clk_set_parent = omap2_clk_set_parent,
915 .clk_disable_unused = omap2_clk_disable_unused,
916};
917
918/*
919 * Set clocks for bypass mode for reboot to work.
920 */
921void omap2_clk_prepare_for_reboot(void)
922{
923 /* REVISIT: Not ready for 343x */
924#if 0
925 u32 rate;
926
927 if (vclk == NULL || sclk == NULL)
928 return;
929
930 rate = clk_get_rate(sclk);
931 clk_set_rate(vclk, rate);
932#endif
933}
934
935/* REVISIT: Move this init stuff out into clock.c */
936
937/*
938 * Switch the MPU rate if specified on cmdline.
939 * We cannot do this early until cmdline is parsed.
940 */
941static int __init omap2_clk_arch_init(void)
942{
943 if (!mpurate)
944 return -EINVAL;
945
946 /* REVISIT: not yet ready for 343x */
947#if 0
7b0f89d7 948 if (clk_set_rate(&virt_prcm_set, mpurate))
02e19a96
PW		 949 printk(KERN_ERR "Could not find matching MPU rate\n");
950#endif
951
952 recalculate_root_clocks();
953
954 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
955 "%ld.%01ld/%ld/%ld MHz\n",
956 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
957 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
958
959 return 0;
960}
961arch_initcall(omap2_clk_arch_init);
962
963int __init omap2_clk_init(void)
964{
965 /* struct prcm_config *prcm; */
44dc9d02 966 struct omap_clk *c;
02e19a96
PW		 967 /* u32 clkrate; */
968 u32 cpu_clkflg;
969
02e19a96
PW		 970 if (cpu_is_omap34xx()) {
971 cpu_mask = RATE_IN_343X;
44dc9d02 972 cpu_clkflg = CK_343X;
02e19a96
PW		 973
974 /*
975 * Update this if there are further clock changes between ES2
976 * and production parts
977 */
84a34344 978 if (omap_rev() == OMAP3430_REV_ES1_0) {
02e19a96 979 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
44dc9d02 980 cpu_clkflg |= CK_3430ES1;
02e19a96
PW		 981 } else {
982 cpu_mask |= RATE_IN_3430ES2;
44dc9d02 983 cpu_clkflg |= CK_3430ES2;
02e19a96
PW		 984 }
985 }
986
987 clk_init(&omap2_clk_functions);
988
3f0a820c 989 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
79716870 990 clk_preinit(c->lk.clk);
3f0a820c 991
44dc9d02
RK		 992 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
993 if (c->cpu & cpu_clkflg) {
994 clkdev_add(&c->lk);
995 clk_register(c->lk.clk);
996 omap2_init_clk_clkdm(c->lk.clk);
333943ba 997 }
02e19a96
PW		 998
999 /* REVISIT: Not yet ready for OMAP3 */
1000#if 0
1001 /* Check the MPU rate set by bootloader */
1002 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1003 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1004 if (!(prcm->flags & cpu_mask))
1005 continue;
1006 if (prcm->xtal_speed != sys_ck.rate)
1007 continue;
1008 if (prcm->dpll_speed <= clkrate)
1009 break;
1010 }
1011 curr_prcm_set = prcm;
1012#endif
1013
1014 recalculate_root_clocks();
1015
3760d31f 1016 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
02e19a96
PW		 1017 "%ld.%01ld/%ld/%ld MHz\n",
1018 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3760d31f 1019 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
02e19a96
PW		 1020
1021 /*
1022 * Only enable those clocks we will need, let the drivers
1023 * enable other clocks as necessary
1024 */
1025 clk_enable_init_clocks();
1026
1027 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1028 /* REVISIT: not yet ready for 343x */
1029#if 0
1030 vclk = clk_get(NULL, "virt_prcm_set");
1031 sclk = clk_get(NULL, "sys_ck");
1032#endif
1033 return 0;
1034}
1035
1036#endif
Linux kernel - Deliverables
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