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OMAP3 clock: remove superfluous calls to omap2_init_clk_clkdm
[deliverable/linux.git] / arch / arm / mach-omap2 / clock34xx.c
CommitLineData
02e19a96
PW		 1/*
2 * OMAP3-specific clock framework functions
3 *
542313cc 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
3c82e229 5 * Copyright (C) 2007-2009 Nokia Corporation
02e19a96
PW		 6 *
7 * Written by Paul Walmsley
542313cc 8 * Testing and integration fixes by Jouni Högander
02e19a96
PW		 9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/device.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
542313cc 27#include <linux/limits.h>
fbd3bdb2 28#include <linux/bitops.h>
02e19a96 29
11b66383 30#include <mach/cpu.h>
a09e64fb
RK		 31#include <mach/clock.h>
32#include <mach/sram.h>
02e19a96 33#include <asm/div64.h>
44dc9d02 34#include <asm/clkdev.h>
02e19a96 35
f8de9b2c 36#include <mach/sdrc.h>
02e19a96 37#include "clock.h"
02e19a96
PW		 38#include "prm.h"
39#include "prm-regbits-34xx.h"
40#include "cm.h"
41#include "cm-regbits-34xx.h"
42
548d8495
RK		 43static const struct clkops clkops_noncore_dpll_ops;
44
3c82e229
PW		 45static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
46 void __iomem **idlest_reg,
47 u8 *idlest_bit);
48static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
49 void __iomem **idlest_reg,
50 u8 *idlest_bit);
51static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
52 void __iomem **idlest_reg,
53 u8 *idlest_bit);
54
55static const struct clkops clkops_omap3430es2_ssi_wait = {
56 .enable = omap2_dflt_clk_enable,
57 .disable = omap2_dflt_clk_disable,
58 .find_idlest = omap3430es2_clk_ssi_find_idlest,
59 .find_companion = omap2_clk_dflt_find_companion,
60};
61
62static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
63 .enable = omap2_dflt_clk_enable,
64 .disable = omap2_dflt_clk_disable,
65 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
66 .find_companion = omap2_clk_dflt_find_companion,
67};
68
69static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
70 .enable = omap2_dflt_clk_enable,
71 .disable = omap2_dflt_clk_disable,
72 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
73 .find_companion = omap2_clk_dflt_find_companion,
74};
75
548d8495
RK		 76#include "clock34xx.h"
77
44dc9d02
RK		 78struct omap_clk {
79 u32 cpu;
80 struct clk_lookup lk;
81};
82
83#define CLK(dev, con, ck, cp) \
84 { \
85 .cpu = cp, \
86 .lk = { \
87 .dev_id = dev, \
88 .con_id = con, \
89 .clk = ck, \
90 }, \
91 }
92
93#define CK_343X (1 << 0)
94#define CK_3430ES1 (1 << 1)
95#define CK_3430ES2 (1 << 2)
96
97static struct omap_clk omap34xx_clks[] = {
98 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
99 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
100 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
101 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
102 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
103 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
104 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
105 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
106 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
107 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
108 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
109 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
110 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
111 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
112 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
113 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
114 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
115 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
116 CLK(NULL, "core_ck", &core_ck, CK_343X),
117 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
118 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
119 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
120 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
121 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
122 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
123 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
124 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
125 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
126 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
127 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
44dc9d02
RK		 128 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
129 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
130 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
131 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
132 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
133 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
134 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
135 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
136 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
137 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
138 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
139 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
140 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
141 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
142 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
143 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
44dc9d02
RK		 144 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
145 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
146 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
147 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
148 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
149 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
150 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
151 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
152 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
153 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
154 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
155 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
156 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
157 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
158 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
159 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
160 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
161 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
162 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
163 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
8111b221
KH		 164 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
165 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
166 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
44dc9d02
RK		 167 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
168 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
169 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
170 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
171 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
172 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
6f7607cc
RK		 173 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
174 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
44dc9d02 175 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
6f7607cc 176 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
1d14de08
RK		 177 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
178 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
179 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
b820ce4e
RK		 180 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
181 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
44dc9d02 182 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
1b5715ec
RK		 183 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
184 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
185 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
186 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
44dc9d02
RK		 187 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
188 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
189 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
190 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
cc51c9d4 191 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
3c82e229
PW		 192 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
193 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
194 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
195 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
44dc9d02 196 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
3c82e229
PW		 197 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
198 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 199 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
200 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
201 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
202 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
203 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
204 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
6f7607cc 205 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
44dc9d02
RK		 206 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
207 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
208 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
209 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
6f7607cc
RK		 210 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
211 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
44dc9d02 212 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
cc51c9d4 213 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
1b5715ec
RK		 214 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
215 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
216 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
217 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
1d14de08
RK		 218 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
219 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
220 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
44dc9d02
RK		 221 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
222 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
223 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
224 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
b820ce4e
RK		 225 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
226 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
44dc9d02
RK		 227 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
228 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
229 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
230 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3c82e229
PW		 231 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
232 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 233 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
234 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
235 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
eeec7c8d 236 CLK("omap_rng", "ick", &rng_ick, CK_343X),
44dc9d02
RK		 237 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
238 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3c82e229
PW		 239 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
240 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
005187ee
TL		 241 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
242 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
243 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
3c82e229
PW		 244 CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
245 CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 246 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
247 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
6c8fe0b9 248 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
44dc9d02
RK		 249 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
250 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
251 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
44dc9d02
RK		 252 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
253 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
254 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
255 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
39a80c7f 256 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
44dc9d02
RK		 257 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
258 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
39a80c7f 259 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
44dc9d02
RK		 260 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
261 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
262 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
263 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
264 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
265 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
266 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
267 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
268 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
269 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
270 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
271 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
272 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
273 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
274 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
275 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
276 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
277 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
278 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
279 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
280 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
281 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
282 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
283 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
284 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
285 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
286 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
287 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
288 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
289 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
290 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
291 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
292 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
293 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
294 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
295 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
296 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
297 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
298 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
b820ce4e
RK		 299 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
300 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
301 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
302 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
303 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
304 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
44dc9d02
RK		 305 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
306 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
307 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
308 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
309 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
310 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
311 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
312 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
313 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
314 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
315 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
316 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
317};
318
542313cc
PW		 319/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
320#define DPLL_AUTOIDLE_DISABLE 0x0
321#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
322
323#define MAX_DPLL_WAIT_TRIES 1000000
02e19a96 324
4519c2bf
PW		 325#define MIN_SDRC_DLL_LOCK_FREQ 83000000
326
c9812d04
PW		 327#define CYCLES_PER_MHZ 1000000
328
329/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
330#define SDRC_MPURATE_SCALE 8
331
332/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
333#define SDRC_MPURATE_BASE_SHIFT 9
334
335/*
336 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
337 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
338 */
339#define SDRC_MPURATE_LOOPS 96
340
3c82e229
PW		 341/**
342 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
343 * @clk: struct clk * being enabled
344 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
345 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
346 *
347 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
348 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
349 * @idlest_reg and @idlest_bit. No return value.
350 */
351static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
352 void __iomem **idlest_reg,
353 u8 *idlest_bit)
354{
355 u32 r;
356
357 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
358 *idlest_reg = (__force void __iomem *)r;
359 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
360}
361
362/**
363 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
364 * @clk: struct clk * being enabled
365 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
366 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
367 *
368 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
369 * target IDLEST bits. For our purposes, we are concerned with the
370 * target IDLEST bits, which exist at a different bit position than
371 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
372 * default find_idlest code assumes that they are at the same
373 * position.) No return value.
374 */
375static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
376 void __iomem **idlest_reg,
377 u8 *idlest_bit)
378{
379 u32 r;
380
381 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
382 *idlest_reg = (__force void __iomem *)r;
383 /* USBHOST_IDLE has same shift */
384 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
385}
386
387/**
388 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
389 * @clk: struct clk * being enabled
390 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
391 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
392 *
393 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
394 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
395 * @idlest_reg and @idlest_bit. No return value.
396 */
397static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
398 void __iomem **idlest_reg,
399 u8 *idlest_bit)
400{
401 u32 r;
402
403 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
404 *idlest_reg = (__force void __iomem *)r;
405 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
406}
407
02e19a96
PW		 408/**
409 * omap3_dpll_recalc - recalculate DPLL rate
410 * @clk: DPLL struct clk
411 *
412 * Recalculate and propagate the DPLL rate.
413 */
8b9dbc16 414static unsigned long omap3_dpll_recalc(struct clk *clk)
02e19a96 415{
8b9dbc16 416 return omap2_get_dpll_rate(clk);
02e19a96
PW		 417}
418
542313cc
PW		 419/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
420static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
421{
422 const struct dpll_data *dd;
ad67ef68 423 u32 v;
542313cc
PW		 424
425 dd = clk->dpll_data;
426
ad67ef68
PW		 427 v = __raw_readl(dd->control_reg);
428 v &= ~dd->enable_mask;
429 v |= clken_bits << __ffs(dd->enable_mask);
430 __raw_writel(v, dd->control_reg);
542313cc
PW		 431}
432
433/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
434static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
435{
436 const struct dpll_data *dd;
437 int i = 0;
438 int ret = -EINVAL;
542313cc
PW		 439
440 dd = clk->dpll_data;
441
c1bd7aaf 442 state <<= __ffs(dd->idlest_mask);
542313cc 443
c1bd7aaf 444 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
542313cc
PW		 445 i < MAX_DPLL_WAIT_TRIES) {
446 i++;
447 udelay(1);
448 }
449
450 if (i == MAX_DPLL_WAIT_TRIES) {
451 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
452 clk->name, (state) ? "locked" : "bypassed");
453 } else {
454 pr_debug("clock: %s transition to '%s' in %d loops\n",
455 clk->name, (state) ? "locked" : "bypassed", i);
456
457 ret = 0;
458 }
459
460 return ret;
461}
462
16c90f02
PW		 463/* From 3430 TRM ES2 4.7.6.2 */
464static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
465{
466 unsigned long fint;
467 u16 f = 0;
468
c0bf3132 469 fint = clk->dpll_data->clk_ref->rate / (n + 1);
16c90f02
PW		 470
471 pr_debug("clock: fint is %lu\n", fint);
472
473 if (fint >= 750000 && fint <= 1000000)
474 f = 0x3;
475 else if (fint > 1000000 && fint <= 1250000)
476 f = 0x4;
477 else if (fint > 1250000 && fint <= 1500000)
478 f = 0x5;
479 else if (fint > 1500000 && fint <= 1750000)
480 f = 0x6;
481 else if (fint > 1750000 && fint <= 2100000)
482 f = 0x7;
483 else if (fint > 7500000 && fint <= 10000000)
484 f = 0xB;
485 else if (fint > 10000000 && fint <= 12500000)
486 f = 0xC;
487 else if (fint > 12500000 && fint <= 15000000)
488 f = 0xD;
489 else if (fint > 15000000 && fint <= 17500000)
490 f = 0xE;
491 else if (fint > 17500000 && fint <= 21000000)
492 f = 0xF;
493 else
494 pr_debug("clock: unknown freqsel setting for %d\n", n);
495
496 return f;
497}
498
542313cc
PW		 499/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
500
501/*
502 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
503 * @clk: pointer to a DPLL struct clk
504 *
505 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
506 * readiness before returning. Will save and restore the DPLL's
507 * autoidle state across the enable, per the CDP code. If the DPLL
508 * locked successfully, return 0; if the DPLL did not lock in the time
509 * allotted, or DPLL3 was passed in, return -EINVAL.
510 */
511static int _omap3_noncore_dpll_lock(struct clk *clk)
512{
513 u8 ai;
514 int r;
515
516 if (clk == &dpll3_ck)
517 return -EINVAL;
518
519 pr_debug("clock: locking DPLL %s\n", clk->name);
520
521 ai = omap3_dpll_autoidle_read(clk);
522
416db864
PW		 523 omap3_dpll_deny_idle(clk);
524
542313cc
PW		 525 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
526
416db864
PW		 527 r = _omap3_wait_dpll_status(clk, 1);
528
529 if (ai)
542313cc 530 omap3_dpll_allow_idle(clk);
542313cc
PW		 531
532 return r;
533}
534
535/*
c0bf3132 536 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
542313cc
PW		 537 * @clk: pointer to a DPLL struct clk
538 *
539 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
540 * bypass mode, the DPLL's rate is set equal to its parent clock's
541 * rate. Waits for the DPLL to report readiness before returning.
542 * Will save and restore the DPLL's autoidle state across the enable,
543 * per the CDP code. If the DPLL entered bypass mode successfully,
544 * return 0; if the DPLL did not enter bypass in the time allotted, or
545 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
546 * return -EINVAL.
547 */
548static int _omap3_noncore_dpll_bypass(struct clk *clk)
549{
550 int r;
551 u8 ai;
552
553 if (clk == &dpll3_ck)
554 return -EINVAL;
555
556 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
557 return -EINVAL;
558
559 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
560 clk->name);
561
562 ai = omap3_dpll_autoidle_read(clk);
563
564 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
565
566 r = _omap3_wait_dpll_status(clk, 0);
567
568 if (ai)
569 omap3_dpll_allow_idle(clk);
570 else
571 omap3_dpll_deny_idle(clk);
572
573 return r;
574}
575
576/*
577 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
578 * @clk: pointer to a DPLL struct clk
579 *
580 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
581 * restore the DPLL's autoidle state across the stop, per the CDP
582 * code. If DPLL3 was passed in, or the DPLL does not support
583 * low-power stop, return -EINVAL; otherwise, return 0.
584 */
585static int _omap3_noncore_dpll_stop(struct clk *clk)
586{
587 u8 ai;
588
589 if (clk == &dpll3_ck)
590 return -EINVAL;
591
592 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
593 return -EINVAL;
594
595 pr_debug("clock: stopping DPLL %s\n", clk->name);
596
597 ai = omap3_dpll_autoidle_read(clk);
598
599 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
600
601 if (ai)
602 omap3_dpll_allow_idle(clk);
603 else
604 omap3_dpll_deny_idle(clk);
605
606 return 0;
607}
608
609/**
610 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
611 * @clk: pointer to a DPLL struct clk
612 *
613 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
614 * The choice of modes depends on the DPLL's programmed rate: if it is
615 * the same as the DPLL's parent clock, it will enter bypass;
616 * otherwise, it will enter lock. This code will wait for the DPLL to
617 * indicate readiness before returning, unless the DPLL takes too long
618 * to enter the target state. Intended to be used as the struct clk's
619 * enable function. If DPLL3 was passed in, or the DPLL does not
620 * support low-power stop, or if the DPLL took too long to enter
621 * bypass or lock, return -EINVAL; otherwise, return 0.
622 */
623static int omap3_noncore_dpll_enable(struct clk *clk)
624{
625 int r;
c0bf3132 626 struct dpll_data *dd;
542313cc
PW		 627
628 if (clk == &dpll3_ck)
629 return -EINVAL;
630
c0bf3132
RK		 631 dd = clk->dpll_data;
632 if (!dd)
633 return -EINVAL;
634
635 if (clk->rate == dd->clk_bypass->rate) {
636 WARN_ON(clk->parent != dd->clk_bypass);
542313cc 637 r = _omap3_noncore_dpll_bypass(clk);
c0bf3132
RK		 638 } else {
639 WARN_ON(clk->parent != dd->clk_ref);
542313cc 640 r = _omap3_noncore_dpll_lock(clk);
c0bf3132
RK		 641 }
642 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
643 if (!r)
644 clk->rate = omap2_get_dpll_rate(clk);
542313cc
PW		 645
646 return r;
647}
648
649/**
650 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
651 * @clk: pointer to a DPLL struct clk
652 *
653 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
654 * The choice of modes depends on the DPLL's programmed rate: if it is
655 * the same as the DPLL's parent clock, it will enter bypass;
656 * otherwise, it will enter lock. This code will wait for the DPLL to
657 * indicate readiness before returning, unless the DPLL takes too long
658 * to enter the target state. Intended to be used as the struct clk's
659 * enable function. If DPLL3 was passed in, or the DPLL does not
660 * support low-power stop, or if the DPLL took too long to enter
661 * bypass or lock, return -EINVAL; otherwise, return 0.
662 */
663static void omap3_noncore_dpll_disable(struct clk *clk)
664{
665 if (clk == &dpll3_ck)
666 return;
667
668 _omap3_noncore_dpll_stop(clk);
669}
670
16c90f02
PW		 671
672/* Non-CORE DPLL rate set code */
673
674/*
675 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
676 * @clk: struct clk * of DPLL to set
677 * @m: DPLL multiplier to set
678 * @n: DPLL divider to set
679 * @freqsel: FREQSEL value to set
680 *
681 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
682 * lock.. Returns -EINVAL upon error, or 0 upon success.
683 */
684static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
685{
686 struct dpll_data *dd = clk->dpll_data;
687 u32 v;
688
689 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
690 _omap3_noncore_dpll_bypass(clk);
691
f0587b63
PW		 692 /* Set jitter correction */
693 v = __raw_readl(dd->control_reg);
694 v &= ~dd->freqsel_mask;
695 v |= freqsel << __ffs(dd->freqsel_mask);
696 __raw_writel(v, dd->control_reg);
697
698 /* Set DPLL multiplier, divider */
16c90f02
PW		 699 v = __raw_readl(dd->mult_div1_reg);
700 v &= ~(dd->mult_mask | dd->div1_mask);
16c90f02 701 v |= m << __ffs(dd->mult_mask);
f0587b63 702 v |= (n - 1) << __ffs(dd->div1_mask);
16c90f02
PW		 703 __raw_writel(v, dd->mult_div1_reg);
704
705 /* We let the clock framework set the other output dividers later */
706
707 /* REVISIT: Set ramp-up delay? */
708
709 _omap3_noncore_dpll_lock(clk);
710
711 return 0;
712}
713
714/**
715 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
716 * @clk: struct clk * of DPLL to set
717 * @rate: rounded target rate
718 *
c0bf3132
RK		 719 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
720 * low-power bypass, and the target rate is the bypass source clock
721 * rate, then configure the DPLL for bypass. Otherwise, round the
722 * target rate if it hasn't been done already, then program and lock
723 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
16c90f02
PW		 724 */
725static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
726{
c0bf3132 727 struct clk *new_parent = NULL;
16c90f02
PW		 728 u16 freqsel;
729 struct dpll_data *dd;
c0bf3132 730 int ret;
16c90f02
PW		 731
732 if (!clk || !rate)
733 return -EINVAL;
734
735 dd = clk->dpll_data;
736 if (!dd)
737 return -EINVAL;
738
739 if (rate == omap2_get_dpll_rate(clk))
740 return 0;
741
c0bf3132
RK		 742 /*
743 * Ensure both the bypass and ref clocks are enabled prior to
744 * doing anything; we need the bypass clock running to reprogram
745 * the DPLL.
746 */
747 omap2_clk_enable(dd->clk_bypass);
748 omap2_clk_enable(dd->clk_ref);
16c90f02 749
c0bf3132
RK		 750 if (dd->clk_bypass->rate == rate &&
751 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
752 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
753
754 ret = _omap3_noncore_dpll_bypass(clk);
755 if (!ret)
756 new_parent = dd->clk_bypass;
757 } else {
758 if (dd->last_rounded_rate != rate)
759 omap2_dpll_round_rate(clk, rate);
16c90f02 760
c0bf3132
RK		 761 if (dd->last_rounded_rate == 0)
762 return -EINVAL;
16c90f02 763
c0bf3132
RK		 764 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
765 if (!freqsel)
766 WARN_ON(1);
767
768 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
769 clk->name, rate);
770
771 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
772 dd->last_rounded_n, freqsel);
773 if (!ret)
774 new_parent = dd->clk_ref;
775 }
776 if (!ret) {
777 /*
778 * Switch the parent clock in the heirarchy, and make sure
779 * that the new parent's usecount is correct. Note: we
780 * enable the new parent before disabling the old to avoid
781 * any unnecessary hardware disable->enable transitions.
782 */
783 if (clk->usecount) {
784 omap2_clk_enable(new_parent);
785 omap2_clk_disable(clk->parent);
786 }
787 clk_reparent(clk, new_parent);
788 clk->rate = rate;
789 }
790 omap2_clk_disable(dd->clk_ref);
791 omap2_clk_disable(dd->clk_bypass);
16c90f02 792
16c90f02
PW		 793 return 0;
794}
795
796static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
797{
798 /*
799 * According to the 12-5 CDP code from TI, "Limitation 2.5"
800 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
801 * on DPLL4.
802 */
803 if (omap_rev() == OMAP3430_REV_ES1_0) {
804 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
805 "silicon 'Limitation 2.5' on 3430ES1.\n");
806 return -EINVAL;
807 }
808 return omap3_noncore_dpll_set_rate(clk, rate);
809}
810
0eafd472
PW		 811
812/*
813 * CORE DPLL (DPLL3) rate programming functions
814 *
815 * These call into SRAM code to do the actual CM writes, since the SDRAM
816 * is clocked from DPLL3.
817 */
818
819/**
820 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
821 * @clk: struct clk * of DPLL to set
822 * @rate: rounded target rate
823 *
824 * Program the DPLL M2 divider with the rounded target rate. Returns
825 * -EINVAL upon error, or 0 upon success.
826 */
827static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
828{
829 u32 new_div = 0;
4519c2bf 830 u32 unlock_dll = 0;
c9812d04
PW		 831 u32 c;
832 unsigned long validrate, sdrcrate, mpurate;
58cda884
JP		 833 struct omap_sdrc_params *sdrc_cs0;
834 struct omap_sdrc_params *sdrc_cs1;
835 int ret;
0eafd472
PW		 836
837 if (!clk || !rate)
838 return -EINVAL;
839
840 if (clk != &dpll3_m2_ck)
841 return -EINVAL;
842
0eafd472
PW		 843 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
844 if (validrate != rate)
845 return -EINVAL;
846
847 sdrcrate = sdrc_ick.rate;
848 if (rate > clk->rate)
3afec633 849 sdrcrate <<= ((rate / clk->rate) >> 1);
0eafd472 850 else
3afec633 851 sdrcrate >>= ((clk->rate / rate) >> 1);
0eafd472 852
58cda884
JP		 853 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
854 if (ret)
0eafd472
PW		 855 return -EINVAL;
856
4519c2bf
PW		 857 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
858 pr_debug("clock: will unlock SDRC DLL\n");
859 unlock_dll = 1;
860 }
861
c9812d04
PW		 862 /*
863 * XXX This only needs to be done when the CPU frequency changes
864 */
865 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
866 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
867 c += 1; /* for safety */
868 c *= SDRC_MPURATE_LOOPS;
869 c >>= SDRC_MPURATE_SCALE;
870 if (c == 0)
871 c = 1;
872
b7aee4bf
PW		 873 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
874 validrate);
58cda884
JP		 875 pr_debug("clock: SDRC CS0 timing params used:"
876 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
877 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
878 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
879 if (sdrc_cs1)
880 pr_debug("clock: SDRC CS1 timing params used: "
881 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
882 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
883 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
884
885 if (sdrc_cs1)
886 omap3_configure_core_dpll(
887 new_div, unlock_dll, c, rate > clk->rate,
888 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
889 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
890 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
891 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
892 else
893 omap3_configure_core_dpll(
894 new_div, unlock_dll, c, rate > clk->rate,
895 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
896 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
897 0, 0, 0, 0);
0eafd472 898
0eafd472
PW		 899 return 0;
900}
901
902
548d8495
RK		 903static const struct clkops clkops_noncore_dpll_ops = {
904 .enable = &omap3_noncore_dpll_enable,
905 .disable = &omap3_noncore_dpll_disable,
906};
907
16c90f02
PW		 908/* DPLL autoidle read/set code */
909
910
542313cc
PW		 911/**
912 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
913 * @clk: struct clk * of the DPLL to read
914 *
915 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
916 * -EINVAL if passed a null pointer or if the struct clk does not
917 * appear to refer to a DPLL.
918 */
919static u32 omap3_dpll_autoidle_read(struct clk *clk)
920{
921 const struct dpll_data *dd;
922 u32 v;
923
924 if (!clk || !clk->dpll_data)
925 return -EINVAL;
926
927 dd = clk->dpll_data;
928
ad67ef68 929 v = __raw_readl(dd->autoidle_reg);
542313cc
PW		 930 v &= dd->autoidle_mask;
931 v >>= __ffs(dd->autoidle_mask);
932
933 return v;
934}
935
936/**
937 * omap3_dpll_allow_idle - enable DPLL autoidle bits
938 * @clk: struct clk * of the DPLL to operate on
939 *
940 * Enable DPLL automatic idle control. This automatic idle mode
941 * switching takes effect only when the DPLL is locked, at least on
942 * OMAP3430. The DPLL will enter low-power stop when its downstream
943 * clocks are gated. No return value.
944 */
945static void omap3_dpll_allow_idle(struct clk *clk)
946{
947 const struct dpll_data *dd;
ad67ef68 948 u32 v;
542313cc
PW		 949
950 if (!clk || !clk->dpll_data)
951 return;
952
953 dd = clk->dpll_data;
954
955 /*
956 * REVISIT: CORE DPLL can optionally enter low-power bypass
957 * by writing 0x5 instead of 0x1. Add some mechanism to
958 * optionally enter this mode.
959 */
ad67ef68
PW		 960 v = __raw_readl(dd->autoidle_reg);
961 v &= ~dd->autoidle_mask;
962 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
963 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 964}
965
966/**
967 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
968 * @clk: struct clk * of the DPLL to operate on
969 *
970 * Disable DPLL automatic idle control. No return value.
971 */
972static void omap3_dpll_deny_idle(struct clk *clk)
973{
974 const struct dpll_data *dd;
ad67ef68 975 u32 v;
542313cc
PW		 976
977 if (!clk || !clk->dpll_data)
978 return;
979
980 dd = clk->dpll_data;
981
ad67ef68
PW		 982 v = __raw_readl(dd->autoidle_reg);
983 v &= ~dd->autoidle_mask;
984 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
985 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 986}
987
988/* Clock control for DPLL outputs */
989
02e19a96
PW		 990/**
991 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
992 * @clk: DPLL output struct clk
993 *
994 * Using parent clock DPLL data, look up DPLL state. If locked, set our
995 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
996 */
8b9dbc16 997static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
02e19a96
PW		 998{
999 const struct dpll_data *dd;
8b9dbc16 1000 unsigned long rate;
02e19a96
PW		 1001 u32 v;
1002 struct clk *pclk;
1003
1004 /* Walk up the parents of clk, looking for a DPLL */
1005 pclk = clk->parent;
1006 while (pclk && !pclk->dpll_data)
1007 pclk = pclk->parent;
1008
1009 /* clk does not have a DPLL as a parent? */
1010 WARN_ON(!pclk);
1011
1012 dd = pclk->dpll_data;
1013
c0bf3132 1014 WARN_ON(!dd->enable_mask);
02e19a96
PW		 1015
1016 v = __raw_readl(dd->control_reg) & dd->enable_mask;
1017 v >>= __ffs(dd->enable_mask);
c0bf3132 1018 if (v != OMAP3XXX_EN_DPLL_LOCKED)
8b9dbc16 1019 rate = clk->parent->rate;
02e19a96 1020 else
8b9dbc16
RK		 1021 rate = clk->parent->rate * 2;
1022 return rate;
02e19a96
PW		 1023}
1024
542313cc
PW		 1025/* Common clock code */
1026
02e19a96
PW		 1027/*
1028 * As it is structured now, this will prevent an OMAP2/3 multiboot
1029 * kernel from compiling. This will need further attention.
1030 */
1031#if defined(CONFIG_ARCH_OMAP3)
1032
1033static struct clk_functions omap2_clk_functions = {
1034 .clk_enable = omap2_clk_enable,
1035 .clk_disable = omap2_clk_disable,
1036 .clk_round_rate = omap2_clk_round_rate,
1037 .clk_set_rate = omap2_clk_set_rate,
1038 .clk_set_parent = omap2_clk_set_parent,
1039 .clk_disable_unused = omap2_clk_disable_unused,
1040};
1041
1042/*
1043 * Set clocks for bypass mode for reboot to work.
1044 */
1045void omap2_clk_prepare_for_reboot(void)
1046{
1047 /* REVISIT: Not ready for 343x */
1048#if 0
1049 u32 rate;
1050
1051 if (vclk == NULL || sclk == NULL)
1052 return;
1053
1054 rate = clk_get_rate(sclk);
1055 clk_set_rate(vclk, rate);
1056#endif
1057}
1058
1059/* REVISIT: Move this init stuff out into clock.c */
1060
1061/*
1062 * Switch the MPU rate if specified on cmdline.
1063 * We cannot do this early until cmdline is parsed.
1064 */
1065static int __init omap2_clk_arch_init(void)
1066{
1067 if (!mpurate)
1068 return -EINVAL;
1069
1070 /* REVISIT: not yet ready for 343x */
11b66383
SP		 1071 if (clk_set_rate(&dpll1_ck, mpurate))
1072 printk(KERN_ERR "*** Unable to set MPU rate\n");
02e19a96
PW		 1073
1074 recalculate_root_clocks();
1075
11b66383 1076 printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
02e19a96 1077 "%ld.%01ld/%ld/%ld MHz\n",
11b66383
SP		 1078 (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
1079 (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
1080
1081 calibrate_delay();
02e19a96
PW		 1082
1083 return 0;
1084}
1085arch_initcall(omap2_clk_arch_init);
1086
1087int __init omap2_clk_init(void)
1088{
1089 /* struct prcm_config *prcm; */
44dc9d02 1090 struct omap_clk *c;
02e19a96
PW		 1091 /* u32 clkrate; */
1092 u32 cpu_clkflg;
1093
02e19a96
PW		 1094 if (cpu_is_omap34xx()) {
1095 cpu_mask = RATE_IN_343X;
44dc9d02 1096 cpu_clkflg = CK_343X;
02e19a96
PW		 1097
1098 /*
1099 * Update this if there are further clock changes between ES2
1100 * and production parts
1101 */
84a34344 1102 if (omap_rev() == OMAP3430_REV_ES1_0) {
02e19a96 1103 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
44dc9d02 1104 cpu_clkflg |= CK_3430ES1;
02e19a96
PW		 1105 } else {
1106 cpu_mask |= RATE_IN_3430ES2;
44dc9d02 1107 cpu_clkflg |= CK_3430ES2;
02e19a96
PW		 1108 }
1109 }
1110
1111 clk_init(&omap2_clk_functions);
1112
3f0a820c 1113 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
79716870 1114 clk_preinit(c->lk.clk);
3f0a820c 1115
44dc9d02
RK		 1116 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1117 if (c->cpu & cpu_clkflg) {
1118 clkdev_add(&c->lk);
1119 clk_register(c->lk.clk);
1120 omap2_init_clk_clkdm(c->lk.clk);
333943ba 1121 }
02e19a96
PW		 1122
1123 /* REVISIT: Not yet ready for OMAP3 */
1124#if 0
1125 /* Check the MPU rate set by bootloader */
1126 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1127 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1128 if (!(prcm->flags & cpu_mask))
1129 continue;
1130 if (prcm->xtal_speed != sys_ck.rate)
1131 continue;
1132 if (prcm->dpll_speed <= clkrate)
1133 break;
1134 }
1135 curr_prcm_set = prcm;
1136#endif
1137
1138 recalculate_root_clocks();
1139
11b66383 1140 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
02e19a96
PW		 1141 "%ld.%01ld/%ld/%ld MHz\n",
1142 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3760d31f 1143 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
02e19a96
PW		 1144
1145 /*
1146 * Only enable those clocks we will need, let the drivers
1147 * enable other clocks as necessary
1148 */
1149 clk_enable_init_clocks();
1150
1151 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1152 /* REVISIT: not yet ready for 343x */
1153#if 0
1154 vclk = clk_get(NULL, "virt_prcm_set");
1155 sclk = clk_get(NULL, "sys_ck");
1156#endif
1157 return 0;
1158}
1159
1160#endif
Linux kernel - Deliverables
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