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OMAP clock: drop .id field; ensure each clock has a unique name
[deliverable/linux.git] / arch / arm / mach-omap2 / clock34xx_data.c
CommitLineData
82e9bd58
PW		 1/*
2 * OMAP3 clock data
3 *
93340a22
PW		 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
82e9bd58
PW		 6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
82e9bd58
PW		 19#include <linux/kernel.h>
20#include <linux/clk.h>
93340a22 21#include <linux/list.h>
82e9bd58
PW		 22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
27#include "clock34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30#include "prm.h"
31#include "prm-regbits-34xx.h"
32
33/*
34 * clocks
35 */
36
37#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
38
39/* Maximum DPLL multiplier, divider values for OMAP3 */
93340a22 40#define OMAP3_MAX_DPLL_MULT 2047
358965d7 41#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
82e9bd58
PW		 42#define OMAP3_MAX_DPLL_DIV 128
43
44/*
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 */
51
52/* Forward declarations for DPLL bypass clocks */
53static struct clk dpll1_fck;
54static struct clk dpll2_fck;
55
56/* PRM CLOCKS */
57
58/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
59static struct clk omap_32k_fck = {
60 .name = "omap_32k_fck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .flags = RATE_FIXED,
64};
65
66static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck",
68 .ops = &clkops_null,
69 .rate = 32768,
70 .flags = RATE_FIXED,
71};
72
73/* Virtual source clocks for osc_sys_ck */
74static struct clk virt_12m_ck = {
75 .name = "virt_12m_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78 .flags = RATE_FIXED,
79};
80
81static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck",
83 .ops = &clkops_null,
84 .rate = 13000000,
85 .flags = RATE_FIXED,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 .flags = RATE_FIXED,
93};
94
95static struct clk virt_19_2m_ck = {
96 .name = "virt_19_2m_ck",
97 .ops = &clkops_null,
98 .rate = 19200000,
99 .flags = RATE_FIXED,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106 .flags = RATE_FIXED,
107};
108
109static struct clk virt_38_4m_ck = {
110 .name = "virt_38_4m_ck",
111 .ops = &clkops_null,
112 .rate = 38400000,
113 .flags = RATE_FIXED,
114};
115
116static const struct clksel_rate osc_sys_12m_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
118 { .div = 0 }
119};
120
121static const struct clksel_rate osc_sys_13m_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
123 { .div = 0 }
124};
125
126static const struct clksel_rate osc_sys_16_8m_rates[] = {
127 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
128 { .div = 0 }
129};
130
131static const struct clksel_rate osc_sys_19_2m_rates[] = {
132 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
133 { .div = 0 }
134};
135
136static const struct clksel_rate osc_sys_26m_rates[] = {
137 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
138 { .div = 0 }
139};
140
141static const struct clksel_rate osc_sys_38_4m_rates[] = {
142 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
143 { .div = 0 }
144};
145
146static const struct clksel osc_sys_clksel[] = {
147 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
148 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
149 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
150 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
151 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
152 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
153 { .parent = NULL },
154};
155
156/* Oscillator clock */
157/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
158static struct clk osc_sys_ck = {
159 .name = "osc_sys_ck",
160 .ops = &clkops_null,
161 .init = &omap2_init_clksel_parent,
162 .clksel_reg = OMAP3430_PRM_CLKSEL,
163 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
164 .clksel = osc_sys_clksel,
165 /* REVISIT: deal with autoextclkmode? */
166 .flags = RATE_FIXED,
167 .recalc = &omap2_clksel_recalc,
168};
169
170static const struct clksel_rate div2_rates[] = {
171 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
172 { .div = 2, .val = 2, .flags = RATE_IN_343X },
173 { .div = 0 }
174};
175
176static const struct clksel sys_clksel[] = {
177 { .parent = &osc_sys_ck, .rates = div2_rates },
178 { .parent = NULL }
179};
180
181/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
182/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
183static struct clk sys_ck = {
184 .name = "sys_ck",
185 .ops = &clkops_null,
186 .parent = &osc_sys_ck,
187 .init = &omap2_init_clksel_parent,
188 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
189 .clksel_mask = OMAP_SYSCLKDIV_MASK,
190 .clksel = sys_clksel,
191 .recalc = &omap2_clksel_recalc,
192};
193
194static struct clk sys_altclk = {
195 .name = "sys_altclk",
196 .ops = &clkops_null,
197};
198
199/* Optional external clock input for some McBSPs */
200static struct clk mcbsp_clks = {
201 .name = "mcbsp_clks",
202 .ops = &clkops_null,
203};
204
205/* PRM EXTERNAL CLOCK OUTPUT */
206
207static struct clk sys_clkout1 = {
208 .name = "sys_clkout1",
209 .ops = &clkops_omap2_dflt,
210 .parent = &osc_sys_ck,
211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
213 .recalc = &followparent_recalc,
214};
215
216/* DPLLS */
217
218/* CM CLOCKS */
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
678bc9a2
VB		 240static const struct clksel_rate div32_dpll4_rates_3630[] = {
241 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
242 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
243 { .div = 3, .val = 3, .flags = RATE_IN_36XX },
244 { .div = 4, .val = 4, .flags = RATE_IN_36XX },
245 { .div = 5, .val = 5, .flags = RATE_IN_36XX },
246 { .div = 6, .val = 6, .flags = RATE_IN_36XX },
247 { .div = 7, .val = 7, .flags = RATE_IN_36XX },
248 { .div = 8, .val = 8, .flags = RATE_IN_36XX },
249 { .div = 9, .val = 9, .flags = RATE_IN_36XX },
250 { .div = 10, .val = 10, .flags = RATE_IN_36XX },
251 { .div = 11, .val = 11, .flags = RATE_IN_36XX },
252 { .div = 12, .val = 12, .flags = RATE_IN_36XX },
253 { .div = 13, .val = 13, .flags = RATE_IN_36XX },
254 { .div = 14, .val = 14, .flags = RATE_IN_36XX },
255 { .div = 15, .val = 15, .flags = RATE_IN_36XX },
256 { .div = 16, .val = 16, .flags = RATE_IN_36XX },
257 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
258 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
259 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
260 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
261 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
262 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
263 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
264 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
265 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
266 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
267 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
268 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
269 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
270 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
271 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
272 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
273 { .div = 0 }
274};
275
82e9bd58
PW		 276/* DPLL1 */
277/* MPU clock source */
278/* Type: DPLL */
279static struct dpll_data dpll1_dd = {
280 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
281 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
282 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
283 .clk_bypass = &dpll1_fck,
284 .clk_ref = &sys_ck,
285 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
286 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
287 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
288 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
289 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
290 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
291 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
292 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
293 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
294 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
295 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
296 .max_multiplier = OMAP3_MAX_DPLL_MULT,
297 .min_divider = 1,
298 .max_divider = OMAP3_MAX_DPLL_DIV,
299 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
300};
301
302static struct clk dpll1_ck = {
303 .name = "dpll1_ck",
304 .ops = &clkops_null,
305 .parent = &sys_ck,
306 .dpll_data = &dpll1_dd,
307 .round_rate = &omap2_dpll_round_rate,
308 .set_rate = &omap3_noncore_dpll_set_rate,
309 .clkdm_name = "dpll1_clkdm",
310 .recalc = &omap3_dpll_recalc,
311};
312
313/*
314 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
315 * DPLL isn't bypassed.
316 */
317static struct clk dpll1_x2_ck = {
318 .name = "dpll1_x2_ck",
319 .ops = &clkops_null,
320 .parent = &dpll1_ck,
321 .clkdm_name = "dpll1_clkdm",
322 .recalc = &omap3_clkoutx2_recalc,
323};
324
325/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
326static const struct clksel div16_dpll1_x2m2_clksel[] = {
327 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
328 { .parent = NULL }
329};
330
331/*
332 * Does not exist in the TRM - needed to separate the M2 divider from
333 * bypass selection in mpu_ck
334 */
335static struct clk dpll1_x2m2_ck = {
336 .name = "dpll1_x2m2_ck",
337 .ops = &clkops_null,
338 .parent = &dpll1_x2_ck,
339 .init = &omap2_init_clksel_parent,
340 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
341 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
342 .clksel = div16_dpll1_x2m2_clksel,
343 .clkdm_name = "dpll1_clkdm",
344 .recalc = &omap2_clksel_recalc,
345};
346
347/* DPLL2 */
348/* IVA2 clock source */
349/* Type: DPLL */
350
351static struct dpll_data dpll2_dd = {
352 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
353 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
354 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
355 .clk_bypass = &dpll2_fck,
356 .clk_ref = &sys_ck,
357 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
358 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
359 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
360 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
361 (1 << DPLL_LOW_POWER_BYPASS),
362 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
363 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
364 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
365 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
366 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
367 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
368 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
369 .max_multiplier = OMAP3_MAX_DPLL_MULT,
370 .min_divider = 1,
371 .max_divider = OMAP3_MAX_DPLL_DIV,
372 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
373};
374
375static struct clk dpll2_ck = {
376 .name = "dpll2_ck",
4751227d 377 .ops = &omap3_clkops_noncore_dpll_ops,
82e9bd58
PW		 378 .parent = &sys_ck,
379 .dpll_data = &dpll2_dd,
380 .round_rate = &omap2_dpll_round_rate,
381 .set_rate = &omap3_noncore_dpll_set_rate,
382 .clkdm_name = "dpll2_clkdm",
383 .recalc = &omap3_dpll_recalc,
384};
385
386static const struct clksel div16_dpll2_m2x2_clksel[] = {
387 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
388 { .parent = NULL }
389};
390
391/*
392 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
393 * or CLKOUTX2. CLKOUT seems most plausible.
394 */
395static struct clk dpll2_m2_ck = {
396 .name = "dpll2_m2_ck",
397 .ops = &clkops_null,
398 .parent = &dpll2_ck,
399 .init = &omap2_init_clksel_parent,
400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
401 OMAP3430_CM_CLKSEL2_PLL),
402 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
403 .clksel = div16_dpll2_m2x2_clksel,
404 .clkdm_name = "dpll2_clkdm",
405 .recalc = &omap2_clksel_recalc,
406};
407
408/*
409 * DPLL3
410 * Source clock for all interfaces and for some device fclks
411 * REVISIT: Also supports fast relock bypass - not included below
412 */
413static struct dpll_data dpll3_dd = {
414 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
416 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
417 .clk_bypass = &sys_ck,
418 .clk_ref = &sys_ck,
419 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
420 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
421 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
422 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
423 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
424 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
425 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
426 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
427 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
428 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
429 .max_multiplier = OMAP3_MAX_DPLL_MULT,
430 .min_divider = 1,
431 .max_divider = OMAP3_MAX_DPLL_DIV,
432 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
433};
434
435static struct clk dpll3_ck = {
436 .name = "dpll3_ck",
437 .ops = &clkops_null,
438 .parent = &sys_ck,
439 .dpll_data = &dpll3_dd,
440 .round_rate = &omap2_dpll_round_rate,
441 .clkdm_name = "dpll3_clkdm",
442 .recalc = &omap3_dpll_recalc,
443};
444
445/*
446 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
447 * DPLL isn't bypassed
448 */
449static struct clk dpll3_x2_ck = {
450 .name = "dpll3_x2_ck",
451 .ops = &clkops_null,
452 .parent = &dpll3_ck,
453 .clkdm_name = "dpll3_clkdm",
454 .recalc = &omap3_clkoutx2_recalc,
455};
456
457static const struct clksel_rate div31_dpll3_rates[] = {
458 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
459 { .div = 2, .val = 2, .flags = RATE_IN_343X },
460 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
461 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
462 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
463 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
464 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
465 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
466 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
467 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
468 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
469 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
470 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
471 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
472 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
473 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
474 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
475 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
476 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
477 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
478 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
479 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
480 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
481 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
482 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
483 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
484 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
485 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
486 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
487 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
488 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
489 { .div = 0 },
490};
491
492static const struct clksel div31_dpll3m2_clksel[] = {
493 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
494 { .parent = NULL }
495};
496
497/* DPLL3 output M2 - primary control point for CORE speed */
498static struct clk dpll3_m2_ck = {
499 .name = "dpll3_m2_ck",
500 .ops = &clkops_null,
501 .parent = &dpll3_ck,
502 .init = &omap2_init_clksel_parent,
503 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
504 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
505 .clksel = div31_dpll3m2_clksel,
506 .clkdm_name = "dpll3_clkdm",
507 .round_rate = &omap2_clksel_round_rate,
508 .set_rate = &omap3_core_dpll_m2_set_rate,
509 .recalc = &omap2_clksel_recalc,
510};
511
512static struct clk core_ck = {
513 .name = "core_ck",
514 .ops = &clkops_null,
515 .parent = &dpll3_m2_ck,
516 .recalc = &followparent_recalc,
517};
518
519static struct clk dpll3_m2x2_ck = {
520 .name = "dpll3_m2x2_ck",
521 .ops = &clkops_null,
522 .parent = &dpll3_m2_ck,
523 .clkdm_name = "dpll3_clkdm",
524 .recalc = &omap3_clkoutx2_recalc,
525};
526
527/* The PWRDN bit is apparently only available on 3430ES2 and above */
528static const struct clksel div16_dpll3_clksel[] = {
529 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
530 { .parent = NULL }
531};
532
533/* This virtual clock is the source for dpll3_m3x2_ck */
534static struct clk dpll3_m3_ck = {
535 .name = "dpll3_m3_ck",
536 .ops = &clkops_null,
537 .parent = &dpll3_ck,
538 .init = &omap2_init_clksel_parent,
539 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
540 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
541 .clksel = div16_dpll3_clksel,
542 .clkdm_name = "dpll3_clkdm",
543 .recalc = &omap2_clksel_recalc,
544};
545
546/* The PWRDN bit is apparently only available on 3430ES2 and above */
547static struct clk dpll3_m3x2_ck = {
548 .name = "dpll3_m3x2_ck",
549 .ops = &clkops_omap2_dflt_wait,
550 .parent = &dpll3_m3_ck,
551 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
552 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
553 .flags = INVERT_ENABLE,
554 .clkdm_name = "dpll3_clkdm",
555 .recalc = &omap3_clkoutx2_recalc,
556};
557
558static struct clk emu_core_alwon_ck = {
559 .name = "emu_core_alwon_ck",
560 .ops = &clkops_null,
561 .parent = &dpll3_m3x2_ck,
562 .clkdm_name = "dpll3_clkdm",
563 .recalc = &followparent_recalc,
564};
565
566/* DPLL4 */
567/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
568/* Type: DPLL */
358965d7
RW		 569static struct dpll_data dpll4_dd;
570static struct dpll_data dpll4_dd_34xx __initdata = {
82e9bd58
PW		 571 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
572 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
573 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
574 .clk_bypass = &sys_ck,
575 .clk_ref = &sys_ck,
576 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
577 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
578 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
579 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
580 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
581 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
582 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
583 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
584 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
585 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
586 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
587 .max_multiplier = OMAP3_MAX_DPLL_MULT,
588 .min_divider = 1,
589 .max_divider = OMAP3_MAX_DPLL_DIV,
590 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
591};
592
358965d7
RW		 593static struct dpll_data dpll4_dd_3630 __initdata = {
594 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
595 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
596 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
597 .clk_bypass = &sys_ck,
598 .clk_ref = &sys_ck,
599 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
600 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
601 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
602 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
603 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
604 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
605 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
606 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
607 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
608 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
609 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
610 .min_divider = 1,
611 .max_divider = OMAP3_MAX_DPLL_DIV,
612 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
613 .flags = DPLL_J_TYPE
614};
615
82e9bd58
PW		 616static struct clk dpll4_ck = {
617 .name = "dpll4_ck",
4751227d 618 .ops = &omap3_clkops_noncore_dpll_ops,
82e9bd58
PW		 619 .parent = &sys_ck,
620 .dpll_data = &dpll4_dd,
621 .round_rate = &omap2_dpll_round_rate,
622 .set_rate = &omap3_dpll4_set_rate,
623 .clkdm_name = "dpll4_clkdm",
624 .recalc = &omap3_dpll_recalc,
625};
626
627/*
628 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
629 * DPLL isn't bypassed --
630 * XXX does this serve any downstream clocks?
631 */
632static struct clk dpll4_x2_ck = {
633 .name = "dpll4_x2_ck",
634 .ops = &clkops_null,
635 .parent = &dpll4_ck,
636 .clkdm_name = "dpll4_clkdm",
637 .recalc = &omap3_clkoutx2_recalc,
638};
639
640static const struct clksel div16_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
642 { .parent = NULL }
643};
644
678bc9a2
VB		 645static const struct clksel div32_dpll4_clksel[] = {
646 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
647 { .parent = NULL }
648};
649
82e9bd58 650/* This virtual clock is the source for dpll4_m2x2_ck */
678bc9a2
VB		 651static struct clk dpll4_m2_ck;
652
653static struct clk dpll4_m2_ck_34xx __initdata = {
82e9bd58
PW		 654 .name = "dpll4_m2_ck",
655 .ops = &clkops_null,
656 .parent = &dpll4_ck,
657 .init = &omap2_init_clksel_parent,
658 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
659 .clksel_mask = OMAP3430_DIV_96M_MASK,
660 .clksel = div16_dpll4_clksel,
661 .clkdm_name = "dpll4_clkdm",
662 .recalc = &omap2_clksel_recalc,
663};
664
678bc9a2
VB		 665static struct clk dpll4_m2_ck_3630 __initdata = {
666 .name = "dpll4_m2_ck",
667 .ops = &clkops_null,
668 .parent = &dpll4_ck,
669 .init = &omap2_init_clksel_parent,
670 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
671 .clksel_mask = OMAP3630_DIV_96M_MASK,
672 .clksel = div32_dpll4_clksel,
673 .clkdm_name = "dpll4_clkdm",
674 .recalc = &omap2_clksel_recalc,
675};
676
82e9bd58
PW		 677/* The PWRDN bit is apparently only available on 3430ES2 and above */
678static struct clk dpll4_m2x2_ck = {
679 .name = "dpll4_m2x2_ck",
680 .ops = &clkops_omap2_dflt_wait,
681 .parent = &dpll4_m2_ck,
682 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
683 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
684 .flags = INVERT_ENABLE,
685 .clkdm_name = "dpll4_clkdm",
686 .recalc = &omap3_clkoutx2_recalc,
687};
688
689/*
690 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
691 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
692 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
693 * CM_96K_(F)CLK.
694 */
7356f0b2
VB		 695
696/* Adding 192MHz Clock node needed by SGX */
697static struct clk omap_192m_alwon_fck = {
698 .name = "omap_192m_alwon_fck",
82e9bd58
PW		 699 .ops = &clkops_null,
700 .parent = &dpll4_m2x2_ck,
701 .recalc = &followparent_recalc,
702};
703
7356f0b2
VB		 704static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
705 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
706 { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
707 { .div = 0 }
708};
709
710static const struct clksel omap_96m_alwon_fck_clksel[] = {
711 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
712 { .parent = NULL }
82e9bd58
PW		 713};
714
715static const struct clksel_rate omap_96m_dpll_rates[] = {
716 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
717 { .div = 0 }
718};
719
720static const struct clksel_rate omap_96m_sys_rates[] = {
721 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
722 { .div = 0 }
723};
724
7356f0b2
VB		 725static struct clk omap_96m_alwon_fck = {
726 .name = "omap_96m_alwon_fck",
727 .ops = &clkops_null,
728 .parent = &dpll4_m2x2_ck,
729 .recalc = &followparent_recalc,
730};
731
732static struct clk omap_96m_alwon_fck_3630 = {
733 .name = "omap_96m_alwon_fck",
734 .parent = &omap_192m_alwon_fck,
735 .init = &omap2_init_clksel_parent,
736 .ops = &clkops_null,
737 .recalc = &omap2_clksel_recalc,
738 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
739 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
740 .clksel = omap_96m_alwon_fck_clksel
741};
742
743static struct clk cm_96m_fck = {
744 .name = "cm_96m_fck",
745 .ops = &clkops_null,
746 .parent = &omap_96m_alwon_fck,
747 .recalc = &followparent_recalc,
748};
749
82e9bd58
PW		 750static const struct clksel omap_96m_fck_clksel[] = {
751 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
752 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
753 { .parent = NULL }
754};
755
756static struct clk omap_96m_fck = {
757 .name = "omap_96m_fck",
758 .ops = &clkops_null,
759 .parent = &sys_ck,
760 .init = &omap2_init_clksel_parent,
761 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
762 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
763 .clksel = omap_96m_fck_clksel,
764 .recalc = &omap2_clksel_recalc,
765};
766
767/* This virtual clock is the source for dpll4_m3x2_ck */
678bc9a2
VB		 768static struct clk dpll4_m3_ck;
769
770static struct clk dpll4_m3_ck_34xx __initdata = {
82e9bd58
PW		 771 .name = "dpll4_m3_ck",
772 .ops = &clkops_null,
773 .parent = &dpll4_ck,
774 .init = &omap2_init_clksel_parent,
775 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
776 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
777 .clksel = div16_dpll4_clksel,
778 .clkdm_name = "dpll4_clkdm",
779 .recalc = &omap2_clksel_recalc,
780};
781
678bc9a2
VB		 782static struct clk dpll4_m3_ck_3630 __initdata = {
783 .name = "dpll4_m3_ck",
784 .ops = &clkops_null,
785 .parent = &dpll4_ck,
786 .init = &omap2_init_clksel_parent,
787 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
788 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
789 .clksel = div32_dpll4_clksel,
790 .clkdm_name = "dpll4_clkdm",
791 .recalc = &omap2_clksel_recalc,
792};
793
82e9bd58
PW		 794/* The PWRDN bit is apparently only available on 3430ES2 and above */
795static struct clk dpll4_m3x2_ck = {
796 .name = "dpll4_m3x2_ck",
797 .ops = &clkops_omap2_dflt_wait,
798 .parent = &dpll4_m3_ck,
82e9bd58
PW		 799 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
800 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
801 .flags = INVERT_ENABLE,
802 .clkdm_name = "dpll4_clkdm",
803 .recalc = &omap3_clkoutx2_recalc,
804};
805
806static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
807 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
808 { .div = 0 }
809};
810
811static const struct clksel_rate omap_54m_alt_rates[] = {
812 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
813 { .div = 0 }
814};
815
816static const struct clksel omap_54m_clksel[] = {
817 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
818 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
819 { .parent = NULL }
820};
821
822static struct clk omap_54m_fck = {
823 .name = "omap_54m_fck",
824 .ops = &clkops_null,
825 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
827 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
828 .clksel = omap_54m_clksel,
829 .recalc = &omap2_clksel_recalc,
830};
831
832static const struct clksel_rate omap_48m_cm96m_rates[] = {
833 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
834 { .div = 0 }
835};
836
837static const struct clksel_rate omap_48m_alt_rates[] = {
838 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
839 { .div = 0 }
840};
841
842static const struct clksel omap_48m_clksel[] = {
843 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
844 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
845 { .parent = NULL }
846};
847
848static struct clk omap_48m_fck = {
849 .name = "omap_48m_fck",
850 .ops = &clkops_null,
851 .init = &omap2_init_clksel_parent,
852 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
853 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
854 .clksel = omap_48m_clksel,
855 .recalc = &omap2_clksel_recalc,
856};
857
858static struct clk omap_12m_fck = {
859 .name = "omap_12m_fck",
860 .ops = &clkops_null,
861 .parent = &omap_48m_fck,
862 .fixed_div = 4,
e9b98f60 863 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 864};
865
866/* This virstual clock is the source for dpll4_m4x2_ck */
678bc9a2
VB		 867static struct clk dpll4_m4_ck;
868
869static struct clk dpll4_m4_ck_34xx __initdata = {
82e9bd58
PW		 870 .name = "dpll4_m4_ck",
871 .ops = &clkops_null,
872 .parent = &dpll4_ck,
873 .init = &omap2_init_clksel_parent,
874 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
875 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
876 .clksel = div16_dpll4_clksel,
877 .clkdm_name = "dpll4_clkdm",
878 .recalc = &omap2_clksel_recalc,
879 .set_rate = &omap2_clksel_set_rate,
880 .round_rate = &omap2_clksel_round_rate,
881};
882
678bc9a2
VB		 883static struct clk dpll4_m4_ck_3630 __initdata = {
884 .name = "dpll4_m4_ck",
885 .ops = &clkops_null,
886 .parent = &dpll4_ck,
887 .init = &omap2_init_clksel_parent,
888 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
889 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
890 .clksel = div32_dpll4_clksel,
891 .clkdm_name = "dpll4_clkdm",
892 .recalc = &omap2_clksel_recalc,
893 .set_rate = &omap2_clksel_set_rate,
894 .round_rate = &omap2_clksel_round_rate,
895};
896
82e9bd58
PW		 897/* The PWRDN bit is apparently only available on 3430ES2 and above */
898static struct clk dpll4_m4x2_ck = {
899 .name = "dpll4_m4x2_ck",
900 .ops = &clkops_omap2_dflt_wait,
901 .parent = &dpll4_m4_ck,
902 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
903 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
904 .flags = INVERT_ENABLE,
905 .clkdm_name = "dpll4_clkdm",
906 .recalc = &omap3_clkoutx2_recalc,
907};
908
909/* This virtual clock is the source for dpll4_m5x2_ck */
678bc9a2
VB		 910static struct clk dpll4_m5_ck;
911
912static struct clk dpll4_m5_ck_34xx __initdata = {
82e9bd58
PW		 913 .name = "dpll4_m5_ck",
914 .ops = &clkops_null,
915 .parent = &dpll4_ck,
916 .init = &omap2_init_clksel_parent,
917 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
918 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
919 .clksel = div16_dpll4_clksel,
920 .clkdm_name = "dpll4_clkdm",
3e3ee156
TT		 921 .set_rate = &omap2_clksel_set_rate,
922 .round_rate = &omap2_clksel_round_rate,
82e9bd58
PW		 923 .recalc = &omap2_clksel_recalc,
924};
925
678bc9a2
VB		 926static struct clk dpll4_m5_ck_3630 __initdata = {
927 .name = "dpll4_m5_ck",
928 .ops = &clkops_null,
929 .parent = &dpll4_ck,
930 .init = &omap2_init_clksel_parent,
931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
932 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
933 .clksel = div32_dpll4_clksel,
934 .clkdm_name = "dpll4_clkdm",
935 .recalc = &omap2_clksel_recalc,
936};
937
82e9bd58
PW		 938/* The PWRDN bit is apparently only available on 3430ES2 and above */
939static struct clk dpll4_m5x2_ck = {
940 .name = "dpll4_m5x2_ck",
941 .ops = &clkops_omap2_dflt_wait,
942 .parent = &dpll4_m5_ck,
943 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
944 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
945 .flags = INVERT_ENABLE,
946 .clkdm_name = "dpll4_clkdm",
947 .recalc = &omap3_clkoutx2_recalc,
948};
949
950/* This virtual clock is the source for dpll4_m6x2_ck */
678bc9a2
VB		 951static struct clk dpll4_m6_ck;
952
953static struct clk dpll4_m6_ck_34xx __initdata = {
82e9bd58
PW		 954 .name = "dpll4_m6_ck",
955 .ops = &clkops_null,
956 .parent = &dpll4_ck,
957 .init = &omap2_init_clksel_parent,
958 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
959 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
960 .clksel = div16_dpll4_clksel,
961 .clkdm_name = "dpll4_clkdm",
962 .recalc = &omap2_clksel_recalc,
963};
964
678bc9a2
VB		 965static struct clk dpll4_m6_ck_3630 __initdata = {
966 .name = "dpll4_m6_ck",
967 .ops = &clkops_null,
968 .parent = &dpll4_ck,
969 .init = &omap2_init_clksel_parent,
970 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
971 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
972 .clksel = div32_dpll4_clksel,
973 .clkdm_name = "dpll4_clkdm",
974 .recalc = &omap2_clksel_recalc,
975};
976
82e9bd58
PW		 977/* The PWRDN bit is apparently only available on 3430ES2 and above */
978static struct clk dpll4_m6x2_ck = {
979 .name = "dpll4_m6x2_ck",
980 .ops = &clkops_omap2_dflt_wait,
981 .parent = &dpll4_m6_ck,
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PW		 982 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
983 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
984 .flags = INVERT_ENABLE,
985 .clkdm_name = "dpll4_clkdm",
986 .recalc = &omap3_clkoutx2_recalc,
987};
988
989static struct clk emu_per_alwon_ck = {
990 .name = "emu_per_alwon_ck",
991 .ops = &clkops_null,
992 .parent = &dpll4_m6x2_ck,
993 .clkdm_name = "dpll4_clkdm",
994 .recalc = &followparent_recalc,
995};
996
997/* DPLL5 */
998/* Supplies 120MHz clock, USIM source clock */
999/* Type: DPLL */
1000/* 3430ES2 only */
1001static struct dpll_data dpll5_dd = {
1002 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1003 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1004 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1005 .clk_bypass = &sys_ck,
1006 .clk_ref = &sys_ck,
1007 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1008 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1009 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1010 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1011 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1012 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1013 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1014 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1015 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1016 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1017 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1018 .max_multiplier = OMAP3_MAX_DPLL_MULT,
1019 .min_divider = 1,
1020 .max_divider = OMAP3_MAX_DPLL_DIV,
1021 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
1022};
1023
1024static struct clk dpll5_ck = {
1025 .name = "dpll5_ck",
4751227d 1026 .ops = &omap3_clkops_noncore_dpll_ops,
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PW		 1027 .parent = &sys_ck,
1028 .dpll_data = &dpll5_dd,
1029 .round_rate = &omap2_dpll_round_rate,
1030 .set_rate = &omap3_noncore_dpll_set_rate,
1031 .clkdm_name = "dpll5_clkdm",
1032 .recalc = &omap3_dpll_recalc,
1033};
1034
1035static const struct clksel div16_dpll5_clksel[] = {
1036 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1037 { .parent = NULL }
1038};
1039
1040static struct clk dpll5_m2_ck = {
1041 .name = "dpll5_m2_ck",
1042 .ops = &clkops_null,
1043 .parent = &dpll5_ck,
1044 .init = &omap2_init_clksel_parent,
1045 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1046 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
1047 .clksel = div16_dpll5_clksel,
1048 .clkdm_name = "dpll5_clkdm",
1049 .recalc = &omap2_clksel_recalc,
1050};
1051
1052/* CM EXTERNAL CLOCK OUTPUTS */
1053
1054static const struct clksel_rate clkout2_src_core_rates[] = {
1055 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1056 { .div = 0 }
1057};
1058
1059static const struct clksel_rate clkout2_src_sys_rates[] = {
1060 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1061 { .div = 0 }
1062};
1063
1064static const struct clksel_rate clkout2_src_96m_rates[] = {
1065 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1066 { .div = 0 }
1067};
1068
1069static const struct clksel_rate clkout2_src_54m_rates[] = {
1070 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1071 { .div = 0 }
1072};
1073
1074static const struct clksel clkout2_src_clksel[] = {
1075 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1076 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1077 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1078 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1079 { .parent = NULL }
1080};
1081
1082static struct clk clkout2_src_ck = {
1083 .name = "clkout2_src_ck",
1084 .ops = &clkops_omap2_dflt,
1085 .init = &omap2_init_clksel_parent,
1086 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1087 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1088 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1089 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1090 .clksel = clkout2_src_clksel,
1091 .clkdm_name = "core_clkdm",
1092 .recalc = &omap2_clksel_recalc,
1093};
1094
1095static const struct clksel_rate sys_clkout2_rates[] = {
1096 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1097 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1098 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1099 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1100 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1101 { .div = 0 },
1102};
1103
1104static const struct clksel sys_clkout2_clksel[] = {
1105 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1106 { .parent = NULL },
1107};
1108
1109static struct clk sys_clkout2 = {
1110 .name = "sys_clkout2",
1111 .ops = &clkops_null,
1112 .init = &omap2_init_clksel_parent,
1113 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1114 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1115 .clksel = sys_clkout2_clksel,
1116 .recalc = &omap2_clksel_recalc,
1117};
1118
1119/* CM OUTPUT CLOCKS */
1120
1121static struct clk corex2_fck = {
1122 .name = "corex2_fck",
1123 .ops = &clkops_null,
1124 .parent = &dpll3_m2x2_ck,
1125 .recalc = &followparent_recalc,
1126};
1127
1128/* DPLL power domain clock controls */
1129
1130static const struct clksel_rate div4_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1132 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1133 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1134 { .div = 0 }
1135};
1136
1137static const struct clksel div4_core_clksel[] = {
1138 { .parent = &core_ck, .rates = div4_rates },
1139 { .parent = NULL }
1140};
1141
1142/*
1143 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1144 * may be inconsistent here?
1145 */
1146static struct clk dpll1_fck = {
1147 .name = "dpll1_fck",
1148 .ops = &clkops_null,
1149 .parent = &core_ck,
1150 .init = &omap2_init_clksel_parent,
1151 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1152 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1153 .clksel = div4_core_clksel,
1154 .recalc = &omap2_clksel_recalc,
1155};
1156
1157static struct clk mpu_ck = {
1158 .name = "mpu_ck",
1159 .ops = &clkops_null,
1160 .parent = &dpll1_x2m2_ck,
1161 .clkdm_name = "mpu_clkdm",
1162 .recalc = &followparent_recalc,
1163};
1164
1165/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1166static const struct clksel_rate arm_fck_rates[] = {
1167 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1168 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1169 { .div = 0 },
1170};
1171
1172static const struct clksel arm_fck_clksel[] = {
1173 { .parent = &mpu_ck, .rates = arm_fck_rates },
1174 { .parent = NULL }
1175};
1176
1177static struct clk arm_fck = {
1178 .name = "arm_fck",
1179 .ops = &clkops_null,
1180 .parent = &mpu_ck,
1181 .init = &omap2_init_clksel_parent,
1182 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1183 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1184 .clksel = arm_fck_clksel,
1185 .clkdm_name = "mpu_clkdm",
1186 .recalc = &omap2_clksel_recalc,
1187};
1188
1189/* XXX What about neon_clkdm ? */
1190
1191/*
1192 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1193 * although it is referenced - so this is a guess
1194 */
1195static struct clk emu_mpu_alwon_ck = {
1196 .name = "emu_mpu_alwon_ck",
1197 .ops = &clkops_null,
1198 .parent = &mpu_ck,
1199 .recalc = &followparent_recalc,
1200};
1201
1202static struct clk dpll2_fck = {
1203 .name = "dpll2_fck",
1204 .ops = &clkops_null,
1205 .parent = &core_ck,
1206 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1208 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1209 .clksel = div4_core_clksel,
1210 .recalc = &omap2_clksel_recalc,
1211};
1212
1213static struct clk iva2_ck = {
1214 .name = "iva2_ck",
1215 .ops = &clkops_omap2_dflt_wait,
1216 .parent = &dpll2_m2_ck,
82e9bd58
PW		 1217 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1218 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1219 .clkdm_name = "iva2_clkdm",
1220 .recalc = &followparent_recalc,
1221};
1222
1223/* Common interface clocks */
1224
1225static const struct clksel div2_core_clksel[] = {
1226 { .parent = &core_ck, .rates = div2_rates },
1227 { .parent = NULL }
1228};
1229
1230static struct clk l3_ick = {
1231 .name = "l3_ick",
1232 .ops = &clkops_null,
1233 .parent = &core_ck,
1234 .init = &omap2_init_clksel_parent,
1235 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1236 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1237 .clksel = div2_core_clksel,
1238 .clkdm_name = "core_l3_clkdm",
1239 .recalc = &omap2_clksel_recalc,
1240};
1241
1242static const struct clksel div2_l3_clksel[] = {
1243 { .parent = &l3_ick, .rates = div2_rates },
1244 { .parent = NULL }
1245};
1246
1247static struct clk l4_ick = {
1248 .name = "l4_ick",
1249 .ops = &clkops_null,
1250 .parent = &l3_ick,
1251 .init = &omap2_init_clksel_parent,
1252 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1253 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1254 .clksel = div2_l3_clksel,
1255 .clkdm_name = "core_l4_clkdm",
1256 .recalc = &omap2_clksel_recalc,
1257
1258};
1259
1260static const struct clksel div2_l4_clksel[] = {
1261 { .parent = &l4_ick, .rates = div2_rates },
1262 { .parent = NULL }
1263};
1264
1265static struct clk rm_ick = {
1266 .name = "rm_ick",
1267 .ops = &clkops_null,
1268 .parent = &l4_ick,
1269 .init = &omap2_init_clksel_parent,
1270 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1271 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1272 .clksel = div2_l4_clksel,
1273 .recalc = &omap2_clksel_recalc,
1274};
1275
1276/* GFX power domain */
1277
1278/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1279
1280static const struct clksel gfx_l3_clksel[] = {
1281 { .parent = &l3_ick, .rates = gfx_l3_rates },
1282 { .parent = NULL }
1283};
1284
1285/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1286static struct clk gfx_l3_ck = {
1287 .name = "gfx_l3_ck",
1288 .ops = &clkops_omap2_dflt_wait,
1289 .parent = &l3_ick,
82e9bd58
PW		 1290 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1291 .enable_bit = OMAP_EN_GFX_SHIFT,
1292 .recalc = &followparent_recalc,
1293};
1294
1295static struct clk gfx_l3_fck = {
1296 .name = "gfx_l3_fck",
1297 .ops = &clkops_null,
1298 .parent = &gfx_l3_ck,
1299 .init = &omap2_init_clksel_parent,
1300 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1301 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1302 .clksel = gfx_l3_clksel,
1303 .clkdm_name = "gfx_3430es1_clkdm",
1304 .recalc = &omap2_clksel_recalc,
1305};
1306
1307static struct clk gfx_l3_ick = {
1308 .name = "gfx_l3_ick",
1309 .ops = &clkops_null,
1310 .parent = &gfx_l3_ck,
1311 .clkdm_name = "gfx_3430es1_clkdm",
1312 .recalc = &followparent_recalc,
1313};
1314
1315static struct clk gfx_cg1_ck = {
1316 .name = "gfx_cg1_ck",
1317 .ops = &clkops_omap2_dflt_wait,
1318 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1319 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1320 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1321 .clkdm_name = "gfx_3430es1_clkdm",
1322 .recalc = &followparent_recalc,
1323};
1324
1325static struct clk gfx_cg2_ck = {
1326 .name = "gfx_cg2_ck",
1327 .ops = &clkops_omap2_dflt_wait,
1328 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1329 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1330 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1331 .clkdm_name = "gfx_3430es1_clkdm",
1332 .recalc = &followparent_recalc,
1333};
1334
1335/* SGX power domain - 3430ES2 only */
1336
1337static const struct clksel_rate sgx_core_rates[] = {
7356f0b2 1338 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
82e9bd58
PW		 1339 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1340 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1341 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1342 { .div = 0 },
1343};
1344
7356f0b2
VB		 1345static const struct clksel_rate sgx_192m_rates[] = {
1346 { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
1347 { .div = 0 },
1348};
1349
1350static const struct clksel_rate sgx_corex2_rates[] = {
1351 { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
1352 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1353 { .div = 0 },
1354};
1355
82e9bd58
PW		 1356static const struct clksel_rate sgx_96m_rates[] = {
1357 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1358 { .div = 0 },
1359};
1360
1361static const struct clksel sgx_clksel[] = {
1362 { .parent = &core_ck, .rates = sgx_core_rates },
1363 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
7356f0b2
VB		 1364 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1365 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1366 { .parent = NULL }
82e9bd58
PW		 1367};
1368
1369static struct clk sgx_fck = {
1370 .name = "sgx_fck",
1371 .ops = &clkops_omap2_dflt_wait,
1372 .init = &omap2_init_clksel_parent,
1373 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1374 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1375 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1376 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1377 .clksel = sgx_clksel,
1378 .clkdm_name = "sgx_clkdm",
1379 .recalc = &omap2_clksel_recalc,
7356f0b2
VB		 1380 .set_rate = &omap2_clksel_set_rate,
1381 .round_rate = &omap2_clksel_round_rate
82e9bd58
PW		 1382};
1383
1384static struct clk sgx_ick = {
1385 .name = "sgx_ick",
1386 .ops = &clkops_omap2_dflt_wait,
1387 .parent = &l3_ick,
1388 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1389 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1390 .clkdm_name = "sgx_clkdm",
1391 .recalc = &followparent_recalc,
1392};
1393
1394/* CORE power domain */
1395
1396static struct clk d2d_26m_fck = {
1397 .name = "d2d_26m_fck",
1398 .ops = &clkops_omap2_dflt_wait,
1399 .parent = &sys_ck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1402 .clkdm_name = "d2d_clkdm",
1403 .recalc = &followparent_recalc,
1404};
1405
1406static struct clk modem_fck = {
1407 .name = "modem_fck",
1408 .ops = &clkops_omap2_dflt_wait,
1409 .parent = &sys_ck,
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1412 .clkdm_name = "d2d_clkdm",
1413 .recalc = &followparent_recalc,
1414};
1415
1416static struct clk sad2d_ick = {
1417 .name = "sad2d_ick",
1418 .ops = &clkops_omap2_dflt_wait,
1419 .parent = &l3_ick,
1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1421 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1422 .clkdm_name = "d2d_clkdm",
1423 .recalc = &followparent_recalc,
1424};
1425
1426static struct clk mad2d_ick = {
1427 .name = "mad2d_ick",
1428 .ops = &clkops_omap2_dflt_wait,
1429 .parent = &l3_ick,
1430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1431 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1432 .clkdm_name = "d2d_clkdm",
1433 .recalc = &followparent_recalc,
1434};
1435
1436static const struct clksel omap343x_gpt_clksel[] = {
1437 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1438 { .parent = &sys_ck, .rates = gpt_sys_rates },
1439 { .parent = NULL}
1440};
1441
1442static struct clk gpt10_fck = {
1443 .name = "gpt10_fck",
1444 .ops = &clkops_omap2_dflt_wait,
1445 .parent = &sys_ck,
1446 .init = &omap2_init_clksel_parent,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1449 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1450 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1451 .clksel = omap343x_gpt_clksel,
1452 .clkdm_name = "core_l4_clkdm",
1453 .recalc = &omap2_clksel_recalc,
1454};
1455
1456static struct clk gpt11_fck = {
1457 .name = "gpt11_fck",
1458 .ops = &clkops_omap2_dflt_wait,
1459 .parent = &sys_ck,
1460 .init = &omap2_init_clksel_parent,
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1463 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1464 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1465 .clksel = omap343x_gpt_clksel,
1466 .clkdm_name = "core_l4_clkdm",
1467 .recalc = &omap2_clksel_recalc,
1468};
1469
1470static struct clk cpefuse_fck = {
1471 .name = "cpefuse_fck",
1472 .ops = &clkops_omap2_dflt,
1473 .parent = &sys_ck,
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1475 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk ts_fck = {
1480 .name = "ts_fck",
1481 .ops = &clkops_omap2_dflt,
1482 .parent = &omap_32k_fck,
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1484 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1485 .recalc = &followparent_recalc,
1486};
1487
1488static struct clk usbtll_fck = {
1489 .name = "usbtll_fck",
1490 .ops = &clkops_omap2_dflt,
1491 .parent = &dpll5_m2_ck,
1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1493 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1494 .recalc = &followparent_recalc,
1495};
1496
1497/* CORE 96M FCLK-derived clocks */
1498
1499static struct clk core_96m_fck = {
1500 .name = "core_96m_fck",
1501 .ops = &clkops_null,
1502 .parent = &omap_96m_fck,
1503 .clkdm_name = "core_l4_clkdm",
1504 .recalc = &followparent_recalc,
1505};
1506
1507static struct clk mmchs3_fck = {
b92c170d 1508 .name = "mmchs3_fck",
82e9bd58 1509 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1510 .parent = &core_96m_fck,
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1513 .clkdm_name = "core_l4_clkdm",
1514 .recalc = &followparent_recalc,
1515};
1516
1517static struct clk mmchs2_fck = {
b92c170d 1518 .name = "mmchs2_fck",
82e9bd58 1519 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1520 .parent = &core_96m_fck,
1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1523 .clkdm_name = "core_l4_clkdm",
1524 .recalc = &followparent_recalc,
1525};
1526
1527static struct clk mspro_fck = {
1528 .name = "mspro_fck",
1529 .ops = &clkops_omap2_dflt_wait,
1530 .parent = &core_96m_fck,
1531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1532 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1533 .clkdm_name = "core_l4_clkdm",
1534 .recalc = &followparent_recalc,
1535};
1536
1537static struct clk mmchs1_fck = {
b92c170d 1538 .name = "mmchs1_fck",
82e9bd58
PW		 1539 .ops = &clkops_omap2_dflt_wait,
1540 .parent = &core_96m_fck,
1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1542 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1543 .clkdm_name = "core_l4_clkdm",
1544 .recalc = &followparent_recalc,
1545};
1546
1547static struct clk i2c3_fck = {
b92c170d 1548 .name = "i2c3_fck",
82e9bd58 1549 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1550 .parent = &core_96m_fck,
1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1553 .clkdm_name = "core_l4_clkdm",
1554 .recalc = &followparent_recalc,
1555};
1556
1557static struct clk i2c2_fck = {
b92c170d 1558 .name = "i2c2_fck",
82e9bd58 1559 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1560 .parent = &core_96m_fck,
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1563 .clkdm_name = "core_l4_clkdm",
1564 .recalc = &followparent_recalc,
1565};
1566
1567static struct clk i2c1_fck = {
b92c170d 1568 .name = "i2c1_fck",
82e9bd58 1569 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1570 .parent = &core_96m_fck,
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1573 .clkdm_name = "core_l4_clkdm",
1574 .recalc = &followparent_recalc,
1575};
1576
1577/*
1578 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1579 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1580 */
1581static const struct clksel_rate common_mcbsp_96m_rates[] = {
1582 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1583 { .div = 0 }
1584};
1585
1586static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1587 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1588 { .div = 0 }
1589};
1590
1591static const struct clksel mcbsp_15_clksel[] = {
1592 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1593 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1594 { .parent = NULL }
1595};
1596
1597static struct clk mcbsp5_fck = {
b92c170d 1598 .name = "mcbsp5_fck",
82e9bd58 1599 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1600 .init = &omap2_init_clksel_parent,
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1603 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1604 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1605 .clksel = mcbsp_15_clksel,
1606 .clkdm_name = "core_l4_clkdm",
1607 .recalc = &omap2_clksel_recalc,
1608};
1609
1610static struct clk mcbsp1_fck = {
b92c170d 1611 .name = "mcbsp1_fck",
82e9bd58 1612 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1613 .init = &omap2_init_clksel_parent,
1614 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1615 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1616 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1617 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1618 .clksel = mcbsp_15_clksel,
1619 .clkdm_name = "core_l4_clkdm",
1620 .recalc = &omap2_clksel_recalc,
1621};
1622
1623/* CORE_48M_FCK-derived clocks */
1624
1625static struct clk core_48m_fck = {
1626 .name = "core_48m_fck",
1627 .ops = &clkops_null,
1628 .parent = &omap_48m_fck,
1629 .clkdm_name = "core_l4_clkdm",
1630 .recalc = &followparent_recalc,
1631};
1632
1633static struct clk mcspi4_fck = {
b92c170d 1634 .name = "mcspi4_fck",
82e9bd58 1635 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1636 .parent = &core_48m_fck,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1639 .recalc = &followparent_recalc,
1640};
1641
1642static struct clk mcspi3_fck = {
b92c170d 1643 .name = "mcspi3_fck",
82e9bd58 1644 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1645 .parent = &core_48m_fck,
1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1647 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1648 .recalc = &followparent_recalc,
1649};
1650
1651static struct clk mcspi2_fck = {
b92c170d 1652 .name = "mcspi2_fck",
82e9bd58 1653 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1654 .parent = &core_48m_fck,
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1656 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1657 .recalc = &followparent_recalc,
1658};
1659
1660static struct clk mcspi1_fck = {
b92c170d 1661 .name = "mcspi1_fck",
82e9bd58 1662 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1663 .parent = &core_48m_fck,
1664 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1665 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1666 .recalc = &followparent_recalc,
1667};
1668
1669static struct clk uart2_fck = {
1670 .name = "uart2_fck",
1671 .ops = &clkops_omap2_dflt_wait,
1672 .parent = &core_48m_fck,
1673 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1674 .enable_bit = OMAP3430_EN_UART2_SHIFT,
9b5bc5fa 1675 .clkdm_name = "core_l4_clkdm",
82e9bd58
PW		 1676 .recalc = &followparent_recalc,
1677};
1678
1679static struct clk uart1_fck = {
1680 .name = "uart1_fck",
1681 .ops = &clkops_omap2_dflt_wait,
1682 .parent = &core_48m_fck,
1683 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1684 .enable_bit = OMAP3430_EN_UART1_SHIFT,
9b5bc5fa 1685 .clkdm_name = "core_l4_clkdm",
82e9bd58
PW		 1686 .recalc = &followparent_recalc,
1687};
1688
1689static struct clk fshostusb_fck = {
1690 .name = "fshostusb_fck",
1691 .ops = &clkops_omap2_dflt_wait,
1692 .parent = &core_48m_fck,
1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1694 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1695 .recalc = &followparent_recalc,
1696};
1697
1698/* CORE_12M_FCK based clocks */
1699
1700static struct clk core_12m_fck = {
1701 .name = "core_12m_fck",
1702 .ops = &clkops_null,
1703 .parent = &omap_12m_fck,
1704 .clkdm_name = "core_l4_clkdm",
1705 .recalc = &followparent_recalc,
1706};
1707
1708static struct clk hdq_fck = {
1709 .name = "hdq_fck",
1710 .ops = &clkops_omap2_dflt_wait,
1711 .parent = &core_12m_fck,
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1713 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1714 .recalc = &followparent_recalc,
1715};
1716
1717/* DPLL3-derived clock */
1718
1719static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1720 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1721 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1722 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1723 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1724 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1725 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1726 { .div = 0 }
1727};
1728
1729static const struct clksel ssi_ssr_clksel[] = {
1730 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1731 { .parent = NULL }
1732};
1733
1734static struct clk ssi_ssr_fck_3430es1 = {
1735 .name = "ssi_ssr_fck",
1736 .ops = &clkops_omap2_dflt,
1737 .init = &omap2_init_clksel_parent,
1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1739 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1740 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1741 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1742 .clksel = ssi_ssr_clksel,
1743 .clkdm_name = "core_l4_clkdm",
1744 .recalc = &omap2_clksel_recalc,
1745};
1746
1747static struct clk ssi_ssr_fck_3430es2 = {
1748 .name = "ssi_ssr_fck",
1749 .ops = &clkops_omap3430es2_ssi_wait,
1750 .init = &omap2_init_clksel_parent,
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1753 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1754 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1755 .clksel = ssi_ssr_clksel,
1756 .clkdm_name = "core_l4_clkdm",
1757 .recalc = &omap2_clksel_recalc,
1758};
1759
1760static struct clk ssi_sst_fck_3430es1 = {
1761 .name = "ssi_sst_fck",
1762 .ops = &clkops_null,
1763 .parent = &ssi_ssr_fck_3430es1,
1764 .fixed_div = 2,
e9b98f60 1765 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 1766};
1767
1768static struct clk ssi_sst_fck_3430es2 = {
1769 .name = "ssi_sst_fck",
1770 .ops = &clkops_null,
1771 .parent = &ssi_ssr_fck_3430es2,
1772 .fixed_div = 2,
e9b98f60 1773 .recalc = &omap_fixed_divisor_recalc,
82e9bd58
PW		 1774};
1775
1776
1777
1778/* CORE_L3_ICK based clocks */
1779
1780/*
1781 * XXX must add clk_enable/clk_disable for these if standard code won't
1782 * handle it
1783 */
1784static struct clk core_l3_ick = {
1785 .name = "core_l3_ick",
1786 .ops = &clkops_null,
1787 .parent = &l3_ick,
1788 .clkdm_name = "core_l3_clkdm",
1789 .recalc = &followparent_recalc,
1790};
1791
1792static struct clk hsotgusb_ick_3430es1 = {
1793 .name = "hsotgusb_ick",
1794 .ops = &clkops_omap2_dflt,
1795 .parent = &core_l3_ick,
1796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1797 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1798 .clkdm_name = "core_l3_clkdm",
1799 .recalc = &followparent_recalc,
1800};
1801
1802static struct clk hsotgusb_ick_3430es2 = {
1803 .name = "hsotgusb_ick",
1804 .ops = &clkops_omap3430es2_hsotgusb_wait,
1805 .parent = &core_l3_ick,
1806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1808 .clkdm_name = "core_l3_clkdm",
1809 .recalc = &followparent_recalc,
1810};
1811
1812static struct clk sdrc_ick = {
1813 .name = "sdrc_ick",
1814 .ops = &clkops_omap2_dflt_wait,
1815 .parent = &core_l3_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1818 .flags = ENABLE_ON_INIT,
1819 .clkdm_name = "core_l3_clkdm",
1820 .recalc = &followparent_recalc,
1821};
1822
1823static struct clk gpmc_fck = {
1824 .name = "gpmc_fck",
1825 .ops = &clkops_null,
1826 .parent = &core_l3_ick,
1827 .flags = ENABLE_ON_INIT, /* huh? */
1828 .clkdm_name = "core_l3_clkdm",
1829 .recalc = &followparent_recalc,
1830};
1831
1832/* SECURITY_L3_ICK based clocks */
1833
1834static struct clk security_l3_ick = {
1835 .name = "security_l3_ick",
1836 .ops = &clkops_null,
1837 .parent = &l3_ick,
1838 .recalc = &followparent_recalc,
1839};
1840
1841static struct clk pka_ick = {
1842 .name = "pka_ick",
1843 .ops = &clkops_omap2_dflt_wait,
1844 .parent = &security_l3_ick,
1845 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1846 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1847 .recalc = &followparent_recalc,
1848};
1849
1850/* CORE_L4_ICK based clocks */
1851
1852static struct clk core_l4_ick = {
1853 .name = "core_l4_ick",
1854 .ops = &clkops_null,
1855 .parent = &l4_ick,
1856 .clkdm_name = "core_l4_clkdm",
1857 .recalc = &followparent_recalc,
1858};
1859
1860static struct clk usbtll_ick = {
1861 .name = "usbtll_ick",
1862 .ops = &clkops_omap2_dflt_wait,
1863 .parent = &core_l4_ick,
1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1865 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1866 .clkdm_name = "core_l4_clkdm",
1867 .recalc = &followparent_recalc,
1868};
1869
1870static struct clk mmchs3_ick = {
b92c170d 1871 .name = "mmchs3_ick",
82e9bd58 1872 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1873 .parent = &core_l4_ick,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1876 .clkdm_name = "core_l4_clkdm",
1877 .recalc = &followparent_recalc,
1878};
1879
1880/* Intersystem Communication Registers - chassis mode only */
1881static struct clk icr_ick = {
1882 .name = "icr_ick",
1883 .ops = &clkops_omap2_dflt_wait,
1884 .parent = &core_l4_ick,
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1887 .clkdm_name = "core_l4_clkdm",
1888 .recalc = &followparent_recalc,
1889};
1890
1891static struct clk aes2_ick = {
1892 .name = "aes2_ick",
1893 .ops = &clkops_omap2_dflt_wait,
1894 .parent = &core_l4_ick,
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1897 .clkdm_name = "core_l4_clkdm",
1898 .recalc = &followparent_recalc,
1899};
1900
1901static struct clk sha12_ick = {
1902 .name = "sha12_ick",
1903 .ops = &clkops_omap2_dflt_wait,
1904 .parent = &core_l4_ick,
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1907 .clkdm_name = "core_l4_clkdm",
1908 .recalc = &followparent_recalc,
1909};
1910
1911static struct clk des2_ick = {
1912 .name = "des2_ick",
1913 .ops = &clkops_omap2_dflt_wait,
1914 .parent = &core_l4_ick,
1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1917 .clkdm_name = "core_l4_clkdm",
1918 .recalc = &followparent_recalc,
1919};
1920
1921static struct clk mmchs2_ick = {
b92c170d 1922 .name = "mmchs2_ick",
82e9bd58 1923 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1924 .parent = &core_l4_ick,
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1927 .clkdm_name = "core_l4_clkdm",
1928 .recalc = &followparent_recalc,
1929};
1930
1931static struct clk mmchs1_ick = {
b92c170d 1932 .name = "mmchs1_ick",
82e9bd58
PW		 1933 .ops = &clkops_omap2_dflt_wait,
1934 .parent = &core_l4_ick,
1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1936 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1937 .clkdm_name = "core_l4_clkdm",
1938 .recalc = &followparent_recalc,
1939};
1940
1941static struct clk mspro_ick = {
1942 .name = "mspro_ick",
1943 .ops = &clkops_omap2_dflt_wait,
1944 .parent = &core_l4_ick,
1945 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1946 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1947 .clkdm_name = "core_l4_clkdm",
1948 .recalc = &followparent_recalc,
1949};
1950
1951static struct clk hdq_ick = {
1952 .name = "hdq_ick",
1953 .ops = &clkops_omap2_dflt_wait,
1954 .parent = &core_l4_ick,
1955 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1956 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1957 .clkdm_name = "core_l4_clkdm",
1958 .recalc = &followparent_recalc,
1959};
1960
1961static struct clk mcspi4_ick = {
b92c170d 1962 .name = "mcspi4_ick",
82e9bd58 1963 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1964 .parent = &core_l4_ick,
1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1966 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1967 .clkdm_name = "core_l4_clkdm",
1968 .recalc = &followparent_recalc,
1969};
1970
1971static struct clk mcspi3_ick = {
b92c170d 1972 .name = "mcspi3_ick",
82e9bd58 1973 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1974 .parent = &core_l4_ick,
1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1977 .clkdm_name = "core_l4_clkdm",
1978 .recalc = &followparent_recalc,
1979};
1980
1981static struct clk mcspi2_ick = {
b92c170d 1982 .name = "mcspi2_ick",
82e9bd58 1983 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1984 .parent = &core_l4_ick,
1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1987 .clkdm_name = "core_l4_clkdm",
1988 .recalc = &followparent_recalc,
1989};
1990
1991static struct clk mcspi1_ick = {
b92c170d 1992 .name = "mcspi1_ick",
82e9bd58 1993 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 1994 .parent = &core_l4_ick,
1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1997 .clkdm_name = "core_l4_clkdm",
1998 .recalc = &followparent_recalc,
1999};
2000
2001static struct clk i2c3_ick = {
b92c170d 2002 .name = "i2c3_ick",
82e9bd58 2003 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2004 .parent = &core_l4_ick,
2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2007 .clkdm_name = "core_l4_clkdm",
2008 .recalc = &followparent_recalc,
2009};
2010
2011static struct clk i2c2_ick = {
b92c170d 2012 .name = "i2c2_ick",
82e9bd58 2013 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2014 .parent = &core_l4_ick,
2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2016 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2017 .clkdm_name = "core_l4_clkdm",
2018 .recalc = &followparent_recalc,
2019};
2020
2021static struct clk i2c1_ick = {
b92c170d 2022 .name = "i2c1_ick",
82e9bd58 2023 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2024 .parent = &core_l4_ick,
2025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2026 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2027 .clkdm_name = "core_l4_clkdm",
2028 .recalc = &followparent_recalc,
2029};
2030
2031static struct clk uart2_ick = {
2032 .name = "uart2_ick",
2033 .ops = &clkops_omap2_dflt_wait,
2034 .parent = &core_l4_ick,
2035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2036 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2037 .clkdm_name = "core_l4_clkdm",
2038 .recalc = &followparent_recalc,
2039};
2040
2041static struct clk uart1_ick = {
2042 .name = "uart1_ick",
2043 .ops = &clkops_omap2_dflt_wait,
2044 .parent = &core_l4_ick,
2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2047 .clkdm_name = "core_l4_clkdm",
2048 .recalc = &followparent_recalc,
2049};
2050
2051static struct clk gpt11_ick = {
2052 .name = "gpt11_ick",
2053 .ops = &clkops_omap2_dflt_wait,
2054 .parent = &core_l4_ick,
2055 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2056 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2057 .clkdm_name = "core_l4_clkdm",
2058 .recalc = &followparent_recalc,
2059};
2060
2061static struct clk gpt10_ick = {
2062 .name = "gpt10_ick",
2063 .ops = &clkops_omap2_dflt_wait,
2064 .parent = &core_l4_ick,
2065 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2066 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2067 .clkdm_name = "core_l4_clkdm",
2068 .recalc = &followparent_recalc,
2069};
2070
2071static struct clk mcbsp5_ick = {
b92c170d 2072 .name = "mcbsp5_ick",
82e9bd58 2073 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2074 .parent = &core_l4_ick,
2075 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2076 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2077 .clkdm_name = "core_l4_clkdm",
2078 .recalc = &followparent_recalc,
2079};
2080
2081static struct clk mcbsp1_ick = {
b92c170d 2082 .name = "mcbsp1_ick",
82e9bd58 2083 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2084 .parent = &core_l4_ick,
2085 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2086 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2087 .clkdm_name = "core_l4_clkdm",
2088 .recalc = &followparent_recalc,
2089};
2090
2091static struct clk fac_ick = {
2092 .name = "fac_ick",
2093 .ops = &clkops_omap2_dflt_wait,
2094 .parent = &core_l4_ick,
2095 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2096 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2097 .clkdm_name = "core_l4_clkdm",
2098 .recalc = &followparent_recalc,
2099};
2100
2101static struct clk mailboxes_ick = {
2102 .name = "mailboxes_ick",
2103 .ops = &clkops_omap2_dflt_wait,
2104 .parent = &core_l4_ick,
2105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2106 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2107 .clkdm_name = "core_l4_clkdm",
2108 .recalc = &followparent_recalc,
2109};
2110
2111static struct clk omapctrl_ick = {
2112 .name = "omapctrl_ick",
2113 .ops = &clkops_omap2_dflt_wait,
2114 .parent = &core_l4_ick,
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2116 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2117 .flags = ENABLE_ON_INIT,
2118 .recalc = &followparent_recalc,
2119};
2120
2121/* SSI_L4_ICK based clocks */
2122
2123static struct clk ssi_l4_ick = {
2124 .name = "ssi_l4_ick",
2125 .ops = &clkops_null,
2126 .parent = &l4_ick,
2127 .clkdm_name = "core_l4_clkdm",
2128 .recalc = &followparent_recalc,
2129};
2130
2131static struct clk ssi_ick_3430es1 = {
2132 .name = "ssi_ick",
2133 .ops = &clkops_omap2_dflt,
2134 .parent = &ssi_l4_ick,
2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2137 .clkdm_name = "core_l4_clkdm",
2138 .recalc = &followparent_recalc,
2139};
2140
2141static struct clk ssi_ick_3430es2 = {
2142 .name = "ssi_ick",
2143 .ops = &clkops_omap3430es2_ssi_wait,
2144 .parent = &ssi_l4_ick,
2145 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2146 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2147 .clkdm_name = "core_l4_clkdm",
2148 .recalc = &followparent_recalc,
2149};
2150
2151/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2152 * but l4_ick makes more sense to me */
2153
2154static const struct clksel usb_l4_clksel[] = {
2155 { .parent = &l4_ick, .rates = div2_rates },
2156 { .parent = NULL },
2157};
2158
2159static struct clk usb_l4_ick = {
2160 .name = "usb_l4_ick",
2161 .ops = &clkops_omap2_dflt_wait,
2162 .parent = &l4_ick,
2163 .init = &omap2_init_clksel_parent,
2164 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2165 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2166 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2167 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2168 .clksel = usb_l4_clksel,
2169 .recalc = &omap2_clksel_recalc,
2170};
2171
2172/* SECURITY_L4_ICK2 based clocks */
2173
2174static struct clk security_l4_ick2 = {
2175 .name = "security_l4_ick2",
2176 .ops = &clkops_null,
2177 .parent = &l4_ick,
2178 .recalc = &followparent_recalc,
2179};
2180
2181static struct clk aes1_ick = {
2182 .name = "aes1_ick",
2183 .ops = &clkops_omap2_dflt_wait,
2184 .parent = &security_l4_ick2,
2185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2186 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2187 .recalc = &followparent_recalc,
2188};
2189
2190static struct clk rng_ick = {
2191 .name = "rng_ick",
2192 .ops = &clkops_omap2_dflt_wait,
2193 .parent = &security_l4_ick2,
2194 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2195 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2196 .recalc = &followparent_recalc,
2197};
2198
2199static struct clk sha11_ick = {
2200 .name = "sha11_ick",
2201 .ops = &clkops_omap2_dflt_wait,
2202 .parent = &security_l4_ick2,
2203 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2204 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2205 .recalc = &followparent_recalc,
2206};
2207
2208static struct clk des1_ick = {
2209 .name = "des1_ick",
2210 .ops = &clkops_omap2_dflt_wait,
2211 .parent = &security_l4_ick2,
2212 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2213 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2214 .recalc = &followparent_recalc,
2215};
2216
2217/* DSS */
2218static struct clk dss1_alwon_fck_3430es1 = {
2219 .name = "dss1_alwon_fck",
2220 .ops = &clkops_omap2_dflt,
2221 .parent = &dpll4_m4x2_ck,
2222 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2223 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2224 .clkdm_name = "dss_clkdm",
2225 .recalc = &followparent_recalc,
2226};
2227
2228static struct clk dss1_alwon_fck_3430es2 = {
2229 .name = "dss1_alwon_fck",
2230 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2231 .parent = &dpll4_m4x2_ck,
2232 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2233 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2234 .clkdm_name = "dss_clkdm",
2235 .recalc = &followparent_recalc,
2236};
2237
2238static struct clk dss_tv_fck = {
2239 .name = "dss_tv_fck",
2240 .ops = &clkops_omap2_dflt,
2241 .parent = &omap_54m_fck,
2242 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2243 .enable_bit = OMAP3430_EN_TV_SHIFT,
2244 .clkdm_name = "dss_clkdm",
2245 .recalc = &followparent_recalc,
2246};
2247
2248static struct clk dss_96m_fck = {
2249 .name = "dss_96m_fck",
2250 .ops = &clkops_omap2_dflt,
2251 .parent = &omap_96m_fck,
2252 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2253 .enable_bit = OMAP3430_EN_TV_SHIFT,
2254 .clkdm_name = "dss_clkdm",
2255 .recalc = &followparent_recalc,
2256};
2257
2258static struct clk dss2_alwon_fck = {
2259 .name = "dss2_alwon_fck",
2260 .ops = &clkops_omap2_dflt,
2261 .parent = &sys_ck,
2262 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2263 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2264 .clkdm_name = "dss_clkdm",
2265 .recalc = &followparent_recalc,
2266};
2267
2268static struct clk dss_ick_3430es1 = {
2269 /* Handles both L3 and L4 clocks */
2270 .name = "dss_ick",
2271 .ops = &clkops_omap2_dflt,
2272 .parent = &l4_ick,
2273 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2274 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2275 .clkdm_name = "dss_clkdm",
2276 .recalc = &followparent_recalc,
2277};
2278
2279static struct clk dss_ick_3430es2 = {
2280 /* Handles both L3 and L4 clocks */
2281 .name = "dss_ick",
2282 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2283 .parent = &l4_ick,
2284 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2285 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2286 .clkdm_name = "dss_clkdm",
2287 .recalc = &followparent_recalc,
2288};
2289
2290/* CAM */
2291
2292static struct clk cam_mclk = {
2293 .name = "cam_mclk",
2294 .ops = &clkops_omap2_dflt,
2295 .parent = &dpll4_m5x2_ck,
2296 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2297 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2298 .clkdm_name = "cam_clkdm",
2299 .recalc = &followparent_recalc,
2300};
2301
2302static struct clk cam_ick = {
2303 /* Handles both L3 and L4 clocks */
2304 .name = "cam_ick",
2305 .ops = &clkops_omap2_dflt,
2306 .parent = &l4_ick,
2307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2308 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2309 .clkdm_name = "cam_clkdm",
2310 .recalc = &followparent_recalc,
2311};
2312
2313static struct clk csi2_96m_fck = {
2314 .name = "csi2_96m_fck",
2315 .ops = &clkops_omap2_dflt,
2316 .parent = &core_96m_fck,
2317 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2318 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2319 .clkdm_name = "cam_clkdm",
2320 .recalc = &followparent_recalc,
2321};
2322
2323/* USBHOST - 3430ES2 only */
2324
2325static struct clk usbhost_120m_fck = {
2326 .name = "usbhost_120m_fck",
2327 .ops = &clkops_omap2_dflt,
2328 .parent = &dpll5_m2_ck,
2329 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2330 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2331 .clkdm_name = "usbhost_clkdm",
2332 .recalc = &followparent_recalc,
2333};
2334
2335static struct clk usbhost_48m_fck = {
2336 .name = "usbhost_48m_fck",
2337 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2338 .parent = &omap_48m_fck,
2339 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2340 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2341 .clkdm_name = "usbhost_clkdm",
2342 .recalc = &followparent_recalc,
2343};
2344
2345static struct clk usbhost_ick = {
2346 /* Handles both L3 and L4 clocks */
2347 .name = "usbhost_ick",
2348 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2349 .parent = &l4_ick,
2350 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2351 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2352 .clkdm_name = "usbhost_clkdm",
2353 .recalc = &followparent_recalc,
2354};
2355
2356/* WKUP */
2357
2358static const struct clksel_rate usim_96m_rates[] = {
2359 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2360 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2361 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2362 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2363 { .div = 0 },
2364};
2365
2366static const struct clksel_rate usim_120m_rates[] = {
2367 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2368 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2369 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2370 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2371 { .div = 0 },
2372};
2373
2374static const struct clksel usim_clksel[] = {
2375 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2376 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2377 { .parent = &sys_ck, .rates = div2_rates },
2378 { .parent = NULL },
2379};
2380
2381/* 3430ES2 only */
2382static struct clk usim_fck = {
2383 .name = "usim_fck",
2384 .ops = &clkops_omap2_dflt_wait,
2385 .init = &omap2_init_clksel_parent,
2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2387 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2388 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2389 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2390 .clksel = usim_clksel,
2391 .recalc = &omap2_clksel_recalc,
2392};
2393
2394/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2395static struct clk gpt1_fck = {
2396 .name = "gpt1_fck",
2397 .ops = &clkops_omap2_dflt_wait,
2398 .init = &omap2_init_clksel_parent,
2399 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2400 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2401 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2402 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2403 .clksel = omap343x_gpt_clksel,
2404 .clkdm_name = "wkup_clkdm",
2405 .recalc = &omap2_clksel_recalc,
2406};
2407
2408static struct clk wkup_32k_fck = {
2409 .name = "wkup_32k_fck",
2410 .ops = &clkops_null,
2411 .parent = &omap_32k_fck,
2412 .clkdm_name = "wkup_clkdm",
2413 .recalc = &followparent_recalc,
2414};
2415
2416static struct clk gpio1_dbck = {
2417 .name = "gpio1_dbck",
2418 .ops = &clkops_omap2_dflt,
2419 .parent = &wkup_32k_fck,
2420 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2421 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2422 .clkdm_name = "wkup_clkdm",
2423 .recalc = &followparent_recalc,
2424};
2425
2426static struct clk wdt2_fck = {
2427 .name = "wdt2_fck",
2428 .ops = &clkops_omap2_dflt_wait,
2429 .parent = &wkup_32k_fck,
2430 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2431 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2432 .clkdm_name = "wkup_clkdm",
2433 .recalc = &followparent_recalc,
2434};
2435
2436static struct clk wkup_l4_ick = {
2437 .name = "wkup_l4_ick",
2438 .ops = &clkops_null,
2439 .parent = &sys_ck,
2440 .clkdm_name = "wkup_clkdm",
2441 .recalc = &followparent_recalc,
2442};
2443
2444/* 3430ES2 only */
2445/* Never specifically named in the TRM, so we have to infer a likely name */
2446static struct clk usim_ick = {
2447 .name = "usim_ick",
2448 .ops = &clkops_omap2_dflt_wait,
2449 .parent = &wkup_l4_ick,
2450 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2451 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2452 .clkdm_name = "wkup_clkdm",
2453 .recalc = &followparent_recalc,
2454};
2455
2456static struct clk wdt2_ick = {
2457 .name = "wdt2_ick",
2458 .ops = &clkops_omap2_dflt_wait,
2459 .parent = &wkup_l4_ick,
2460 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2461 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2462 .clkdm_name = "wkup_clkdm",
2463 .recalc = &followparent_recalc,
2464};
2465
2466static struct clk wdt1_ick = {
2467 .name = "wdt1_ick",
2468 .ops = &clkops_omap2_dflt_wait,
2469 .parent = &wkup_l4_ick,
2470 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2471 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2472 .clkdm_name = "wkup_clkdm",
2473 .recalc = &followparent_recalc,
2474};
2475
2476static struct clk gpio1_ick = {
2477 .name = "gpio1_ick",
2478 .ops = &clkops_omap2_dflt_wait,
2479 .parent = &wkup_l4_ick,
2480 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2481 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2482 .clkdm_name = "wkup_clkdm",
2483 .recalc = &followparent_recalc,
2484};
2485
2486static struct clk omap_32ksync_ick = {
2487 .name = "omap_32ksync_ick",
2488 .ops = &clkops_omap2_dflt_wait,
2489 .parent = &wkup_l4_ick,
2490 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2491 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2492 .clkdm_name = "wkup_clkdm",
2493 .recalc = &followparent_recalc,
2494};
2495
2496/* XXX This clock no longer exists in 3430 TRM rev F */
2497static struct clk gpt12_ick = {
2498 .name = "gpt12_ick",
2499 .ops = &clkops_omap2_dflt_wait,
2500 .parent = &wkup_l4_ick,
2501 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2502 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2503 .clkdm_name = "wkup_clkdm",
2504 .recalc = &followparent_recalc,
2505};
2506
2507static struct clk gpt1_ick = {
2508 .name = "gpt1_ick",
2509 .ops = &clkops_omap2_dflt_wait,
2510 .parent = &wkup_l4_ick,
2511 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2512 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2513 .clkdm_name = "wkup_clkdm",
2514 .recalc = &followparent_recalc,
2515};
2516
2517
2518
2519/* PER clock domain */
2520
2521static struct clk per_96m_fck = {
2522 .name = "per_96m_fck",
2523 .ops = &clkops_null,
2524 .parent = &omap_96m_alwon_fck,
2525 .clkdm_name = "per_clkdm",
2526 .recalc = &followparent_recalc,
2527};
2528
2529static struct clk per_48m_fck = {
2530 .name = "per_48m_fck",
2531 .ops = &clkops_null,
2532 .parent = &omap_48m_fck,
2533 .clkdm_name = "per_clkdm",
2534 .recalc = &followparent_recalc,
2535};
2536
2537static struct clk uart3_fck = {
2538 .name = "uart3_fck",
2539 .ops = &clkops_omap2_dflt_wait,
2540 .parent = &per_48m_fck,
2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2542 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2543 .clkdm_name = "per_clkdm",
2544 .recalc = &followparent_recalc,
2545};
2546
2547static struct clk gpt2_fck = {
2548 .name = "gpt2_fck",
2549 .ops = &clkops_omap2_dflt_wait,
2550 .init = &omap2_init_clksel_parent,
2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2552 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2553 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2554 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2555 .clksel = omap343x_gpt_clksel,
2556 .clkdm_name = "per_clkdm",
2557 .recalc = &omap2_clksel_recalc,
2558};
2559
2560static struct clk gpt3_fck = {
2561 .name = "gpt3_fck",
2562 .ops = &clkops_omap2_dflt_wait,
2563 .init = &omap2_init_clksel_parent,
2564 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2565 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2566 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2567 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2568 .clksel = omap343x_gpt_clksel,
2569 .clkdm_name = "per_clkdm",
2570 .recalc = &omap2_clksel_recalc,
2571};
2572
2573static struct clk gpt4_fck = {
2574 .name = "gpt4_fck",
2575 .ops = &clkops_omap2_dflt_wait,
2576 .init = &omap2_init_clksel_parent,
2577 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2579 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2580 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2581 .clksel = omap343x_gpt_clksel,
2582 .clkdm_name = "per_clkdm",
2583 .recalc = &omap2_clksel_recalc,
2584};
2585
2586static struct clk gpt5_fck = {
2587 .name = "gpt5_fck",
2588 .ops = &clkops_omap2_dflt_wait,
2589 .init = &omap2_init_clksel_parent,
2590 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2591 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2592 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2593 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2594 .clksel = omap343x_gpt_clksel,
2595 .clkdm_name = "per_clkdm",
2596 .recalc = &omap2_clksel_recalc,
2597};
2598
2599static struct clk gpt6_fck = {
2600 .name = "gpt6_fck",
2601 .ops = &clkops_omap2_dflt_wait,
2602 .init = &omap2_init_clksel_parent,
2603 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2605 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2606 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2607 .clksel = omap343x_gpt_clksel,
2608 .clkdm_name = "per_clkdm",
2609 .recalc = &omap2_clksel_recalc,
2610};
2611
2612static struct clk gpt7_fck = {
2613 .name = "gpt7_fck",
2614 .ops = &clkops_omap2_dflt_wait,
2615 .init = &omap2_init_clksel_parent,
2616 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2617 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2618 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2619 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2620 .clksel = omap343x_gpt_clksel,
2621 .clkdm_name = "per_clkdm",
2622 .recalc = &omap2_clksel_recalc,
2623};
2624
2625static struct clk gpt8_fck = {
2626 .name = "gpt8_fck",
2627 .ops = &clkops_omap2_dflt_wait,
2628 .init = &omap2_init_clksel_parent,
2629 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2630 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2631 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2632 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2633 .clksel = omap343x_gpt_clksel,
2634 .clkdm_name = "per_clkdm",
2635 .recalc = &omap2_clksel_recalc,
2636};
2637
2638static struct clk gpt9_fck = {
2639 .name = "gpt9_fck",
2640 .ops = &clkops_omap2_dflt_wait,
2641 .init = &omap2_init_clksel_parent,
2642 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2643 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2644 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2645 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2646 .clksel = omap343x_gpt_clksel,
2647 .clkdm_name = "per_clkdm",
2648 .recalc = &omap2_clksel_recalc,
2649};
2650
2651static struct clk per_32k_alwon_fck = {
2652 .name = "per_32k_alwon_fck",
2653 .ops = &clkops_null,
2654 .parent = &omap_32k_fck,
2655 .clkdm_name = "per_clkdm",
2656 .recalc = &followparent_recalc,
2657};
2658
2659static struct clk gpio6_dbck = {
2660 .name = "gpio6_dbck",
2661 .ops = &clkops_omap2_dflt,
2662 .parent = &per_32k_alwon_fck,
2663 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2664 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2665 .clkdm_name = "per_clkdm",
2666 .recalc = &followparent_recalc,
2667};
2668
2669static struct clk gpio5_dbck = {
2670 .name = "gpio5_dbck",
2671 .ops = &clkops_omap2_dflt,
2672 .parent = &per_32k_alwon_fck,
2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2674 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2675 .clkdm_name = "per_clkdm",
2676 .recalc = &followparent_recalc,
2677};
2678
2679static struct clk gpio4_dbck = {
2680 .name = "gpio4_dbck",
2681 .ops = &clkops_omap2_dflt,
2682 .parent = &per_32k_alwon_fck,
2683 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2684 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2685 .clkdm_name = "per_clkdm",
2686 .recalc = &followparent_recalc,
2687};
2688
2689static struct clk gpio3_dbck = {
2690 .name = "gpio3_dbck",
2691 .ops = &clkops_omap2_dflt,
2692 .parent = &per_32k_alwon_fck,
2693 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2694 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2695 .clkdm_name = "per_clkdm",
2696 .recalc = &followparent_recalc,
2697};
2698
2699static struct clk gpio2_dbck = {
2700 .name = "gpio2_dbck",
2701 .ops = &clkops_omap2_dflt,
2702 .parent = &per_32k_alwon_fck,
2703 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2704 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2705 .clkdm_name = "per_clkdm",
2706 .recalc = &followparent_recalc,
2707};
2708
2709static struct clk wdt3_fck = {
2710 .name = "wdt3_fck",
2711 .ops = &clkops_omap2_dflt_wait,
2712 .parent = &per_32k_alwon_fck,
2713 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2714 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2715 .clkdm_name = "per_clkdm",
2716 .recalc = &followparent_recalc,
2717};
2718
2719static struct clk per_l4_ick = {
2720 .name = "per_l4_ick",
2721 .ops = &clkops_null,
2722 .parent = &l4_ick,
2723 .clkdm_name = "per_clkdm",
2724 .recalc = &followparent_recalc,
2725};
2726
2727static struct clk gpio6_ick = {
2728 .name = "gpio6_ick",
2729 .ops = &clkops_omap2_dflt_wait,
2730 .parent = &per_l4_ick,
2731 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2732 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2733 .clkdm_name = "per_clkdm",
2734 .recalc = &followparent_recalc,
2735};
2736
2737static struct clk gpio5_ick = {
2738 .name = "gpio5_ick",
2739 .ops = &clkops_omap2_dflt_wait,
2740 .parent = &per_l4_ick,
2741 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2743 .clkdm_name = "per_clkdm",
2744 .recalc = &followparent_recalc,
2745};
2746
2747static struct clk gpio4_ick = {
2748 .name = "gpio4_ick",
2749 .ops = &clkops_omap2_dflt_wait,
2750 .parent = &per_l4_ick,
2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2753 .clkdm_name = "per_clkdm",
2754 .recalc = &followparent_recalc,
2755};
2756
2757static struct clk gpio3_ick = {
2758 .name = "gpio3_ick",
2759 .ops = &clkops_omap2_dflt_wait,
2760 .parent = &per_l4_ick,
2761 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2762 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2763 .clkdm_name = "per_clkdm",
2764 .recalc = &followparent_recalc,
2765};
2766
2767static struct clk gpio2_ick = {
2768 .name = "gpio2_ick",
2769 .ops = &clkops_omap2_dflt_wait,
2770 .parent = &per_l4_ick,
2771 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2772 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2773 .clkdm_name = "per_clkdm",
2774 .recalc = &followparent_recalc,
2775};
2776
2777static struct clk wdt3_ick = {
2778 .name = "wdt3_ick",
2779 .ops = &clkops_omap2_dflt_wait,
2780 .parent = &per_l4_ick,
2781 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2782 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2783 .clkdm_name = "per_clkdm",
2784 .recalc = &followparent_recalc,
2785};
2786
2787static struct clk uart3_ick = {
2788 .name = "uart3_ick",
2789 .ops = &clkops_omap2_dflt_wait,
2790 .parent = &per_l4_ick,
2791 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2792 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2793 .clkdm_name = "per_clkdm",
2794 .recalc = &followparent_recalc,
2795};
2796
2797static struct clk gpt9_ick = {
2798 .name = "gpt9_ick",
2799 .ops = &clkops_omap2_dflt_wait,
2800 .parent = &per_l4_ick,
2801 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2802 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2803 .clkdm_name = "per_clkdm",
2804 .recalc = &followparent_recalc,
2805};
2806
2807static struct clk gpt8_ick = {
2808 .name = "gpt8_ick",
2809 .ops = &clkops_omap2_dflt_wait,
2810 .parent = &per_l4_ick,
2811 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2812 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2813 .clkdm_name = "per_clkdm",
2814 .recalc = &followparent_recalc,
2815};
2816
2817static struct clk gpt7_ick = {
2818 .name = "gpt7_ick",
2819 .ops = &clkops_omap2_dflt_wait,
2820 .parent = &per_l4_ick,
2821 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2822 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2823 .clkdm_name = "per_clkdm",
2824 .recalc = &followparent_recalc,
2825};
2826
2827static struct clk gpt6_ick = {
2828 .name = "gpt6_ick",
2829 .ops = &clkops_omap2_dflt_wait,
2830 .parent = &per_l4_ick,
2831 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2832 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2833 .clkdm_name = "per_clkdm",
2834 .recalc = &followparent_recalc,
2835};
2836
2837static struct clk gpt5_ick = {
2838 .name = "gpt5_ick",
2839 .ops = &clkops_omap2_dflt_wait,
2840 .parent = &per_l4_ick,
2841 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2842 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2843 .clkdm_name = "per_clkdm",
2844 .recalc = &followparent_recalc,
2845};
2846
2847static struct clk gpt4_ick = {
2848 .name = "gpt4_ick",
2849 .ops = &clkops_omap2_dflt_wait,
2850 .parent = &per_l4_ick,
2851 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2852 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2853 .clkdm_name = "per_clkdm",
2854 .recalc = &followparent_recalc,
2855};
2856
2857static struct clk gpt3_ick = {
2858 .name = "gpt3_ick",
2859 .ops = &clkops_omap2_dflt_wait,
2860 .parent = &per_l4_ick,
2861 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2862 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2863 .clkdm_name = "per_clkdm",
2864 .recalc = &followparent_recalc,
2865};
2866
2867static struct clk gpt2_ick = {
2868 .name = "gpt2_ick",
2869 .ops = &clkops_omap2_dflt_wait,
2870 .parent = &per_l4_ick,
2871 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2872 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2873 .clkdm_name = "per_clkdm",
2874 .recalc = &followparent_recalc,
2875};
2876
2877static struct clk mcbsp2_ick = {
b92c170d 2878 .name = "mcbsp2_ick",
82e9bd58 2879 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2880 .parent = &per_l4_ick,
2881 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2882 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2883 .clkdm_name = "per_clkdm",
2884 .recalc = &followparent_recalc,
2885};
2886
2887static struct clk mcbsp3_ick = {
b92c170d 2888 .name = "mcbsp3_ick",
82e9bd58 2889 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2890 .parent = &per_l4_ick,
2891 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2892 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2893 .clkdm_name = "per_clkdm",
2894 .recalc = &followparent_recalc,
2895};
2896
2897static struct clk mcbsp4_ick = {
b92c170d 2898 .name = "mcbsp4_ick",
82e9bd58 2899 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2900 .parent = &per_l4_ick,
2901 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2902 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2903 .clkdm_name = "per_clkdm",
2904 .recalc = &followparent_recalc,
2905};
2906
2907static const struct clksel mcbsp_234_clksel[] = {
073463ca 2908 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
82e9bd58
PW		 2909 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2910 { .parent = NULL }
2911};
2912
2913static struct clk mcbsp2_fck = {
b92c170d 2914 .name = "mcbsp2_fck",
82e9bd58 2915 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2916 .init = &omap2_init_clksel_parent,
2917 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2918 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2919 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2920 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2921 .clksel = mcbsp_234_clksel,
2922 .clkdm_name = "per_clkdm",
2923 .recalc = &omap2_clksel_recalc,
2924};
2925
2926static struct clk mcbsp3_fck = {
b92c170d 2927 .name = "mcbsp3_fck",
82e9bd58 2928 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2929 .init = &omap2_init_clksel_parent,
2930 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2931 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2932 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2933 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2934 .clksel = mcbsp_234_clksel,
2935 .clkdm_name = "per_clkdm",
2936 .recalc = &omap2_clksel_recalc,
2937};
2938
2939static struct clk mcbsp4_fck = {
b92c170d 2940 .name = "mcbsp4_fck",
82e9bd58 2941 .ops = &clkops_omap2_dflt_wait,
82e9bd58
PW		 2942 .init = &omap2_init_clksel_parent,
2943 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2944 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2945 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2946 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2947 .clksel = mcbsp_234_clksel,
2948 .clkdm_name = "per_clkdm",
2949 .recalc = &omap2_clksel_recalc,
2950};
2951
2952/* EMU clocks */
2953
2954/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2955
2956static const struct clksel_rate emu_src_sys_rates[] = {
2957 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2958 { .div = 0 },
2959};
2960
2961static const struct clksel_rate emu_src_core_rates[] = {
2962 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2963 { .div = 0 },
2964};
2965
2966static const struct clksel_rate emu_src_per_rates[] = {
2967 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2968 { .div = 0 },
2969};
2970
2971static const struct clksel_rate emu_src_mpu_rates[] = {
2972 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2973 { .div = 0 },
2974};
2975
2976static const struct clksel emu_src_clksel[] = {
2977 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2978 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2979 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2980 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2981 { .parent = NULL },
2982};
2983
2984/*
2985 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2986 * to switch the source of some of the EMU clocks.
2987 * XXX Are there CLKEN bits for these EMU clks?
2988 */
2989static struct clk emu_src_ck = {
2990 .name = "emu_src_ck",
2991 .ops = &clkops_null,
2992 .init = &omap2_init_clksel_parent,
2993 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2994 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2995 .clksel = emu_src_clksel,
2996 .clkdm_name = "emu_clkdm",
2997 .recalc = &omap2_clksel_recalc,
2998};
2999
3000static const struct clksel_rate pclk_emu_rates[] = {
3001 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3002 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3003 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3004 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3005 { .div = 0 },
3006};
3007
3008static const struct clksel pclk_emu_clksel[] = {
3009 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3010 { .parent = NULL },
3011};
3012
3013static struct clk pclk_fck = {
3014 .name = "pclk_fck",
3015 .ops = &clkops_null,
3016 .init = &omap2_init_clksel_parent,
3017 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3018 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3019 .clksel = pclk_emu_clksel,
3020 .clkdm_name = "emu_clkdm",
3021 .recalc = &omap2_clksel_recalc,
3022};
3023
3024static const struct clksel_rate pclkx2_emu_rates[] = {
3025 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3026 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3027 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3028 { .div = 0 },
3029};
3030
3031static const struct clksel pclkx2_emu_clksel[] = {
3032 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3033 { .parent = NULL },
3034};
3035
3036static struct clk pclkx2_fck = {
3037 .name = "pclkx2_fck",
3038 .ops = &clkops_null,
3039 .init = &omap2_init_clksel_parent,
3040 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3041 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3042 .clksel = pclkx2_emu_clksel,
3043 .clkdm_name = "emu_clkdm",
3044 .recalc = &omap2_clksel_recalc,
3045};
3046
3047static const struct clksel atclk_emu_clksel[] = {
3048 { .parent = &emu_src_ck, .rates = div2_rates },
3049 { .parent = NULL },
3050};
3051
3052static struct clk atclk_fck = {
3053 .name = "atclk_fck",
3054 .ops = &clkops_null,
3055 .init = &omap2_init_clksel_parent,
3056 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3057 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3058 .clksel = atclk_emu_clksel,
3059 .clkdm_name = "emu_clkdm",
3060 .recalc = &omap2_clksel_recalc,
3061};
3062
3063static struct clk traceclk_src_fck = {
3064 .name = "traceclk_src_fck",
3065 .ops = &clkops_null,
3066 .init = &omap2_init_clksel_parent,
3067 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3068 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3069 .clksel = emu_src_clksel,
3070 .clkdm_name = "emu_clkdm",
3071 .recalc = &omap2_clksel_recalc,
3072};
3073
3074static const struct clksel_rate traceclk_rates[] = {
3075 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3076 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3077 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3078 { .div = 0 },
3079};
3080
3081static const struct clksel traceclk_clksel[] = {
3082 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3083 { .parent = NULL },
3084};
3085
3086static struct clk traceclk_fck = {
3087 .name = "traceclk_fck",
3088 .ops = &clkops_null,
3089 .init = &omap2_init_clksel_parent,
3090 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3091 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3092 .clksel = traceclk_clksel,
3093 .clkdm_name = "emu_clkdm",
3094 .recalc = &omap2_clksel_recalc,
3095};
3096
3097/* SR clocks */
3098
3099/* SmartReflex fclk (VDD1) */
3100static struct clk sr1_fck = {
3101 .name = "sr1_fck",
3102 .ops = &clkops_omap2_dflt_wait,
3103 .parent = &sys_ck,
3104 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3105 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3106 .recalc = &followparent_recalc,
3107};
3108
3109/* SmartReflex fclk (VDD2) */
3110static struct clk sr2_fck = {
3111 .name = "sr2_fck",
3112 .ops = &clkops_omap2_dflt_wait,
3113 .parent = &sys_ck,
3114 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3115 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3116 .recalc = &followparent_recalc,
3117};
3118
3119static struct clk sr_l4_ick = {
3120 .name = "sr_l4_ick",
3121 .ops = &clkops_null, /* RMK: missing? */
3122 .parent = &l4_ick,
3123 .clkdm_name = "core_l4_clkdm",
3124 .recalc = &followparent_recalc,
3125};
3126
3127/* SECURE_32K_FCK clocks */
3128
3129static struct clk gpt12_fck = {
3130 .name = "gpt12_fck",
3131 .ops = &clkops_null,
3132 .parent = &secure_32k_fck,
3133 .recalc = &followparent_recalc,
3134};
3135
3136static struct clk wdt1_fck = {
3137 .name = "wdt1_fck",
3138 .ops = &clkops_null,
3139 .parent = &secure_32k_fck,
3140 .recalc = &followparent_recalc,
3141};
3142
3cc4a2fc
RL		 3143/* Clocks for AM35XX */
3144static struct clk ipss_ick = {
3145 .name = "ipss_ick",
3146 .ops = &clkops_am35xx_ipss_wait,
3147 .parent = &core_l3_ick,
3148 .clkdm_name = "core_l3_clkdm",
3149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3150 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3151 .recalc = &followparent_recalc,
3152};
3153
3154static struct clk emac_ick = {
3155 .name = "emac_ick",
3156 .ops = &clkops_am35xx_ipss_module_wait,
3157 .parent = &ipss_ick,
3158 .clkdm_name = "core_l3_clkdm",
3159 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3160 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3161 .recalc = &followparent_recalc,
3162};
3163
3164static struct clk rmii_ck = {
3165 .name = "rmii_ck",
3166 .ops = &clkops_null,
3167 .flags = RATE_FIXED,
3168 .rate = 50000000,
3169};
3170
3171static struct clk emac_fck = {
3172 .name = "emac_fck",
3173 .ops = &clkops_omap2_dflt,
3174 .parent = &rmii_ck,
3175 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3176 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3177 .recalc = &followparent_recalc,
3178};
3179
3180static struct clk hsotgusb_ick_am35xx = {
3181 .name = "hsotgusb_ick",
3182 .ops = &clkops_am35xx_ipss_module_wait,
3183 .parent = &ipss_ick,
3184 .clkdm_name = "core_l3_clkdm",
3185 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3186 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3187 .recalc = &followparent_recalc,
3188};
3189
3190static struct clk hsotgusb_fck_am35xx = {
3191 .name = "hsotgusb_fck",
3192 .ops = &clkops_omap2_dflt,
3193 .parent = &sys_ck,
3194 .clkdm_name = "core_l3_clkdm",
3195 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3196 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3197 .recalc = &followparent_recalc,
3198};
3199
3200static struct clk hecc_ck = {
3201 .name = "hecc_ck",
3202 .ops = &clkops_am35xx_ipss_module_wait,
3203 .parent = &sys_ck,
3204 .clkdm_name = "core_l3_clkdm",
3205 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3206 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3207 .recalc = &followparent_recalc,
3208};
3209
3210static struct clk vpfe_ick = {
3211 .name = "vpfe_ick",
3212 .ops = &clkops_am35xx_ipss_module_wait,
3213 .parent = &ipss_ick,
3214 .clkdm_name = "core_l3_clkdm",
3215 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3216 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3217 .recalc = &followparent_recalc,
3218};
3219
3220static struct clk pclk_ck = {
3221 .name = "pclk_ck",
3222 .ops = &clkops_null,
3223 .flags = RATE_FIXED,
3224 .rate = 27000000,
3225};
3226
3227static struct clk vpfe_fck = {
3228 .name = "vpfe_fck",
3229 .ops = &clkops_omap2_dflt,
3230 .parent = &pclk_ck,
3231 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3232 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3233 .recalc = &followparent_recalc,
3234};
3235
3236/*
3237 * The UART1/2 functional clock acts as the functional
3238 * clock for UART4. No separate fclk control available.
3239 */
3240static struct clk uart4_ick_am35xx = {
3241 .name = "uart4_ick",
3242 .ops = &clkops_omap2_dflt_wait,
3243 .parent = &core_l4_ick,
3244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3245 .enable_bit = AM35XX_EN_UART4_SHIFT,
3246 .clkdm_name = "core_l4_clkdm",
3247 .recalc = &followparent_recalc,
3248};
3249
82e9bd58
PW		 3250
3251/*
3252 * clkdev
3253 */
3254
ced82529
RL		 3255/* XXX At some point we should rename this file to clock3xxx_data.c */
3256static struct omap_clk omap3xxx_clks[] = {
3257 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3258 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3259 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3260 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3261 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3262 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3263 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3264 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3265 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3266 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3267 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3268 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3269 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3270 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3271 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
82e9bd58
PW		 3272 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3273 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
ced82529
RL		 3274 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3275 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3276 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3277 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3278 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3279 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3280 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3281 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3282 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3283 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
7356f0b2 3284 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
ced82529
RL		 3285 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3286 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3287 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3288 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3289 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3290 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3291 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3292 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3293 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3294 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3295 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3296 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3297 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3298 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3299 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3300 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3301 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3302 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3303 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3304 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3305 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3306 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3307 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3308 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3309 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3310 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
82e9bd58
PW		 3311 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3312 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
ced82529
RL		 3313 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3314 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3315 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
82e9bd58
PW		 3316 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3317 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3318 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3319 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3320 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
ced82529
RL		 3321 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3322 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
82e9bd58
PW		 3323 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3324 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3325 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3326 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
ced82529
RL		 3327 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3328 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3330 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3332 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3333 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3334 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
82e9bd58 3335 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
ced82529
RL		 3336 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3337 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3338 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3339 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3340 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3341 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3342 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3343 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3344 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3345 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3346 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3347 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3348 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
82e9bd58 3349 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
ced82529
RL		 3350 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3351 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
82e9bd58
PW		 3352 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3353 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3354 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3355 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
ced82529 3356 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
82e9bd58
PW		 3357 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3358 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
ced82529
RL		 3359 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3360 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
82e9bd58
PW		 3361 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3362 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
ced82529
RL		 3363 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3364 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3365 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
82e9bd58
PW		 3366 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3367 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3368 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
3369 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
ced82529
RL		 3370 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3371 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
82e9bd58 3372 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
ced82529
RL		 3373 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3374 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3375 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3376 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3377 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3378 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3379 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3380 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3381 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3382 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3383 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3384 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3385 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3386 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
82e9bd58
PW		 3387 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3388 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
ced82529 3389 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
82e9bd58
PW		 3390 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3391 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3392 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3393 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3394 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3395 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3396 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3397 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3398 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3399 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
ced82529
RL		 3400 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3401 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3402 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3403 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
82e9bd58 3404 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
ced82529 3405 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
82e9bd58
PW		 3406 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3407 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3408 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
ced82529
RL		 3409 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3410 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3411 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
82e9bd58 3412 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
ced82529
RL		 3413 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3414 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3415 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3416 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
82e9bd58
PW		 3417 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3418 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
ced82529
RL		 3419 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3420 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3421 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3422 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3423 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3424 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3425 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3426 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3427 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3428 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3429 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3430 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3431 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3432 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3433 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3434 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3435 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3436 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3437 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3438 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3439 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3440 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3441 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3442 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3443 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3444 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3445 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3446 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3447 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3448 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3449 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3450 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3451 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3452 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3453 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3454 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3455 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3456 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3457 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3458 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3459 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3460 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3461 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3462 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3463 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3464 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3465 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3466 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3467 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3468 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3469 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3470 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
82e9bd58
PW		 3471 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3472 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3473 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
ced82529
RL		 3474 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3475 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3476 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3cc4a2fc
RL		 3477 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3478 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3479 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3480 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
3481 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
3482 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3483 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3484 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3485 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3486 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3487 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
82e9bd58
PW		 3488};
3489
3490
e80a9729 3491int __init omap3xxx_clk_init(void)
82e9bd58 3492{
82e9bd58 3493 struct omap_clk *c;
2c8a177e 3494 u32 cpu_clkflg = CK_3XXX;
82e9bd58 3495
ced82529
RL		 3496 if (cpu_is_omap3517()) {
3497 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3498 cpu_clkflg |= CK_3517;
3499 } else if (cpu_is_omap3505()) {
3500 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3501 cpu_clkflg |= CK_3505;
3502 } else if (cpu_is_omap34xx()) {
82e9bd58 3503 cpu_mask = RATE_IN_343X;
2c8a177e 3504 cpu_clkflg |= CK_343X;
82e9bd58
PW		 3505
3506 /*
3507 * Update this if there are further clock changes between ES2
3508 * and production parts
3509 */
3510 if (omap_rev() == OMAP3430_REV_ES1_0) {
3511 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3512 cpu_clkflg |= CK_3430ES1;
3513 } else {
3514 cpu_mask |= RATE_IN_3430ES2;
3515 cpu_clkflg |= CK_3430ES2;
3516 }
3517 }
7356f0b2
VB		 3518 if (omap3_has_192mhz_clk())
3519 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
82e9bd58 3520
a7e069fc 3521 if (cpu_is_omap3630()) {
678bc9a2
VB		 3522 cpu_mask |= RATE_IN_36XX;
3523 cpu_clkflg |= CK_36XX;
3524
3525 /*
3526 * XXX This type of dynamic rewriting of the clock tree is
3527 * deprecated and should be revised soon.
3528 */
3529 dpll4_m2_ck = dpll4_m2_ck_3630;
3530 dpll4_m3_ck = dpll4_m3_ck_3630;
3531 dpll4_m4_ck = dpll4_m4_ck_3630;
3532 dpll4_m5_ck = dpll4_m5_ck_3630;
3533 dpll4_m6_ck = dpll4_m6_ck_3630;
3534
a7e069fc
MT		 3535 /*
3536 * For 3630: override clkops_omap2_dflt_wait for the
3537 * clocks affected from PWRDN reset Limitation
3538 */
3539 dpll3_m3x2_ck.ops =
3540 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3541 dpll4_m2x2_ck.ops =
3542 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3543 dpll4_m3x2_ck.ops =
3544 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3545 dpll4_m4x2_ck.ops =
3546 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3547 dpll4_m5x2_ck.ops =
3548 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3549 dpll4_m6x2_ck.ops =
3550 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
678bc9a2
VB		 3551 } else {
3552 /*
3553 * XXX This type of dynamic rewriting of the clock tree is
3554 * deprecated and should be revised soon.
3555 */
3556 dpll4_m2_ck = dpll4_m2_ck_34xx;
3557 dpll4_m3_ck = dpll4_m3_ck_34xx;
3558 dpll4_m4_ck = dpll4_m4_ck_34xx;
3559 dpll4_m5_ck = dpll4_m5_ck_34xx;
3560 dpll4_m6_ck = dpll4_m6_ck_34xx;
a7e069fc
MT		 3561 }
3562
358965d7
RW		 3563 if (cpu_is_omap3630())
3564 dpll4_dd = dpll4_dd_3630;
3565 else
3566 dpll4_dd = dpll4_dd_34xx;
3567
82e9bd58
PW		 3568 clk_init(&omap2_clk_functions);
3569
ced82529 3570 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
82e9bd58
PW		 3571 clk_preinit(c->lk.clk);
3572
ced82529 3573 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
82e9bd58
PW		 3574 if (c->cpu & cpu_clkflg) {
3575 clkdev_add(&c->lk);
3576 clk_register(c->lk.clk);
3577 omap2_init_clk_clkdm(c->lk.clk);
3578 }
3579
82e9bd58
PW		 3580 recalculate_root_clocks();
3581
3582 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3583 "%ld.%01ld/%ld/%ld MHz\n",
3584 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3585 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3586
3587 /*
3588 * Only enable those clocks we will need, let the drivers
3589 * enable other clocks as necessary
3590 */
3591 clk_enable_init_clocks();
3592
3593 /*
3594 * Lock DPLL5 and put it in autoidle.
3595 */
3596 if (omap_rev() >= OMAP3430_REV_ES2_0)
3597 omap3_clk_lock_dpll5();
3598
3599 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3600 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3601 arm_fck_p = clk_get(NULL, "arm_fck");
3602
3603 return 0;
3604}
Linux kernel - Deliverables
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