projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 657ebfad PW |
1 | /* |
| 2 | * OMAP3-specific clock framework functions | |
| 3 | * | |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | |
| 6 | * | |
| 7 | * Paul Walmsley | |
| 8 | * Jouni Högander | |
| 9 | * | |
| 10 | * Parts of this code are based on code written by | |
| 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or modify | |
| 14 | * it under the terms of the GNU General Public License version 2 as | |
| 15 | * published by the Free Software Foundation. | |
| 16 | */ | |
| 17 | #undef DEBUG | |
| 18 | ||
| 19 | #include <linux/kernel.h> | |
| 20 | #include <linux/errno.h> | |
| 657ebfad PW |
21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> | |
| 657ebfad | 23 | |
| 657ebfad PW |
24 | #include <plat/clock.h> |
| 25 | ||
| dbc04161 | 26 | #include "soc.h" |
| 657ebfad PW |
27 | #include "clock.h" |
| 28 | #include "clock3xxx.h" | |
| 59fb659b | 29 | #include "prm2xxx_3xxx.h" |
| 657ebfad | 30 | #include "prm-regbits-34xx.h" |
| 59fb659b | 31 | #include "cm2xxx_3xxx.h" |
| 657ebfad PW |
32 | #include "cm-regbits-34xx.h" |
| 33 | ||
| 34 | /* | |
| 35 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | |
| 36 | * that are sourced by DPLL5, and both of these require this clock | |
| 37 | * to be at 120 MHz for proper operation. | |
| 38 | */ | |
| 39 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | |
| 40 | ||
| 41 | /* needed by omap3_core_dpll_m2_set_rate() */ | |
| 42 | struct clk *sdrc_ick_p, *arm_fck_p; | |
| 43 | ||
| 44 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |
| 45 | { | |
| 46 | /* | |
| 47 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | |
| 48 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | |
| 49 | * on DPLL4. | |
| 50 | */ | |
| 51 | if (omap_rev() == OMAP3430_REV_ES1_0) { | |
| 7852ec05 | 52 | pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); |
| 657ebfad PW |
53 | return -EINVAL; |
| 54 | } | |
| 55 | ||
| 56 | return omap3_noncore_dpll_set_rate(clk, rate); | |
| 57 | } | |
| 58 | ||
| 59 | void __init omap3_clk_lock_dpll5(void) | |
| 60 | { | |
| 61 | struct clk *dpll5_clk; | |
| 62 | struct clk *dpll5_m2_clk; | |
| 63 | ||
| 64 | dpll5_clk = clk_get(NULL, "dpll5_ck"); | |
| 65 | clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); | |
| 4d7cb45e | 66 | clk_prepare_enable(dpll5_clk); |
| 657ebfad | 67 | |
| 657ebfad PW |
68 | /* Program dpll5_m2_clk divider for no division */ |
| 69 | dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); | |
| 4d7cb45e | 70 | clk_prepare_enable(dpll5_m2_clk); |
| 657ebfad PW |
71 | clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); |
| 72 | ||
| 4d7cb45e RN |
73 | clk_disable_unprepare(dpll5_m2_clk); |
| 74 | clk_disable_unprepare(dpll5_clk); | |
| 657ebfad PW |
75 | return; |
| 76 | } | |
| 77 | ||
| 78 | /* Common clock code */ | |
| 79 | ||
| 657ebfad | 80 | /* |
| 4d30e82c PW |
81 | * Switch the MPU rate if specified on cmdline. We cannot do this |
| 82 | * early until cmdline is parsed. XXX This should be removed from the | |
| 83 | * clock code and handled by the OPP layer code in the near future. | |
| 657ebfad PW |
84 | */ |
| 85 | static int __init omap3xxx_clk_arch_init(void) | |
| 86 | { | |
| 4d30e82c | 87 | int ret; |
| 657ebfad PW |
88 | |
| 89 | if (!cpu_is_omap34xx()) | |
| 90 | return 0; | |
| 91 | ||
| 4d30e82c PW |
92 | ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); |
| 93 | if (!ret) | |
| f1f4b770 | 94 | omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); |
| 657ebfad | 95 | |
| 4d30e82c | 96 | return ret; |
| 657ebfad | 97 | } |
| 4d30e82c | 98 | |
| 657ebfad PW |
99 | arch_initcall(omap3xxx_clk_arch_init); |
| 100 | ||
| 101 |