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usb: musb: mark ->set_clock deprecated
[deliverable/linux.git] / arch / arm / mach-omap2 / clock44xx_data.c
CommitLineData
972c5427
RN		 1/*
2 * OMAP4 Clock data
3 *
54776050
RN		 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
972c5427
RN		 6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
76cf5295
RN		 20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
972c5427
RN		 24 */
25
26#include <linux/kernel.h>
93340a22 27#include <linux/list.h>
972c5427 28#include <linux/clk.h>
972c5427
RN		 29#include <plat/clkdev_omap.h>
30
31#include "clock.h"
32#include "clock44xx.h"
33#include "cm.h"
34#include "cm-regbits-44xx.h"
35#include "prm.h"
36#include "prm-regbits-44xx.h"
4814ced5 37#include "control.h"
972c5427
RN		 38
39/* Root clocks */
40
41static struct clk extalt_clkin_ck = {
42 .name = "extalt_clkin_ck",
43 .rate = 59000000,
44 .ops = &clkops_null,
972c5427
RN		 45};
46
47static struct clk pad_clks_ck = {
48 .name = "pad_clks_ck",
49 .rate = 12000000,
50 .ops = &clkops_null,
972c5427
RN		 51};
52
53static struct clk pad_slimbus_core_clks_ck = {
54 .name = "pad_slimbus_core_clks_ck",
55 .rate = 12000000,
56 .ops = &clkops_null,
972c5427
RN		 57};
58
59static struct clk secure_32k_clk_src_ck = {
60 .name = "secure_32k_clk_src_ck",
61 .rate = 32768,
62 .ops = &clkops_null,
972c5427
RN		 63};
64
65static struct clk slimbus_clk = {
66 .name = "slimbus_clk",
67 .rate = 12000000,
68 .ops = &clkops_null,
972c5427
RN		 69};
70
71static struct clk sys_32k_ck = {
72 .name = "sys_32k_ck",
73 .rate = 32768,
74 .ops = &clkops_null,
972c5427
RN		 75};
76
77static struct clk virt_12000000_ck = {
78 .name = "virt_12000000_ck",
79 .ops = &clkops_null,
80 .rate = 12000000,
81};
82
83static struct clk virt_13000000_ck = {
84 .name = "virt_13000000_ck",
85 .ops = &clkops_null,
86 .rate = 13000000,
87};
88
89static struct clk virt_16800000_ck = {
90 .name = "virt_16800000_ck",
91 .ops = &clkops_null,
92 .rate = 16800000,
93};
94
95static struct clk virt_19200000_ck = {
96 .name = "virt_19200000_ck",
97 .ops = &clkops_null,
98 .rate = 19200000,
99};
100
101static struct clk virt_26000000_ck = {
102 .name = "virt_26000000_ck",
103 .ops = &clkops_null,
104 .rate = 26000000,
105};
106
107static struct clk virt_27000000_ck = {
108 .name = "virt_27000000_ck",
109 .ops = &clkops_null,
110 .rate = 27000000,
111};
112
113static struct clk virt_38400000_ck = {
114 .name = "virt_38400000_ck",
115 .ops = &clkops_null,
116 .rate = 38400000,
117};
118
119static const struct clksel_rate div_1_0_rates[] = {
120 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
121 { .div = 0 },
122};
123
124static const struct clksel_rate div_1_1_rates[] = {
125 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
126 { .div = 0 },
127};
128
129static const struct clksel_rate div_1_2_rates[] = {
130 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
131 { .div = 0 },
132};
133
134static const struct clksel_rate div_1_3_rates[] = {
135 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
136 { .div = 0 },
137};
138
139static const struct clksel_rate div_1_4_rates[] = {
140 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
141 { .div = 0 },
142};
143
144static const struct clksel_rate div_1_5_rates[] = {
145 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
146 { .div = 0 },
147};
148
149static const struct clksel_rate div_1_6_rates[] = {
150 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
151 { .div = 0 },
152};
153
154static const struct clksel_rate div_1_7_rates[] = {
155 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
156 { .div = 0 },
157};
158
159static const struct clksel sys_clkin_sel[] = {
160 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
161 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
162 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
163 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
164 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
165 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
166 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
167 { .parent = NULL },
168};
169
170static struct clk sys_clkin_ck = {
171 .name = "sys_clkin_ck",
172 .rate = 38400000,
173 .clksel = sys_clkin_sel,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
176 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
177 .ops = &clkops_null,
178 .recalc = &omap2_clksel_recalc,
972c5427
RN		 179};
180
76cf5295
RN		 181static struct clk tie_low_clock_ck = {
182 .name = "tie_low_clock_ck",
183 .rate = 0,
184 .ops = &clkops_null,
185};
186
972c5427
RN		 187static struct clk utmi_phy_clkout_ck = {
188 .name = "utmi_phy_clkout_ck",
76cf5295 189 .rate = 60000000,
972c5427 190 .ops = &clkops_null,
972c5427
RN		 191};
192
193static struct clk xclk60mhsp1_ck = {
194 .name = "xclk60mhsp1_ck",
76cf5295 195 .rate = 60000000,
972c5427 196 .ops = &clkops_null,
972c5427
RN		 197};
198
199static struct clk xclk60mhsp2_ck = {
200 .name = "xclk60mhsp2_ck",
76cf5295 201 .rate = 60000000,
972c5427 202 .ops = &clkops_null,
972c5427
RN		 203};
204
205static struct clk xclk60motg_ck = {
206 .name = "xclk60motg_ck",
207 .rate = 60000000,
208 .ops = &clkops_null,
972c5427
RN		 209};
210
211/* Module clocks and DPLL outputs */
212
76cf5295
RN		 213static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
214 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
215 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
972c5427
RN		 216 { .parent = NULL },
217};
218
76cf5295
RN		 219static struct clk abe_dpll_bypass_clk_mux_ck = {
220 .name = "abe_dpll_bypass_clk_mux_ck",
972c5427 221 .parent = &sys_clkin_ck,
972c5427 222 .ops = &clkops_null,
76cf5295 223 .recalc = &followparent_recalc,
972c5427
RN		 224};
225
226static struct clk abe_dpll_refclk_mux_ck = {
227 .name = "abe_dpll_refclk_mux_ck",
76cf5295
RN		 228 .parent = &sys_clkin_ck,
229 .clksel = abe_dpll_bypass_clk_mux_sel,
972c5427
RN		 230 .init = &omap2_init_clksel_parent,
231 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
232 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
233 .ops = &clkops_null,
234 .recalc = &omap2_clksel_recalc,
972c5427
RN		 235};
236
237/* DPLL_ABE */
238static struct dpll_data dpll_abe_dd = {
239 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
76cf5295 240 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
972c5427
RN		 241 .clk_ref = &abe_dpll_refclk_mux_ck,
242 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
243 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
244 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
245 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
246 .mult_mask = OMAP4430_DPLL_MULT_MASK,
247 .div1_mask = OMAP4430_DPLL_DIV_MASK,
248 .enable_mask = OMAP4430_DPLL_EN_MASK,
249 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
250 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
251 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
252 .max_divider = OMAP4430_MAX_DPLL_DIV,
253 .min_divider = 1,
254};
255
256
257static struct clk dpll_abe_ck = {
258 .name = "dpll_abe_ck",
259 .parent = &abe_dpll_refclk_mux_ck,
260 .dpll_data = &dpll_abe_dd,
911bd739 261 .init = &omap2_init_dpll_parent,
657ebfad 262 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 263 .recalc = &omap3_dpll_recalc,
264 .round_rate = &omap2_dpll_round_rate,
265 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 266};
267
268static struct clk dpll_abe_m2x2_ck = {
269 .name = "dpll_abe_m2x2_ck",
270 .parent = &dpll_abe_ck,
271 .ops = &clkops_null,
272 .recalc = &followparent_recalc,
972c5427
RN		 273};
274
275static struct clk abe_24m_fclk = {
276 .name = "abe_24m_fclk",
277 .parent = &dpll_abe_m2x2_ck,
278 .ops = &clkops_null,
279 .recalc = &followparent_recalc,
972c5427
RN		 280};
281
282static const struct clksel_rate div3_1to4_rates[] = {
283 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
284 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
285 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
286 { .div = 0 },
287};
288
289static const struct clksel abe_clk_div[] = {
290 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
291 { .parent = NULL },
292};
293
294static struct clk abe_clk = {
295 .name = "abe_clk",
296 .parent = &dpll_abe_m2x2_ck,
297 .clksel = abe_clk_div,
298 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
299 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
300 .ops = &clkops_null,
301 .recalc = &omap2_clksel_recalc,
302 .round_rate = &omap2_clksel_round_rate,
303 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 304};
305
76cf5295
RN		 306static const struct clksel_rate div2_1to2_rates[] = {
307 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
308 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
309 { .div = 0 },
310};
311
972c5427
RN		 312static const struct clksel aess_fclk_div[] = {
313 { .parent = &abe_clk, .rates = div2_1to2_rates },
314 { .parent = NULL },
315};
316
317static struct clk aess_fclk = {
318 .name = "aess_fclk",
319 .parent = &abe_clk,
320 .clksel = aess_fclk_div,
321 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
322 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
323 .ops = &clkops_null,
324 .recalc = &omap2_clksel_recalc,
325 .round_rate = &omap2_clksel_round_rate,
326 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 327};
328
329static const struct clksel_rate div31_1to31_rates[] = {
ecbb0659
RN		 330 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
331 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
332 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
333 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
334 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
335 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
336 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
337 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
338 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
339 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
340 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
341 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
342 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
343 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
344 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
345 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
346 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
347 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
348 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
349 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
350 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
351 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
352 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
353 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
354 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
355 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
356 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
357 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
358 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
359 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
360 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
972c5427
RN		 361 { .div = 0 },
362};
363
364static const struct clksel dpll_abe_m3_div[] = {
365 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
366 { .parent = NULL },
367};
368
369static struct clk dpll_abe_m3_ck = {
370 .name = "dpll_abe_m3_ck",
371 .parent = &dpll_abe_ck,
372 .clksel = dpll_abe_m3_div,
373 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
374 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
375 .ops = &clkops_null,
376 .recalc = &omap2_clksel_recalc,
377 .round_rate = &omap2_clksel_round_rate,
378 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 379};
380
381static const struct clksel core_hsd_byp_clk_mux_sel[] = {
76cf5295 382 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
972c5427
RN		 383 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
384 { .parent = NULL },
385};
386
387static struct clk core_hsd_byp_clk_mux_ck = {
388 .name = "core_hsd_byp_clk_mux_ck",
76cf5295 389 .parent = &sys_clkin_ck,
972c5427
RN		 390 .clksel = core_hsd_byp_clk_mux_sel,
391 .init = &omap2_init_clksel_parent,
392 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
393 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
394 .ops = &clkops_null,
395 .recalc = &omap2_clksel_recalc,
972c5427
RN		 396};
397
398/* DPLL_CORE */
399static struct dpll_data dpll_core_dd = {
400 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
401 .clk_bypass = &core_hsd_byp_clk_mux_ck,
76cf5295 402 .clk_ref = &sys_clkin_ck,
972c5427
RN		 403 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
404 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
405 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
406 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
407 .mult_mask = OMAP4430_DPLL_MULT_MASK,
408 .div1_mask = OMAP4430_DPLL_DIV_MASK,
409 .enable_mask = OMAP4430_DPLL_EN_MASK,
410 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
411 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
412 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
413 .max_divider = OMAP4430_MAX_DPLL_DIV,
414 .min_divider = 1,
415};
416
417
418static struct clk dpll_core_ck = {
419 .name = "dpll_core_ck",
76cf5295 420 .parent = &sys_clkin_ck,
972c5427 421 .dpll_data = &dpll_core_dd,
911bd739 422 .init = &omap2_init_dpll_parent,
972c5427
RN		 423 .ops = &clkops_null,
424 .recalc = &omap3_dpll_recalc,
972c5427
RN		 425};
426
427static const struct clksel dpll_core_m6_div[] = {
428 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
429 { .parent = NULL },
430};
431
432static struct clk dpll_core_m6_ck = {
433 .name = "dpll_core_m6_ck",
434 .parent = &dpll_core_ck,
435 .clksel = dpll_core_m6_div,
436 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
437 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
438 .ops = &clkops_null,
439 .recalc = &omap2_clksel_recalc,
440 .round_rate = &omap2_clksel_round_rate,
441 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 442};
443
444static const struct clksel dbgclk_mux_sel[] = {
445 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
446 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
447 { .parent = NULL },
448};
449
450static struct clk dbgclk_mux_ck = {
451 .name = "dbgclk_mux_ck",
452 .parent = &sys_clkin_ck,
453 .ops = &clkops_null,
454 .recalc = &followparent_recalc,
972c5427
RN		 455};
456
457static struct clk dpll_core_m2_ck = {
458 .name = "dpll_core_m2_ck",
459 .parent = &dpll_core_ck,
460 .clksel = dpll_core_m6_div,
461 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
462 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
463 .ops = &clkops_null,
464 .recalc = &omap2_clksel_recalc,
465 .round_rate = &omap2_clksel_round_rate,
466 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 467};
468
469static struct clk ddrphy_ck = {
470 .name = "ddrphy_ck",
471 .parent = &dpll_core_m2_ck,
472 .ops = &clkops_null,
473 .recalc = &followparent_recalc,
972c5427
RN		 474};
475
476static struct clk dpll_core_m5_ck = {
477 .name = "dpll_core_m5_ck",
478 .parent = &dpll_core_ck,
479 .clksel = dpll_core_m6_div,
480 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
481 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
482 .ops = &clkops_null,
483 .recalc = &omap2_clksel_recalc,
484 .round_rate = &omap2_clksel_round_rate,
485 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 486};
487
488static const struct clksel div_core_div[] = {
489 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
490 { .parent = NULL },
491};
492
493static struct clk div_core_ck = {
494 .name = "div_core_ck",
495 .parent = &dpll_core_m5_ck,
496 .clksel = div_core_div,
497 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
498 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
499 .ops = &clkops_null,
500 .recalc = &omap2_clksel_recalc,
501 .round_rate = &omap2_clksel_round_rate,
502 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 503};
504
505static const struct clksel_rate div4_1to8_rates[] = {
506 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
507 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
508 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
509 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
510 { .div = 0 },
511};
512
513static const struct clksel div_iva_hs_clk_div[] = {
514 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
515 { .parent = NULL },
516};
517
518static struct clk div_iva_hs_clk = {
519 .name = "div_iva_hs_clk",
520 .parent = &dpll_core_m5_ck,
521 .clksel = div_iva_hs_clk_div,
522 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
523 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
524 .ops = &clkops_null,
525 .recalc = &omap2_clksel_recalc,
526 .round_rate = &omap2_clksel_round_rate,
527 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 528};
529
530static struct clk div_mpu_hs_clk = {
531 .name = "div_mpu_hs_clk",
532 .parent = &dpll_core_m5_ck,
533 .clksel = div_iva_hs_clk_div,
534 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
535 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
536 .ops = &clkops_null,
537 .recalc = &omap2_clksel_recalc,
538 .round_rate = &omap2_clksel_round_rate,
539 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 540};
541
542static struct clk dpll_core_m4_ck = {
543 .name = "dpll_core_m4_ck",
544 .parent = &dpll_core_ck,
545 .clksel = dpll_core_m6_div,
546 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
547 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
548 .ops = &clkops_null,
549 .recalc = &omap2_clksel_recalc,
550 .round_rate = &omap2_clksel_round_rate,
551 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 552};
553
554static struct clk dll_clk_div_ck = {
555 .name = "dll_clk_div_ck",
556 .parent = &dpll_core_m4_ck,
557 .ops = &clkops_null,
558 .recalc = &followparent_recalc,
972c5427
RN		 559};
560
561static struct clk dpll_abe_m2_ck = {
562 .name = "dpll_abe_m2_ck",
563 .parent = &dpll_abe_ck,
564 .clksel = dpll_abe_m3_div,
565 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
566 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
567 .ops = &clkops_null,
568 .recalc = &omap2_clksel_recalc,
569 .round_rate = &omap2_clksel_round_rate,
570 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 571};
572
573static struct clk dpll_core_m3_ck = {
574 .name = "dpll_core_m3_ck",
575 .parent = &dpll_core_ck,
576 .clksel = dpll_core_m6_div,
577 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
578 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
579 .ops = &clkops_null,
580 .recalc = &omap2_clksel_recalc,
581 .round_rate = &omap2_clksel_round_rate,
582 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 583};
584
585static struct clk dpll_core_m7_ck = {
586 .name = "dpll_core_m7_ck",
587 .parent = &dpll_core_ck,
588 .clksel = dpll_core_m6_div,
589 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
590 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
591 .ops = &clkops_null,
592 .recalc = &omap2_clksel_recalc,
593 .round_rate = &omap2_clksel_round_rate,
594 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 595};
596
597static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
76cf5295 598 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
972c5427
RN		 599 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
600 { .parent = NULL },
601};
602
603static struct clk iva_hsd_byp_clk_mux_ck = {
604 .name = "iva_hsd_byp_clk_mux_ck",
76cf5295 605 .parent = &sys_clkin_ck,
972c5427
RN		 606 .ops = &clkops_null,
607 .recalc = &followparent_recalc,
972c5427
RN		 608};
609
610/* DPLL_IVA */
611static struct dpll_data dpll_iva_dd = {
612 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
613 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
76cf5295 614 .clk_ref = &sys_clkin_ck,
972c5427
RN		 615 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
616 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
617 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
618 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
619 .mult_mask = OMAP4430_DPLL_MULT_MASK,
620 .div1_mask = OMAP4430_DPLL_DIV_MASK,
621 .enable_mask = OMAP4430_DPLL_EN_MASK,
622 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
623 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
624 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
625 .max_divider = OMAP4430_MAX_DPLL_DIV,
626 .min_divider = 1,
627};
628
629
630static struct clk dpll_iva_ck = {
631 .name = "dpll_iva_ck",
76cf5295 632 .parent = &sys_clkin_ck,
972c5427 633 .dpll_data = &dpll_iva_dd,
911bd739 634 .init = &omap2_init_dpll_parent,
657ebfad 635 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 636 .recalc = &omap3_dpll_recalc,
637 .round_rate = &omap2_dpll_round_rate,
638 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 639};
640
641static const struct clksel dpll_iva_m4_div[] = {
642 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
643 { .parent = NULL },
644};
645
646static struct clk dpll_iva_m4_ck = {
647 .name = "dpll_iva_m4_ck",
648 .parent = &dpll_iva_ck,
649 .clksel = dpll_iva_m4_div,
650 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
651 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
652 .ops = &clkops_null,
653 .recalc = &omap2_clksel_recalc,
654 .round_rate = &omap2_clksel_round_rate,
655 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 656};
657
658static struct clk dpll_iva_m5_ck = {
659 .name = "dpll_iva_m5_ck",
660 .parent = &dpll_iva_ck,
661 .clksel = dpll_iva_m4_div,
662 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
663 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
664 .ops = &clkops_null,
665 .recalc = &omap2_clksel_recalc,
666 .round_rate = &omap2_clksel_round_rate,
667 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 668};
669
670/* DPLL_MPU */
671static struct dpll_data dpll_mpu_dd = {
672 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
673 .clk_bypass = &div_mpu_hs_clk,
76cf5295 674 .clk_ref = &sys_clkin_ck,
972c5427
RN		 675 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
676 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
677 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
678 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
679 .mult_mask = OMAP4430_DPLL_MULT_MASK,
680 .div1_mask = OMAP4430_DPLL_DIV_MASK,
681 .enable_mask = OMAP4430_DPLL_EN_MASK,
682 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
683 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
684 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
685 .max_divider = OMAP4430_MAX_DPLL_DIV,
686 .min_divider = 1,
687};
688
689
690static struct clk dpll_mpu_ck = {
691 .name = "dpll_mpu_ck",
76cf5295 692 .parent = &sys_clkin_ck,
972c5427 693 .dpll_data = &dpll_mpu_dd,
911bd739 694 .init = &omap2_init_dpll_parent,
657ebfad 695 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 696 .recalc = &omap3_dpll_recalc,
697 .round_rate = &omap2_dpll_round_rate,
698 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 699};
700
701static const struct clksel dpll_mpu_m2_div[] = {
702 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
703 { .parent = NULL },
704};
705
706static struct clk dpll_mpu_m2_ck = {
707 .name = "dpll_mpu_m2_ck",
708 .parent = &dpll_mpu_ck,
709 .clksel = dpll_mpu_m2_div,
710 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
711 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
712 .ops = &clkops_null,
713 .recalc = &omap2_clksel_recalc,
714 .round_rate = &omap2_clksel_round_rate,
715 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 716};
717
718static struct clk per_hs_clk_div_ck = {
719 .name = "per_hs_clk_div_ck",
720 .parent = &dpll_abe_m3_ck,
721 .ops = &clkops_null,
722 .recalc = &followparent_recalc,
972c5427
RN		 723};
724
725static const struct clksel per_hsd_byp_clk_mux_sel[] = {
76cf5295 726 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
972c5427
RN		 727 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
728 { .parent = NULL },
729};
730
731static struct clk per_hsd_byp_clk_mux_ck = {
732 .name = "per_hsd_byp_clk_mux_ck",
76cf5295 733 .parent = &sys_clkin_ck,
972c5427
RN		 734 .clksel = per_hsd_byp_clk_mux_sel,
735 .init = &omap2_init_clksel_parent,
736 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
737 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
738 .ops = &clkops_null,
739 .recalc = &omap2_clksel_recalc,
972c5427
RN		 740};
741
742/* DPLL_PER */
743static struct dpll_data dpll_per_dd = {
744 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
745 .clk_bypass = &per_hsd_byp_clk_mux_ck,
76cf5295 746 .clk_ref = &sys_clkin_ck,
972c5427
RN		 747 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
748 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
749 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
750 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
751 .mult_mask = OMAP4430_DPLL_MULT_MASK,
752 .div1_mask = OMAP4430_DPLL_DIV_MASK,
753 .enable_mask = OMAP4430_DPLL_EN_MASK,
754 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
755 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
756 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
757 .max_divider = OMAP4430_MAX_DPLL_DIV,
758 .min_divider = 1,
759};
760
761
762static struct clk dpll_per_ck = {
763 .name = "dpll_per_ck",
76cf5295 764 .parent = &sys_clkin_ck,
972c5427 765 .dpll_data = &dpll_per_dd,
911bd739 766 .init = &omap2_init_dpll_parent,
657ebfad 767 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 768 .recalc = &omap3_dpll_recalc,
769 .round_rate = &omap2_dpll_round_rate,
770 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 771};
772
773static const struct clksel dpll_per_m2_div[] = {
774 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
775 { .parent = NULL },
776};
777
778static struct clk dpll_per_m2_ck = {
779 .name = "dpll_per_m2_ck",
780 .parent = &dpll_per_ck,
781 .clksel = dpll_per_m2_div,
782 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
783 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
784 .ops = &clkops_null,
785 .recalc = &omap2_clksel_recalc,
786 .round_rate = &omap2_clksel_round_rate,
787 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 788};
789
790static struct clk dpll_per_m2x2_ck = {
791 .name = "dpll_per_m2x2_ck",
792 .parent = &dpll_per_ck,
793 .ops = &clkops_null,
794 .recalc = &followparent_recalc,
972c5427
RN		 795};
796
797static struct clk dpll_per_m3_ck = {
798 .name = "dpll_per_m3_ck",
799 .parent = &dpll_per_ck,
800 .clksel = dpll_per_m2_div,
801 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
802 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
803 .ops = &clkops_null,
804 .recalc = &omap2_clksel_recalc,
805 .round_rate = &omap2_clksel_round_rate,
806 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 807};
808
809static struct clk dpll_per_m4_ck = {
810 .name = "dpll_per_m4_ck",
811 .parent = &dpll_per_ck,
812 .clksel = dpll_per_m2_div,
813 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
814 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
815 .ops = &clkops_null,
816 .recalc = &omap2_clksel_recalc,
817 .round_rate = &omap2_clksel_round_rate,
818 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 819};
820
821static struct clk dpll_per_m5_ck = {
822 .name = "dpll_per_m5_ck",
823 .parent = &dpll_per_ck,
824 .clksel = dpll_per_m2_div,
825 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
826 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
827 .ops = &clkops_null,
828 .recalc = &omap2_clksel_recalc,
829 .round_rate = &omap2_clksel_round_rate,
830 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 831};
832
833static struct clk dpll_per_m6_ck = {
834 .name = "dpll_per_m6_ck",
835 .parent = &dpll_per_ck,
836 .clksel = dpll_per_m2_div,
837 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
838 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
839 .ops = &clkops_null,
840 .recalc = &omap2_clksel_recalc,
841 .round_rate = &omap2_clksel_round_rate,
842 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 843};
844
845static struct clk dpll_per_m7_ck = {
846 .name = "dpll_per_m7_ck",
847 .parent = &dpll_per_ck,
848 .clksel = dpll_per_m2_div,
849 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
850 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
851 .ops = &clkops_null,
852 .recalc = &omap2_clksel_recalc,
853 .round_rate = &omap2_clksel_round_rate,
854 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 855};
856
857/* DPLL_UNIPRO */
858static struct dpll_data dpll_unipro_dd = {
859 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
76cf5295
RN		 860 .clk_bypass = &sys_clkin_ck,
861 .clk_ref = &sys_clkin_ck,
972c5427
RN		 862 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
863 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
864 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
865 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
866 .mult_mask = OMAP4430_DPLL_MULT_MASK,
867 .div1_mask = OMAP4430_DPLL_DIV_MASK,
868 .enable_mask = OMAP4430_DPLL_EN_MASK,
869 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
870 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
871 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
872 .max_divider = OMAP4430_MAX_DPLL_DIV,
873 .min_divider = 1,
874};
875
876
877static struct clk dpll_unipro_ck = {
878 .name = "dpll_unipro_ck",
76cf5295 879 .parent = &sys_clkin_ck,
972c5427 880 .dpll_data = &dpll_unipro_dd,
911bd739 881 .init = &omap2_init_dpll_parent,
657ebfad 882 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 883 .recalc = &omap3_dpll_recalc,
884 .round_rate = &omap2_dpll_round_rate,
885 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 886};
887
888static const struct clksel dpll_unipro_m2x2_div[] = {
889 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
890 { .parent = NULL },
891};
892
893static struct clk dpll_unipro_m2x2_ck = {
894 .name = "dpll_unipro_m2x2_ck",
895 .parent = &dpll_unipro_ck,
896 .clksel = dpll_unipro_m2x2_div,
897 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
898 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
899 .ops = &clkops_null,
900 .recalc = &omap2_clksel_recalc,
901 .round_rate = &omap2_clksel_round_rate,
902 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 903};
904
905static struct clk usb_hs_clk_div_ck = {
906 .name = "usb_hs_clk_div_ck",
907 .parent = &dpll_abe_m3_ck,
908 .ops = &clkops_null,
909 .recalc = &followparent_recalc,
972c5427
RN		 910};
911
912/* DPLL_USB */
913static struct dpll_data dpll_usb_dd = {
914 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
915 .clk_bypass = &usb_hs_clk_div_ck,
0e433271 916 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
76cf5295 917 .clk_ref = &sys_clkin_ck,
972c5427
RN		 918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
921 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
922 .mult_mask = OMAP4430_DPLL_MULT_MASK,
923 .div1_mask = OMAP4430_DPLL_DIV_MASK,
924 .enable_mask = OMAP4430_DPLL_EN_MASK,
925 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
926 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1,
930};
931
932
933static struct clk dpll_usb_ck = {
934 .name = "dpll_usb_ck",
76cf5295 935 .parent = &sys_clkin_ck,
972c5427 936 .dpll_data = &dpll_usb_dd,
911bd739 937 .init = &omap2_init_dpll_parent,
657ebfad 938 .ops = &clkops_omap3_noncore_dpll_ops,
972c5427
RN		 939 .recalc = &omap3_dpll_recalc,
940 .round_rate = &omap2_dpll_round_rate,
941 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 942};
943
944static struct clk dpll_usb_clkdcoldo_ck = {
945 .name = "dpll_usb_clkdcoldo_ck",
946 .parent = &dpll_usb_ck,
947 .ops = &clkops_null,
948 .recalc = &followparent_recalc,
972c5427
RN		 949};
950
951static const struct clksel dpll_usb_m2_div[] = {
952 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
953 { .parent = NULL },
954};
955
956static struct clk dpll_usb_m2_ck = {
957 .name = "dpll_usb_m2_ck",
958 .parent = &dpll_usb_ck,
959 .clksel = dpll_usb_m2_div,
960 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
961 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
962 .ops = &clkops_null,
963 .recalc = &omap2_clksel_recalc,
964 .round_rate = &omap2_clksel_round_rate,
965 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 966};
967
968static const struct clksel ducati_clk_mux_sel[] = {
969 { .parent = &div_core_ck, .rates = div_1_0_rates },
970 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
971 { .parent = NULL },
972};
973
974static struct clk ducati_clk_mux_ck = {
975 .name = "ducati_clk_mux_ck",
976 .parent = &div_core_ck,
977 .clksel = ducati_clk_mux_sel,
978 .init = &omap2_init_clksel_parent,
979 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
980 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
981 .ops = &clkops_null,
982 .recalc = &omap2_clksel_recalc,
972c5427
RN		 983};
984
985static struct clk func_12m_fclk = {
986 .name = "func_12m_fclk",
987 .parent = &dpll_per_m2x2_ck,
988 .ops = &clkops_null,
989 .recalc = &followparent_recalc,
972c5427
RN		 990};
991
992static struct clk func_24m_clk = {
993 .name = "func_24m_clk",
994 .parent = &dpll_per_m2_ck,
995 .ops = &clkops_null,
996 .recalc = &followparent_recalc,
972c5427
RN		 997};
998
999static struct clk func_24mc_fclk = {
1000 .name = "func_24mc_fclk",
1001 .parent = &dpll_per_m2x2_ck,
1002 .ops = &clkops_null,
1003 .recalc = &followparent_recalc,
972c5427
RN		 1004};
1005
1006static const struct clksel_rate div2_4to8_rates[] = {
1007 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1008 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1009 { .div = 0 },
1010};
1011
1012static const struct clksel func_48m_fclk_div[] = {
1013 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1014 { .parent = NULL },
1015};
1016
1017static struct clk func_48m_fclk = {
1018 .name = "func_48m_fclk",
1019 .parent = &dpll_per_m2x2_ck,
1020 .clksel = func_48m_fclk_div,
1021 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1022 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1023 .ops = &clkops_null,
1024 .recalc = &omap2_clksel_recalc,
1025 .round_rate = &omap2_clksel_round_rate,
1026 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1027};
1028
1029static struct clk func_48mc_fclk = {
1030 .name = "func_48mc_fclk",
1031 .parent = &dpll_per_m2x2_ck,
1032 .ops = &clkops_null,
1033 .recalc = &followparent_recalc,
972c5427
RN		 1034};
1035
1036static const struct clksel_rate div2_2to4_rates[] = {
1037 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1038 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1039 { .div = 0 },
1040};
1041
1042static const struct clksel func_64m_fclk_div[] = {
1043 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1044 { .parent = NULL },
1045};
1046
1047static struct clk func_64m_fclk = {
1048 .name = "func_64m_fclk",
1049 .parent = &dpll_per_m4_ck,
1050 .clksel = func_64m_fclk_div,
1051 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1052 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1053 .ops = &clkops_null,
1054 .recalc = &omap2_clksel_recalc,
1055 .round_rate = &omap2_clksel_round_rate,
1056 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1057};
1058
1059static const struct clksel func_96m_fclk_div[] = {
1060 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1061 { .parent = NULL },
1062};
1063
1064static struct clk func_96m_fclk = {
1065 .name = "func_96m_fclk",
1066 .parent = &dpll_per_m2x2_ck,
1067 .clksel = func_96m_fclk_div,
1068 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1069 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1070 .ops = &clkops_null,
1071 .recalc = &omap2_clksel_recalc,
1072 .round_rate = &omap2_clksel_round_rate,
1073 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1074};
1075
1076static const struct clksel hsmmc6_fclk_sel[] = {
1077 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1078 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1079 { .parent = NULL },
1080};
1081
1082static struct clk hsmmc6_fclk = {
1083 .name = "hsmmc6_fclk",
1084 .parent = &func_64m_fclk,
1085 .ops = &clkops_null,
1086 .recalc = &followparent_recalc,
972c5427
RN		 1087};
1088
1089static const struct clksel_rate div2_1to8_rates[] = {
1090 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1091 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1092 { .div = 0 },
1093};
1094
1095static const struct clksel init_60m_fclk_div[] = {
1096 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1097 { .parent = NULL },
1098};
1099
1100static struct clk init_60m_fclk = {
1101 .name = "init_60m_fclk",
1102 .parent = &dpll_usb_m2_ck,
1103 .clksel = init_60m_fclk_div,
1104 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1105 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1106 .ops = &clkops_null,
1107 .recalc = &omap2_clksel_recalc,
1108 .round_rate = &omap2_clksel_round_rate,
1109 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1110};
1111
1112static const struct clksel l3_div_div[] = {
1113 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1114 { .parent = NULL },
1115};
1116
1117static struct clk l3_div_ck = {
1118 .name = "l3_div_ck",
1119 .parent = &div_core_ck,
1120 .clksel = l3_div_div,
1121 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1122 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1123 .ops = &clkops_null,
1124 .recalc = &omap2_clksel_recalc,
1125 .round_rate = &omap2_clksel_round_rate,
1126 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1127};
1128
1129static const struct clksel l4_div_div[] = {
1130 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1131 { .parent = NULL },
1132};
1133
1134static struct clk l4_div_ck = {
1135 .name = "l4_div_ck",
1136 .parent = &l3_div_ck,
1137 .clksel = l4_div_div,
1138 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1139 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1140 .ops = &clkops_null,
1141 .recalc = &omap2_clksel_recalc,
1142 .round_rate = &omap2_clksel_round_rate,
1143 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1144};
1145
1146static struct clk lp_clk_div_ck = {
1147 .name = "lp_clk_div_ck",
1148 .parent = &dpll_abe_m2x2_ck,
1149 .ops = &clkops_null,
1150 .recalc = &followparent_recalc,
972c5427
RN		 1151};
1152
1153static const struct clksel l4_wkup_clk_mux_sel[] = {
1154 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1155 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1156 { .parent = NULL },
1157};
1158
1159static struct clk l4_wkup_clk_mux_ck = {
1160 .name = "l4_wkup_clk_mux_ck",
1161 .parent = &sys_clkin_ck,
1162 .clksel = l4_wkup_clk_mux_sel,
1163 .init = &omap2_init_clksel_parent,
1164 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1165 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1166 .ops = &clkops_null,
1167 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1168};
1169
1170static const struct clksel per_abe_nc_fclk_div[] = {
1171 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1172 { .parent = NULL },
1173};
1174
1175static struct clk per_abe_nc_fclk = {
1176 .name = "per_abe_nc_fclk",
1177 .parent = &dpll_abe_m2_ck,
1178 .clksel = per_abe_nc_fclk_div,
1179 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1180 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1181 .ops = &clkops_null,
1182 .recalc = &omap2_clksel_recalc,
1183 .round_rate = &omap2_clksel_round_rate,
1184 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1185};
1186
1187static const struct clksel mcasp2_fclk_sel[] = {
1188 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1189 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1190 { .parent = NULL },
1191};
1192
1193static struct clk mcasp2_fclk = {
1194 .name = "mcasp2_fclk",
1195 .parent = &func_96m_fclk,
1196 .ops = &clkops_null,
1197 .recalc = &followparent_recalc,
972c5427
RN		 1198};
1199
1200static struct clk mcasp3_fclk = {
1201 .name = "mcasp3_fclk",
1202 .parent = &func_96m_fclk,
1203 .ops = &clkops_null,
1204 .recalc = &followparent_recalc,
972c5427
RN		 1205};
1206
1207static struct clk ocp_abe_iclk = {
1208 .name = "ocp_abe_iclk",
1209 .parent = &aess_fclk,
1210 .ops = &clkops_null,
1211 .recalc = &followparent_recalc,
972c5427
RN		 1212};
1213
1214static struct clk per_abe_24m_fclk = {
1215 .name = "per_abe_24m_fclk",
1216 .parent = &dpll_abe_m2_ck,
1217 .ops = &clkops_null,
1218 .recalc = &followparent_recalc,
972c5427
RN		 1219};
1220
1221static const struct clksel pmd_stm_clock_mux_sel[] = {
1222 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1223 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
76cf5295 1224 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
972c5427
RN		 1225 { .parent = NULL },
1226};
1227
1228static struct clk pmd_stm_clock_mux_ck = {
1229 .name = "pmd_stm_clock_mux_ck",
1230 .parent = &sys_clkin_ck,
1231 .ops = &clkops_null,
1232 .recalc = &followparent_recalc,
972c5427
RN		 1233};
1234
1235static struct clk pmd_trace_clk_mux_ck = {
1236 .name = "pmd_trace_clk_mux_ck",
1237 .parent = &sys_clkin_ck,
1238 .ops = &clkops_null,
1239 .recalc = &followparent_recalc,
972c5427
RN		 1240};
1241
76cf5295
RN		 1242static const struct clksel syc_clk_div_div[] = {
1243 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1244 { .parent = NULL },
1245};
1246
972c5427
RN		 1247static struct clk syc_clk_div_ck = {
1248 .name = "syc_clk_div_ck",
1249 .parent = &sys_clkin_ck,
76cf5295 1250 .clksel = syc_clk_div_div,
972c5427
RN		 1251 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1252 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1253 .ops = &clkops_null,
1254 .recalc = &omap2_clksel_recalc,
1255 .round_rate = &omap2_clksel_round_rate,
1256 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1257};
1258
1259/* Leaf clocks controlled by modules */
1260
54776050
RN		 1261static struct clk aes1_fck = {
1262 .name = "aes1_fck",
972c5427
RN		 1263 .ops = &clkops_omap2_dflt,
1264 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1265 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1266 .clkdm_name = "l4_secure_clkdm",
1267 .parent = &l3_div_ck,
1268 .recalc = &followparent_recalc,
1269};
1270
54776050
RN		 1271static struct clk aes2_fck = {
1272 .name = "aes2_fck",
972c5427
RN		 1273 .ops = &clkops_omap2_dflt,
1274 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1275 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1276 .clkdm_name = "l4_secure_clkdm",
1277 .parent = &l3_div_ck,
1278 .recalc = &followparent_recalc,
1279};
1280
54776050
RN		 1281static struct clk aess_fck = {
1282 .name = "aess_fck",
972c5427
RN		 1283 .ops = &clkops_omap2_dflt,
1284 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1285 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1286 .clkdm_name = "abe_clkdm",
1287 .parent = &aess_fclk,
1288 .recalc = &followparent_recalc,
1289};
1290
1c03f42f
BC		 1291static struct clk bandgap_fclk = {
1292 .name = "bandgap_fclk",
1293 .ops = &clkops_omap2_dflt,
1294 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1295 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1296 .clkdm_name = "l4_wkup_clkdm",
1297 .parent = &sys_32k_ck,
1298 .recalc = &followparent_recalc,
1299};
1300
54776050
RN		 1301static struct clk des3des_fck = {
1302 .name = "des3des_fck",
972c5427
RN		 1303 .ops = &clkops_omap2_dflt,
1304 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1305 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1306 .clkdm_name = "l4_secure_clkdm",
1307 .parent = &l4_div_ck,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static const struct clksel dmic_sync_mux_sel[] = {
1312 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1313 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1314 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1315 { .parent = NULL },
1316};
1317
1318static struct clk dmic_sync_mux_ck = {
1319 .name = "dmic_sync_mux_ck",
1320 .parent = &abe_24m_fclk,
1321 .clksel = dmic_sync_mux_sel,
1322 .init = &omap2_init_clksel_parent,
1323 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1324 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1325 .ops = &clkops_null,
1326 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1327};
1328
1329static const struct clksel func_dmic_abe_gfclk_sel[] = {
1330 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1331 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1332 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1333 { .parent = NULL },
1334};
1335
54776050
RN		 1336/* Merged func_dmic_abe_gfclk into dmic */
1337static struct clk dmic_fck = {
1338 .name = "dmic_fck",
972c5427
RN		 1339 .parent = &dmic_sync_mux_ck,
1340 .clksel = func_dmic_abe_gfclk_sel,
1341 .init = &omap2_init_clksel_parent,
1342 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1343 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1344 .ops = &clkops_omap2_dflt,
1345 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1346 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1347 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1348 .clkdm_name = "abe_clkdm",
1349};
1350
0e433271
BC		 1351static struct clk dsp_fck = {
1352 .name = "dsp_fck",
1353 .ops = &clkops_omap2_dflt,
1354 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1355 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1356 .clkdm_name = "tesla_clkdm",
1357 .parent = &dpll_iva_m4_ck,
1358 .recalc = &followparent_recalc,
1359};
1360
1c03f42f
BC		 1361static struct clk dss_sys_clk = {
1362 .name = "dss_sys_clk",
1363 .ops = &clkops_omap2_dflt,
1364 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1365 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1366 .clkdm_name = "l3_dss_clkdm",
1367 .parent = &syc_clk_div_ck,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk dss_tv_clk = {
1372 .name = "dss_tv_clk",
1373 .ops = &clkops_omap2_dflt,
1374 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1375 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1376 .clkdm_name = "l3_dss_clkdm",
1377 .parent = &extalt_clkin_ck,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk dss_dss_clk = {
1382 .name = "dss_dss_clk",
1383 .ops = &clkops_omap2_dflt,
1384 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1386 .clkdm_name = "l3_dss_clkdm",
1387 .parent = &dpll_per_m5_ck,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk dss_48mhz_clk = {
1392 .name = "dss_48mhz_clk",
1393 .ops = &clkops_omap2_dflt,
1394 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1395 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1396 .clkdm_name = "l3_dss_clkdm",
1397 .parent = &func_48mc_fclk,
1398 .recalc = &followparent_recalc,
1399};
1400
54776050
RN		 1401static struct clk dss_fck = {
1402 .name = "dss_fck",
972c5427
RN		 1403 .ops = &clkops_omap2_dflt,
1404 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1405 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1406 .clkdm_name = "l3_dss_clkdm",
1407 .parent = &l3_div_ck,
1408 .recalc = &followparent_recalc,
1409};
1410
0e433271
BC		 1411static struct clk efuse_ctrl_cust_fck = {
1412 .name = "efuse_ctrl_cust_fck",
972c5427 1413 .ops = &clkops_omap2_dflt,
0e433271
BC		 1414 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1416 .clkdm_name = "l4_cefuse_clkdm",
1417 .parent = &sys_clkin_ck,
972c5427
RN		 1418 .recalc = &followparent_recalc,
1419};
1420
0e433271
BC		 1421static struct clk emif1_fck = {
1422 .name = "emif1_fck",
972c5427
RN		 1423 .ops = &clkops_omap2_dflt,
1424 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1425 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
090830b4 1426 .flags = ENABLE_ON_INIT,
972c5427
RN		 1427 .clkdm_name = "l3_emif_clkdm",
1428 .parent = &ddrphy_ck,
1429 .recalc = &followparent_recalc,
1430};
1431
0e433271
BC		 1432static struct clk emif2_fck = {
1433 .name = "emif2_fck",
972c5427
RN		 1434 .ops = &clkops_omap2_dflt,
1435 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1436 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
090830b4 1437 .flags = ENABLE_ON_INIT,
972c5427
RN		 1438 .clkdm_name = "l3_emif_clkdm",
1439 .parent = &ddrphy_ck,
1440 .recalc = &followparent_recalc,
1441};
1442
1443static const struct clksel fdif_fclk_div[] = {
1444 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1445 { .parent = NULL },
1446};
1447
54776050
RN		 1448/* Merged fdif_fclk into fdif */
1449static struct clk fdif_fck = {
1450 .name = "fdif_fck",
972c5427
RN		 1451 .parent = &dpll_per_m4_ck,
1452 .clksel = fdif_fclk_div,
1453 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1454 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1455 .ops = &clkops_omap2_dflt,
1456 .recalc = &omap2_clksel_recalc,
1457 .round_rate = &omap2_clksel_round_rate,
1458 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1459 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1460 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1461 .clkdm_name = "iss_clkdm",
1462};
1463
0e433271
BC		 1464static struct clk fpka_fck = {
1465 .name = "fpka_fck",
972c5427 1466 .ops = &clkops_omap2_dflt,
0e433271 1467 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
972c5427 1468 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
0e433271
BC		 1469 .clkdm_name = "l4_secure_clkdm",
1470 .parent = &l4_div_ck,
1471 .recalc = &followparent_recalc,
972c5427
RN		 1472};
1473
1c03f42f
BC		 1474static struct clk gpio1_dbclk = {
1475 .name = "gpio1_dbclk",
1476 .ops = &clkops_omap2_dflt,
1477 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1478 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1479 .clkdm_name = "l4_wkup_clkdm",
1480 .parent = &sys_32k_ck,
1481 .recalc = &followparent_recalc,
1482};
1483
54776050
RN		 1484static struct clk gpio1_ick = {
1485 .name = "gpio1_ick",
972c5427
RN		 1486 .ops = &clkops_omap2_dflt,
1487 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1488 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1489 .clkdm_name = "l4_wkup_clkdm",
1490 .parent = &l4_wkup_clk_mux_ck,
1491 .recalc = &followparent_recalc,
1492};
1493
1c03f42f
BC		 1494static struct clk gpio2_dbclk = {
1495 .name = "gpio2_dbclk",
1496 .ops = &clkops_omap2_dflt,
1497 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1498 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1499 .clkdm_name = "l4_per_clkdm",
1500 .parent = &sys_32k_ck,
1501 .recalc = &followparent_recalc,
1502};
1503
54776050
RN		 1504static struct clk gpio2_ick = {
1505 .name = "gpio2_ick",
972c5427
RN		 1506 .ops = &clkops_omap2_dflt,
1507 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1508 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1509 .clkdm_name = "l4_per_clkdm",
1510 .parent = &l4_div_ck,
1511 .recalc = &followparent_recalc,
1512};
1513
1c03f42f
BC		 1514static struct clk gpio3_dbclk = {
1515 .name = "gpio3_dbclk",
1516 .ops = &clkops_omap2_dflt,
1517 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1518 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1519 .clkdm_name = "l4_per_clkdm",
1520 .parent = &sys_32k_ck,
1521 .recalc = &followparent_recalc,
1522};
1523
54776050
RN		 1524static struct clk gpio3_ick = {
1525 .name = "gpio3_ick",
972c5427
RN		 1526 .ops = &clkops_omap2_dflt,
1527 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1528 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1529 .clkdm_name = "l4_per_clkdm",
1530 .parent = &l4_div_ck,
1531 .recalc = &followparent_recalc,
1532};
1533
1c03f42f
BC		 1534static struct clk gpio4_dbclk = {
1535 .name = "gpio4_dbclk",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1538 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1539 .clkdm_name = "l4_per_clkdm",
1540 .parent = &sys_32k_ck,
1541 .recalc = &followparent_recalc,
1542};
1543
54776050
RN		 1544static struct clk gpio4_ick = {
1545 .name = "gpio4_ick",
972c5427
RN		 1546 .ops = &clkops_omap2_dflt,
1547 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1548 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1549 .clkdm_name = "l4_per_clkdm",
1550 .parent = &l4_div_ck,
1551 .recalc = &followparent_recalc,
1552};
1553
1c03f42f
BC		 1554static struct clk gpio5_dbclk = {
1555 .name = "gpio5_dbclk",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1558 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559 .clkdm_name = "l4_per_clkdm",
1560 .parent = &sys_32k_ck,
1561 .recalc = &followparent_recalc,
1562};
1563
54776050
RN		 1564static struct clk gpio5_ick = {
1565 .name = "gpio5_ick",
972c5427
RN		 1566 .ops = &clkops_omap2_dflt,
1567 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1568 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1569 .clkdm_name = "l4_per_clkdm",
1570 .parent = &l4_div_ck,
1571 .recalc = &followparent_recalc,
1572};
1573
1c03f42f
BC		 1574static struct clk gpio6_dbclk = {
1575 .name = "gpio6_dbclk",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1578 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &sys_32k_ck,
1581 .recalc = &followparent_recalc,
1582};
1583
54776050
RN		 1584static struct clk gpio6_ick = {
1585 .name = "gpio6_ick",
972c5427
RN		 1586 .ops = &clkops_omap2_dflt,
1587 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1588 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1589 .clkdm_name = "l4_per_clkdm",
1590 .parent = &l4_div_ck,
1591 .recalc = &followparent_recalc,
1592};
1593
54776050
RN		 1594static struct clk gpmc_ick = {
1595 .name = "gpmc_ick",
972c5427
RN		 1596 .ops = &clkops_omap2_dflt,
1597 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1598 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1599 .clkdm_name = "l3_2_clkdm",
1600 .parent = &l3_div_ck,
1601 .recalc = &followparent_recalc,
1602};
1603
0e433271
BC		 1604static const struct clksel sgx_clk_mux_sel[] = {
1605 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1606 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
972c5427
RN		 1607 { .parent = NULL },
1608};
1609
0e433271
BC		 1610/* Merged sgx_clk_mux into gpu */
1611static struct clk gpu_fck = {
1612 .name = "gpu_fck",
1613 .parent = &dpll_core_m7_ck,
1614 .clksel = sgx_clk_mux_sel,
972c5427 1615 .init = &omap2_init_clksel_parent,
0e433271
BC		 1616 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1617 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
972c5427
RN		 1618 .ops = &clkops_omap2_dflt,
1619 .recalc = &omap2_clksel_recalc,
0e433271 1620 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
972c5427 1621 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
0e433271 1622 .clkdm_name = "l3_gfx_clkdm",
972c5427
RN		 1623};
1624
54776050
RN		 1625static struct clk hdq1w_fck = {
1626 .name = "hdq1w_fck",
972c5427
RN		 1627 .ops = &clkops_omap2_dflt,
1628 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1629 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1630 .clkdm_name = "l4_per_clkdm",
1631 .parent = &func_12m_fclk,
1632 .recalc = &followparent_recalc,
1633};
1634
76cf5295
RN		 1635static const struct clksel hsi_fclk_div[] = {
1636 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1637 { .parent = NULL },
1638};
1639
54776050 1640/* Merged hsi_fclk into hsi */
0e433271
BC		 1641static struct clk hsi_fck = {
1642 .name = "hsi_fck",
972c5427 1643 .parent = &dpll_per_m2x2_ck,
76cf5295 1644 .clksel = hsi_fclk_div,
972c5427
RN		 1645 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1646 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1647 .ops = &clkops_omap2_dflt,
1648 .recalc = &omap2_clksel_recalc,
1649 .round_rate = &omap2_clksel_round_rate,
1650 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1651 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1653 .clkdm_name = "l3_init_clkdm",
1654};
1655
54776050
RN		 1656static struct clk i2c1_fck = {
1657 .name = "i2c1_fck",
972c5427
RN		 1658 .ops = &clkops_omap2_dflt,
1659 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1660 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1661 .clkdm_name = "l4_per_clkdm",
1662 .parent = &func_96m_fclk,
1663 .recalc = &followparent_recalc,
1664};
1665
54776050
RN		 1666static struct clk i2c2_fck = {
1667 .name = "i2c2_fck",
972c5427
RN		 1668 .ops = &clkops_omap2_dflt,
1669 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "l4_per_clkdm",
1672 .parent = &func_96m_fclk,
1673 .recalc = &followparent_recalc,
1674};
1675
54776050
RN		 1676static struct clk i2c3_fck = {
1677 .name = "i2c3_fck",
972c5427
RN		 1678 .ops = &clkops_omap2_dflt,
1679 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1680 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1681 .clkdm_name = "l4_per_clkdm",
1682 .parent = &func_96m_fclk,
1683 .recalc = &followparent_recalc,
1684};
1685
54776050
RN		 1686static struct clk i2c4_fck = {
1687 .name = "i2c4_fck",
972c5427
RN		 1688 .ops = &clkops_omap2_dflt,
1689 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1690 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1691 .clkdm_name = "l4_per_clkdm",
1692 .parent = &func_96m_fclk,
1693 .recalc = &followparent_recalc,
1694};
1695
0e433271
BC		 1696static struct clk ipu_fck = {
1697 .name = "ipu_fck",
1698 .ops = &clkops_omap2_dflt,
1699 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1700 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1701 .clkdm_name = "ducati_clkdm",
1702 .parent = &ducati_clk_mux_ck,
1703 .recalc = &followparent_recalc,
1704};
1705
1c03f42f
BC		 1706static struct clk iss_ctrlclk = {
1707 .name = "iss_ctrlclk",
1708 .ops = &clkops_omap2_dflt,
1709 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1710 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1711 .clkdm_name = "iss_clkdm",
1712 .parent = &func_96m_fclk,
1713 .recalc = &followparent_recalc,
1714};
1715
54776050
RN		 1716static struct clk iss_fck = {
1717 .name = "iss_fck",
972c5427
RN		 1718 .ops = &clkops_omap2_dflt,
1719 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1720 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1721 .clkdm_name = "iss_clkdm",
1722 .parent = &ducati_clk_mux_ck,
1723 .recalc = &followparent_recalc,
1724};
1725
0e433271
BC		 1726static struct clk iva_fck = {
1727 .name = "iva_fck",
972c5427
RN		 1728 .ops = &clkops_omap2_dflt,
1729 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1730 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1731 .clkdm_name = "ivahd_clkdm",
1732 .parent = &dpll_iva_m5_ck,
1733 .recalc = &followparent_recalc,
1734};
1735
0e433271
BC		 1736static struct clk kbd_fck = {
1737 .name = "kbd_fck",
972c5427
RN		 1738 .ops = &clkops_omap2_dflt,
1739 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1740 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1741 .clkdm_name = "l4_wkup_clkdm",
1742 .parent = &sys_32k_ck,
1743 .recalc = &followparent_recalc,
1744};
1745
0e433271
BC		 1746static struct clk l3_instr_ick = {
1747 .name = "l3_instr_ick",
972c5427
RN		 1748 .ops = &clkops_omap2_dflt,
1749 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1750 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1751 .clkdm_name = "l3_instr_clkdm",
1752 .parent = &l3_div_ck,
1753 .recalc = &followparent_recalc,
1754};
1755
0e433271
BC		 1756static struct clk l3_main_3_ick = {
1757 .name = "l3_main_3_ick",
972c5427
RN		 1758 .ops = &clkops_omap2_dflt,
1759 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1760 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1761 .clkdm_name = "l3_instr_clkdm",
1762 .parent = &l3_div_ck,
1763 .recalc = &followparent_recalc,
1764};
1765
1766static struct clk mcasp_sync_mux_ck = {
1767 .name = "mcasp_sync_mux_ck",
1768 .parent = &abe_24m_fclk,
1769 .clksel = dmic_sync_mux_sel,
1770 .init = &omap2_init_clksel_parent,
1771 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1772 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1773 .ops = &clkops_null,
1774 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1775};
1776
1777static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1778 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1779 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1780 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1781 { .parent = NULL },
1782};
1783
54776050
RN		 1784/* Merged func_mcasp_abe_gfclk into mcasp */
1785static struct clk mcasp_fck = {
1786 .name = "mcasp_fck",
972c5427
RN		 1787 .parent = &mcasp_sync_mux_ck,
1788 .clksel = func_mcasp_abe_gfclk_sel,
1789 .init = &omap2_init_clksel_parent,
1790 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1791 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1792 .ops = &clkops_omap2_dflt,
1793 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1794 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1795 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1796 .clkdm_name = "abe_clkdm",
1797};
1798
1799static struct clk mcbsp1_sync_mux_ck = {
1800 .name = "mcbsp1_sync_mux_ck",
1801 .parent = &abe_24m_fclk,
1802 .clksel = dmic_sync_mux_sel,
1803 .init = &omap2_init_clksel_parent,
1804 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1805 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1806 .ops = &clkops_null,
1807 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1808};
1809
1810static const struct clksel func_mcbsp1_gfclk_sel[] = {
1811 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1812 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1813 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1814 { .parent = NULL },
1815};
1816
54776050
RN		 1817/* Merged func_mcbsp1_gfclk into mcbsp1 */
1818static struct clk mcbsp1_fck = {
1819 .name = "mcbsp1_fck",
972c5427
RN		 1820 .parent = &mcbsp1_sync_mux_ck,
1821 .clksel = func_mcbsp1_gfclk_sel,
1822 .init = &omap2_init_clksel_parent,
1823 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1824 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1825 .ops = &clkops_omap2_dflt,
1826 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1827 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1829 .clkdm_name = "abe_clkdm",
1830};
1831
1832static struct clk mcbsp2_sync_mux_ck = {
1833 .name = "mcbsp2_sync_mux_ck",
1834 .parent = &abe_24m_fclk,
1835 .clksel = dmic_sync_mux_sel,
1836 .init = &omap2_init_clksel_parent,
1837 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1838 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1839 .ops = &clkops_null,
1840 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1841};
1842
1843static const struct clksel func_mcbsp2_gfclk_sel[] = {
1844 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1845 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1846 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1847 { .parent = NULL },
1848};
1849
54776050
RN		 1850/* Merged func_mcbsp2_gfclk into mcbsp2 */
1851static struct clk mcbsp2_fck = {
1852 .name = "mcbsp2_fck",
972c5427
RN		 1853 .parent = &mcbsp2_sync_mux_ck,
1854 .clksel = func_mcbsp2_gfclk_sel,
1855 .init = &omap2_init_clksel_parent,
1856 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1857 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1858 .ops = &clkops_omap2_dflt,
1859 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1860 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1861 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1862 .clkdm_name = "abe_clkdm",
1863};
1864
1865static struct clk mcbsp3_sync_mux_ck = {
1866 .name = "mcbsp3_sync_mux_ck",
1867 .parent = &abe_24m_fclk,
1868 .clksel = dmic_sync_mux_sel,
1869 .init = &omap2_init_clksel_parent,
1870 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1871 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1872 .ops = &clkops_null,
1873 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1874};
1875
1876static const struct clksel func_mcbsp3_gfclk_sel[] = {
1877 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1878 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1879 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1880 { .parent = NULL },
1881};
1882
54776050
RN		 1883/* Merged func_mcbsp3_gfclk into mcbsp3 */
1884static struct clk mcbsp3_fck = {
1885 .name = "mcbsp3_fck",
972c5427
RN		 1886 .parent = &mcbsp3_sync_mux_ck,
1887 .clksel = func_mcbsp3_gfclk_sel,
1888 .init = &omap2_init_clksel_parent,
1889 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1890 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1891 .ops = &clkops_omap2_dflt,
1892 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1893 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1894 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1895 .clkdm_name = "abe_clkdm",
1896};
1897
1898static struct clk mcbsp4_sync_mux_ck = {
1899 .name = "mcbsp4_sync_mux_ck",
1900 .parent = &func_96m_fclk,
1901 .clksel = mcasp2_fclk_sel,
1902 .init = &omap2_init_clksel_parent,
1903 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1904 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1905 .ops = &clkops_null,
1906 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1907};
1908
1909static const struct clksel per_mcbsp4_gfclk_sel[] = {
1910 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1911 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1912 { .parent = NULL },
1913};
1914
54776050
RN		 1915/* Merged per_mcbsp4_gfclk into mcbsp4 */
1916static struct clk mcbsp4_fck = {
1917 .name = "mcbsp4_fck",
972c5427
RN		 1918 .parent = &mcbsp4_sync_mux_ck,
1919 .clksel = per_mcbsp4_gfclk_sel,
1920 .init = &omap2_init_clksel_parent,
1921 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1922 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1923 .ops = &clkops_omap2_dflt,
1924 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1925 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1926 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1927 .clkdm_name = "l4_per_clkdm",
1928};
1929
0e433271
BC		 1930static struct clk mcpdm_fck = {
1931 .name = "mcpdm_fck",
1932 .ops = &clkops_omap2_dflt,
1933 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1934 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1935 .clkdm_name = "abe_clkdm",
1936 .parent = &pad_clks_ck,
1937 .recalc = &followparent_recalc,
1938};
1939
54776050
RN		 1940static struct clk mcspi1_fck = {
1941 .name = "mcspi1_fck",
972c5427
RN		 1942 .ops = &clkops_omap2_dflt,
1943 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1944 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1945 .clkdm_name = "l4_per_clkdm",
1946 .parent = &func_48m_fclk,
1947 .recalc = &followparent_recalc,
1948};
1949
54776050
RN		 1950static struct clk mcspi2_fck = {
1951 .name = "mcspi2_fck",
972c5427
RN		 1952 .ops = &clkops_omap2_dflt,
1953 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1954 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1955 .clkdm_name = "l4_per_clkdm",
1956 .parent = &func_48m_fclk,
1957 .recalc = &followparent_recalc,
1958};
1959
54776050
RN		 1960static struct clk mcspi3_fck = {
1961 .name = "mcspi3_fck",
972c5427
RN		 1962 .ops = &clkops_omap2_dflt,
1963 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1964 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1965 .clkdm_name = "l4_per_clkdm",
1966 .parent = &func_48m_fclk,
1967 .recalc = &followparent_recalc,
1968};
1969
54776050
RN		 1970static struct clk mcspi4_fck = {
1971 .name = "mcspi4_fck",
972c5427
RN		 1972 .ops = &clkops_omap2_dflt,
1973 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1974 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1975 .clkdm_name = "l4_per_clkdm",
1976 .parent = &func_48m_fclk,
1977 .recalc = &followparent_recalc,
1978};
1979
54776050
RN		 1980/* Merged hsmmc1_fclk into mmc1 */
1981static struct clk mmc1_fck = {
1982 .name = "mmc1_fck",
972c5427
RN		 1983 .parent = &func_64m_fclk,
1984 .clksel = hsmmc6_fclk_sel,
1985 .init = &omap2_init_clksel_parent,
1986 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1987 .clksel_mask = OMAP4430_CLKSEL_MASK,
1988 .ops = &clkops_omap2_dflt,
1989 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1990 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1991 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1992 .clkdm_name = "l3_init_clkdm",
1993};
1994
54776050
RN		 1995/* Merged hsmmc2_fclk into mmc2 */
1996static struct clk mmc2_fck = {
1997 .name = "mmc2_fck",
972c5427
RN		 1998 .parent = &func_64m_fclk,
1999 .clksel = hsmmc6_fclk_sel,
2000 .init = &omap2_init_clksel_parent,
2001 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2002 .clksel_mask = OMAP4430_CLKSEL_MASK,
2003 .ops = &clkops_omap2_dflt,
2004 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2005 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2006 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2007 .clkdm_name = "l3_init_clkdm",
2008};
2009
54776050
RN		 2010static struct clk mmc3_fck = {
2011 .name = "mmc3_fck",
972c5427
RN		 2012 .ops = &clkops_omap2_dflt,
2013 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2014 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2015 .clkdm_name = "l4_per_clkdm",
2016 .parent = &func_48m_fclk,
2017 .recalc = &followparent_recalc,
2018};
2019
54776050
RN		 2020static struct clk mmc4_fck = {
2021 .name = "mmc4_fck",
972c5427
RN		 2022 .ops = &clkops_omap2_dflt,
2023 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2024 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2025 .clkdm_name = "l4_per_clkdm",
2026 .parent = &func_48m_fclk,
2027 .recalc = &followparent_recalc,
2028};
2029
54776050
RN		 2030static struct clk mmc5_fck = {
2031 .name = "mmc5_fck",
972c5427
RN		 2032 .ops = &clkops_omap2_dflt,
2033 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2034 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2035 .clkdm_name = "l4_per_clkdm",
2036 .parent = &func_48m_fclk,
2037 .recalc = &followparent_recalc,
2038};
2039
0edc9e85
BC		 2040static struct clk ocp2scp_usb_phy_phy_48m = {
2041 .name = "ocp2scp_usb_phy_phy_48m",
1c03f42f
BC		 2042 .ops = &clkops_omap2_dflt,
2043 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
0edc9e85 2044 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
1c03f42f 2045 .clkdm_name = "l3_init_clkdm",
0edc9e85 2046 .parent = &func_48m_fclk,
1c03f42f
BC		 2047 .recalc = &followparent_recalc,
2048};
2049
0edc9e85
BC		 2050static struct clk ocp2scp_usb_phy_ick = {
2051 .name = "ocp2scp_usb_phy_ick",
1c03f42f
BC		 2052 .ops = &clkops_omap2_dflt,
2053 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
0edc9e85 2054 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1c03f42f 2055 .clkdm_name = "l3_init_clkdm",
0edc9e85 2056 .parent = &l4_div_ck,
1c03f42f
BC		 2057 .recalc = &followparent_recalc,
2058};
2059
0e433271
BC		 2060static struct clk ocp_wp_noc_ick = {
2061 .name = "ocp_wp_noc_ick",
972c5427
RN		 2062 .ops = &clkops_omap2_dflt,
2063 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2064 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2065 .clkdm_name = "l3_instr_clkdm",
2066 .parent = &l3_div_ck,
2067 .recalc = &followparent_recalc,
2068};
2069
54776050
RN		 2070static struct clk rng_ick = {
2071 .name = "rng_ick",
972c5427
RN		 2072 .ops = &clkops_omap2_dflt,
2073 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2074 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2075 .clkdm_name = "l4_secure_clkdm",
2076 .parent = &l4_div_ck,
2077 .recalc = &followparent_recalc,
2078};
2079
0e433271
BC		 2080static struct clk sha2md5_fck = {
2081 .name = "sha2md5_fck",
972c5427
RN		 2082 .ops = &clkops_omap2_dflt,
2083 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2084 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2085 .clkdm_name = "l4_secure_clkdm",
2086 .parent = &l3_div_ck,
2087 .recalc = &followparent_recalc,
2088};
2089
0e433271
BC		 2090static struct clk sl2if_ick = {
2091 .name = "sl2if_ick",
972c5427
RN		 2092 .ops = &clkops_omap2_dflt,
2093 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2094 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2095 .clkdm_name = "ivahd_clkdm",
2096 .parent = &dpll_iva_m5_ck,
2097 .recalc = &followparent_recalc,
2098};
2099
1c03f42f
BC		 2100static struct clk slimbus1_fclk_1 = {
2101 .name = "slimbus1_fclk_1",
2102 .ops = &clkops_omap2_dflt,
2103 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2104 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2105 .clkdm_name = "abe_clkdm",
2106 .parent = &func_24m_clk,
2107 .recalc = &followparent_recalc,
2108};
2109
2110static struct clk slimbus1_fclk_0 = {
2111 .name = "slimbus1_fclk_0",
2112 .ops = &clkops_omap2_dflt,
2113 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2114 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2115 .clkdm_name = "abe_clkdm",
2116 .parent = &abe_24m_fclk,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk slimbus1_fclk_2 = {
2121 .name = "slimbus1_fclk_2",
2122 .ops = &clkops_omap2_dflt,
2123 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2124 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2125 .clkdm_name = "abe_clkdm",
2126 .parent = &pad_clks_ck,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk slimbus1_slimbus_clk = {
2131 .name = "slimbus1_slimbus_clk",
2132 .ops = &clkops_omap2_dflt,
2133 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2134 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2135 .clkdm_name = "abe_clkdm",
2136 .parent = &slimbus_clk,
2137 .recalc = &followparent_recalc,
2138};
2139
54776050
RN		 2140static struct clk slimbus1_fck = {
2141 .name = "slimbus1_fck",
972c5427
RN		 2142 .ops = &clkops_omap2_dflt,
2143 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2144 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2145 .clkdm_name = "abe_clkdm",
2146 .parent = &ocp_abe_iclk,
2147 .recalc = &followparent_recalc,
2148};
2149
1c03f42f
BC		 2150static struct clk slimbus2_fclk_1 = {
2151 .name = "slimbus2_fclk_1",
2152 .ops = &clkops_omap2_dflt,
2153 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2154 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2155 .clkdm_name = "l4_per_clkdm",
2156 .parent = &per_abe_24m_fclk,
2157 .recalc = &followparent_recalc,
2158};
2159
2160static struct clk slimbus2_fclk_0 = {
2161 .name = "slimbus2_fclk_0",
2162 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2164 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2165 .clkdm_name = "l4_per_clkdm",
2166 .parent = &func_24mc_fclk,
2167 .recalc = &followparent_recalc,
2168};
2169
2170static struct clk slimbus2_slimbus_clk = {
2171 .name = "slimbus2_slimbus_clk",
2172 .ops = &clkops_omap2_dflt,
2173 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2174 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2175 .clkdm_name = "l4_per_clkdm",
2176 .parent = &pad_slimbus_core_clks_ck,
2177 .recalc = &followparent_recalc,
2178};
2179
54776050
RN		 2180static struct clk slimbus2_fck = {
2181 .name = "slimbus2_fck",
972c5427
RN		 2182 .ops = &clkops_omap2_dflt,
2183 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2184 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2185 .clkdm_name = "l4_per_clkdm",
2186 .parent = &l4_div_ck,
2187 .recalc = &followparent_recalc,
2188};
2189
0e433271
BC		 2190static struct clk smartreflex_core_fck = {
2191 .name = "smartreflex_core_fck",
972c5427
RN		 2192 .ops = &clkops_omap2_dflt,
2193 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2194 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2195 .clkdm_name = "l4_ao_clkdm",
2196 .parent = &l4_wkup_clk_mux_ck,
2197 .recalc = &followparent_recalc,
2198};
2199
0e433271
BC		 2200static struct clk smartreflex_iva_fck = {
2201 .name = "smartreflex_iva_fck",
972c5427
RN		 2202 .ops = &clkops_omap2_dflt,
2203 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2204 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2205 .clkdm_name = "l4_ao_clkdm",
2206 .parent = &l4_wkup_clk_mux_ck,
2207 .recalc = &followparent_recalc,
2208};
2209
0e433271
BC		 2210static struct clk smartreflex_mpu_fck = {
2211 .name = "smartreflex_mpu_fck",
972c5427
RN		 2212 .ops = &clkops_omap2_dflt,
2213 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2214 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2215 .clkdm_name = "l4_ao_clkdm",
2216 .parent = &l4_wkup_clk_mux_ck,
2217 .recalc = &followparent_recalc,
2218};
2219
0e433271
BC		 2220/* Merged dmt1_clk_mux into timer1 */
2221static struct clk timer1_fck = {
2222 .name = "timer1_fck",
2223 .parent = &sys_clkin_ck,
2224 .clksel = abe_dpll_bypass_clk_mux_sel,
2225 .init = &omap2_init_clksel_parent,
2226 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2227 .clksel_mask = OMAP4430_CLKSEL_MASK,
972c5427 2228 .ops = &clkops_omap2_dflt,
0e433271
BC		 2229 .recalc = &omap2_clksel_recalc,
2230 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2231 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2232 .clkdm_name = "l4_wkup_clkdm",
2233};
2234
2235/* Merged cm2_dm10_mux into timer10 */
2236static struct clk timer10_fck = {
2237 .name = "timer10_fck",
2238 .parent = &sys_clkin_ck,
2239 .clksel = abe_dpll_bypass_clk_mux_sel,
2240 .init = &omap2_init_clksel_parent,
2241 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2242 .clksel_mask = OMAP4430_CLKSEL_MASK,
2243 .ops = &clkops_omap2_dflt,
2244 .recalc = &omap2_clksel_recalc,
2245 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2246 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2247 .clkdm_name = "l4_per_clkdm",
2248};
2249
2250/* Merged cm2_dm11_mux into timer11 */
2251static struct clk timer11_fck = {
2252 .name = "timer11_fck",
2253 .parent = &sys_clkin_ck,
2254 .clksel = abe_dpll_bypass_clk_mux_sel,
2255 .init = &omap2_init_clksel_parent,
2256 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2257 .clksel_mask = OMAP4430_CLKSEL_MASK,
2258 .ops = &clkops_omap2_dflt,
2259 .recalc = &omap2_clksel_recalc,
2260 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2262 .clkdm_name = "l4_per_clkdm",
2263};
2264
2265/* Merged cm2_dm2_mux into timer2 */
2266static struct clk timer2_fck = {
2267 .name = "timer2_fck",
2268 .parent = &sys_clkin_ck,
2269 .clksel = abe_dpll_bypass_clk_mux_sel,
2270 .init = &omap2_init_clksel_parent,
2271 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2272 .clksel_mask = OMAP4430_CLKSEL_MASK,
2273 .ops = &clkops_omap2_dflt,
2274 .recalc = &omap2_clksel_recalc,
2275 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2276 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2277 .clkdm_name = "l4_per_clkdm",
2278};
2279
2280/* Merged cm2_dm3_mux into timer3 */
2281static struct clk timer3_fck = {
2282 .name = "timer3_fck",
2283 .parent = &sys_clkin_ck,
2284 .clksel = abe_dpll_bypass_clk_mux_sel,
2285 .init = &omap2_init_clksel_parent,
2286 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2287 .clksel_mask = OMAP4430_CLKSEL_MASK,
2288 .ops = &clkops_omap2_dflt,
2289 .recalc = &omap2_clksel_recalc,
2290 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2292 .clkdm_name = "l4_per_clkdm",
2293};
2294
2295/* Merged cm2_dm4_mux into timer4 */
2296static struct clk timer4_fck = {
2297 .name = "timer4_fck",
2298 .parent = &sys_clkin_ck,
2299 .clksel = abe_dpll_bypass_clk_mux_sel,
2300 .init = &omap2_init_clksel_parent,
2301 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2302 .clksel_mask = OMAP4430_CLKSEL_MASK,
2303 .ops = &clkops_omap2_dflt,
2304 .recalc = &omap2_clksel_recalc,
2305 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2306 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2307 .clkdm_name = "l4_per_clkdm",
2308};
2309
2310static const struct clksel timer5_sync_mux_sel[] = {
2311 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2312 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2313 { .parent = NULL },
2314};
2315
2316/* Merged timer5_sync_mux into timer5 */
2317static struct clk timer5_fck = {
2318 .name = "timer5_fck",
2319 .parent = &syc_clk_div_ck,
2320 .clksel = timer5_sync_mux_sel,
2321 .init = &omap2_init_clksel_parent,
2322 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2323 .clksel_mask = OMAP4430_CLKSEL_MASK,
2324 .ops = &clkops_omap2_dflt,
2325 .recalc = &omap2_clksel_recalc,
2326 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2327 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2328 .clkdm_name = "abe_clkdm",
2329};
2330
2331/* Merged timer6_sync_mux into timer6 */
2332static struct clk timer6_fck = {
2333 .name = "timer6_fck",
2334 .parent = &syc_clk_div_ck,
2335 .clksel = timer5_sync_mux_sel,
2336 .init = &omap2_init_clksel_parent,
2337 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2338 .clksel_mask = OMAP4430_CLKSEL_MASK,
2339 .ops = &clkops_omap2_dflt,
2340 .recalc = &omap2_clksel_recalc,
2341 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2343 .clkdm_name = "abe_clkdm",
2344};
2345
2346/* Merged timer7_sync_mux into timer7 */
2347static struct clk timer7_fck = {
2348 .name = "timer7_fck",
2349 .parent = &syc_clk_div_ck,
2350 .clksel = timer5_sync_mux_sel,
2351 .init = &omap2_init_clksel_parent,
2352 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2353 .clksel_mask = OMAP4430_CLKSEL_MASK,
2354 .ops = &clkops_omap2_dflt,
2355 .recalc = &omap2_clksel_recalc,
2356 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2357 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2358 .clkdm_name = "abe_clkdm",
2359};
2360
2361/* Merged timer8_sync_mux into timer8 */
2362static struct clk timer8_fck = {
2363 .name = "timer8_fck",
2364 .parent = &syc_clk_div_ck,
2365 .clksel = timer5_sync_mux_sel,
2366 .init = &omap2_init_clksel_parent,
2367 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2368 .clksel_mask = OMAP4430_CLKSEL_MASK,
2369 .ops = &clkops_omap2_dflt,
2370 .recalc = &omap2_clksel_recalc,
2371 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2372 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2373 .clkdm_name = "abe_clkdm",
2374};
2375
2376/* Merged cm2_dm9_mux into timer9 */
2377static struct clk timer9_fck = {
2378 .name = "timer9_fck",
2379 .parent = &sys_clkin_ck,
2380 .clksel = abe_dpll_bypass_clk_mux_sel,
2381 .init = &omap2_init_clksel_parent,
2382 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2383 .clksel_mask = OMAP4430_CLKSEL_MASK,
2384 .ops = &clkops_omap2_dflt,
2385 .recalc = &omap2_clksel_recalc,
2386 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2387 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2388 .clkdm_name = "l4_per_clkdm",
972c5427
RN		 2389};
2390
54776050
RN		 2391static struct clk uart1_fck = {
2392 .name = "uart1_fck",
972c5427
RN		 2393 .ops = &clkops_omap2_dflt,
2394 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2395 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2396 .clkdm_name = "l4_per_clkdm",
2397 .parent = &func_48m_fclk,
2398 .recalc = &followparent_recalc,
2399};
2400
54776050
RN		 2401static struct clk uart2_fck = {
2402 .name = "uart2_fck",
972c5427
RN		 2403 .ops = &clkops_omap2_dflt,
2404 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2405 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2406 .clkdm_name = "l4_per_clkdm",
2407 .parent = &func_48m_fclk,
2408 .recalc = &followparent_recalc,
2409};
2410
54776050
RN		 2411static struct clk uart3_fck = {
2412 .name = "uart3_fck",
972c5427
RN		 2413 .ops = &clkops_omap2_dflt,
2414 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2416 .clkdm_name = "l4_per_clkdm",
2417 .parent = &func_48m_fclk,
2418 .recalc = &followparent_recalc,
2419};
2420
54776050
RN		 2421static struct clk uart4_fck = {
2422 .name = "uart4_fck",
972c5427
RN		 2423 .ops = &clkops_omap2_dflt,
2424 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2425 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2426 .clkdm_name = "l4_per_clkdm",
2427 .parent = &func_48m_fclk,
2428 .recalc = &followparent_recalc,
2429};
2430
0e433271
BC		 2431static struct clk usb_host_fs_fck = {
2432 .name = "usb_host_fs_fck",
972c5427 2433 .ops = &clkops_omap2_dflt,
0e433271 2434 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
972c5427
RN		 2435 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2436 .clkdm_name = "l3_init_clkdm",
0e433271 2437 .parent = &func_48mc_fclk,
972c5427
RN		 2438 .recalc = &followparent_recalc,
2439};
2440
1c03f42f
BC		 2441static struct clk usb_host_hs_utmi_p3_clk = {
2442 .name = "usb_host_hs_utmi_p3_clk",
2443 .ops = &clkops_omap2_dflt,
2444 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2445 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2446 .clkdm_name = "l3_init_clkdm",
2447 .parent = &init_60m_fclk,
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk usb_host_hs_hsic60m_p1_clk = {
2452 .name = "usb_host_hs_hsic60m_p1_clk",
2453 .ops = &clkops_omap2_dflt,
2454 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2455 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2456 .clkdm_name = "l3_init_clkdm",
2457 .parent = &init_60m_fclk,
2458 .recalc = &followparent_recalc,
2459};
2460
2461static struct clk usb_host_hs_hsic60m_p2_clk = {
2462 .name = "usb_host_hs_hsic60m_p2_clk",
2463 .ops = &clkops_omap2_dflt,
2464 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2465 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2466 .clkdm_name = "l3_init_clkdm",
2467 .parent = &init_60m_fclk,
2468 .recalc = &followparent_recalc,
2469};
2470
2471static const struct clksel utmi_p1_gfclk_sel[] = {
2472 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2473 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2474 { .parent = NULL },
2475};
2476
2477static struct clk utmi_p1_gfclk = {
2478 .name = "utmi_p1_gfclk",
2479 .parent = &init_60m_fclk,
2480 .clksel = utmi_p1_gfclk_sel,
2481 .init = &omap2_init_clksel_parent,
2482 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2483 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2484 .ops = &clkops_null,
2485 .recalc = &omap2_clksel_recalc,
2486};
2487
2488static struct clk usb_host_hs_utmi_p1_clk = {
2489 .name = "usb_host_hs_utmi_p1_clk",
2490 .ops = &clkops_omap2_dflt,
2491 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2492 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2493 .clkdm_name = "l3_init_clkdm",
2494 .parent = &utmi_p1_gfclk,
2495 .recalc = &followparent_recalc,
2496};
2497
2498static const struct clksel utmi_p2_gfclk_sel[] = {
2499 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2500 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2501 { .parent = NULL },
2502};
2503
2504static struct clk utmi_p2_gfclk = {
2505 .name = "utmi_p2_gfclk",
2506 .parent = &init_60m_fclk,
2507 .clksel = utmi_p2_gfclk_sel,
2508 .init = &omap2_init_clksel_parent,
2509 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2510 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2511 .ops = &clkops_null,
2512 .recalc = &omap2_clksel_recalc,
2513};
2514
2515static struct clk usb_host_hs_utmi_p2_clk = {
2516 .name = "usb_host_hs_utmi_p2_clk",
2517 .ops = &clkops_omap2_dflt,
2518 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2519 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2520 .clkdm_name = "l3_init_clkdm",
2521 .parent = &utmi_p2_gfclk,
2522 .recalc = &followparent_recalc,
2523};
2524
2525static struct clk usb_host_hs_hsic480m_p1_clk = {
2526 .name = "usb_host_hs_hsic480m_p1_clk",
2527 .ops = &clkops_omap2_dflt,
2528 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2529 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2530 .clkdm_name = "l3_init_clkdm",
2531 .parent = &dpll_usb_m2_ck,
2532 .recalc = &followparent_recalc,
2533};
2534
2535static struct clk usb_host_hs_hsic480m_p2_clk = {
2536 .name = "usb_host_hs_hsic480m_p2_clk",
2537 .ops = &clkops_omap2_dflt,
2538 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2540 .clkdm_name = "l3_init_clkdm",
2541 .parent = &dpll_usb_m2_ck,
2542 .recalc = &followparent_recalc,
2543};
2544
2545static struct clk usb_host_hs_func48mclk = {
2546 .name = "usb_host_hs_func48mclk",
2547 .ops = &clkops_omap2_dflt,
2548 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2549 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2550 .clkdm_name = "l3_init_clkdm",
2551 .parent = &func_48mc_fclk,
2552 .recalc = &followparent_recalc,
2553};
2554
0e433271
BC		 2555static struct clk usb_host_hs_fck = {
2556 .name = "usb_host_hs_fck",
972c5427
RN		 2557 .ops = &clkops_omap2_dflt,
2558 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2559 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2560 .clkdm_name = "l3_init_clkdm",
2561 .parent = &init_60m_fclk,
2562 .recalc = &followparent_recalc,
2563};
2564
1c03f42f
BC		 2565static const struct clksel otg_60m_gfclk_sel[] = {
2566 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2567 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2568 { .parent = NULL },
2569};
2570
2571static struct clk otg_60m_gfclk = {
2572 .name = "otg_60m_gfclk",
2573 .parent = &utmi_phy_clkout_ck,
2574 .clksel = otg_60m_gfclk_sel,
2575 .init = &omap2_init_clksel_parent,
2576 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2577 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2578 .ops = &clkops_null,
2579 .recalc = &omap2_clksel_recalc,
2580};
2581
2582static struct clk usb_otg_hs_xclk = {
2583 .name = "usb_otg_hs_xclk",
2584 .ops = &clkops_omap2_dflt,
2585 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2586 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2587 .clkdm_name = "l3_init_clkdm",
2588 .parent = &otg_60m_gfclk,
2589 .recalc = &followparent_recalc,
2590};
2591
0e433271
BC		 2592static struct clk usb_otg_hs_ick = {
2593 .name = "usb_otg_hs_ick",
972c5427
RN		 2594 .ops = &clkops_omap2_dflt,
2595 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2596 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2597 .clkdm_name = "l3_init_clkdm",
2598 .parent = &l3_div_ck,
2599 .recalc = &followparent_recalc,
2600};
2601
0edc9e85
BC		 2602static struct clk usb_phy_cm_clk32k = {
2603 .name = "usb_phy_cm_clk32k",
2604 .ops = &clkops_omap2_dflt,
2605 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2606 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2607 .clkdm_name = "l4_ao_clkdm",
2608 .parent = &sys_32k_ck,
2609 .recalc = &followparent_recalc,
2610};
2611
1c03f42f
BC		 2612static struct clk usb_tll_hs_usb_ch2_clk = {
2613 .name = "usb_tll_hs_usb_ch2_clk",
2614 .ops = &clkops_omap2_dflt,
2615 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2616 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2617 .clkdm_name = "l3_init_clkdm",
2618 .parent = &init_60m_fclk,
2619 .recalc = &followparent_recalc,
2620};
2621
2622static struct clk usb_tll_hs_usb_ch0_clk = {
2623 .name = "usb_tll_hs_usb_ch0_clk",
2624 .ops = &clkops_omap2_dflt,
2625 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2626 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2627 .clkdm_name = "l3_init_clkdm",
2628 .parent = &init_60m_fclk,
2629 .recalc = &followparent_recalc,
2630};
2631
2632static struct clk usb_tll_hs_usb_ch1_clk = {
2633 .name = "usb_tll_hs_usb_ch1_clk",
2634 .ops = &clkops_omap2_dflt,
2635 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2636 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2637 .clkdm_name = "l3_init_clkdm",
2638 .parent = &init_60m_fclk,
2639 .recalc = &followparent_recalc,
2640};
2641
0e433271
BC		 2642static struct clk usb_tll_hs_ick = {
2643 .name = "usb_tll_hs_ick",
972c5427
RN		 2644 .ops = &clkops_omap2_dflt,
2645 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2646 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2647 .clkdm_name = "l3_init_clkdm",
2648 .parent = &l4_div_ck,
2649 .recalc = &followparent_recalc,
2650};
2651
0edc9e85
BC		 2652static const struct clksel_rate div2_14to18_rates[] = {
2653 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2654 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2655 { .div = 0 },
2656};
2657
2658static const struct clksel usim_fclk_div[] = {
2659 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2660 { .parent = NULL },
2661};
2662
2663static struct clk usim_ck = {
2664 .name = "usim_ck",
2665 .parent = &dpll_per_m4_ck,
2666 .clksel = usim_fclk_div,
2667 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2668 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2669 .ops = &clkops_null,
2670 .recalc = &omap2_clksel_recalc,
2671 .round_rate = &omap2_clksel_round_rate,
2672 .set_rate = &omap2_clksel_set_rate,
2673};
2674
2675static struct clk usim_fclk = {
2676 .name = "usim_fclk",
2677 .ops = &clkops_omap2_dflt,
2678 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2679 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2680 .clkdm_name = "l4_wkup_clkdm",
2681 .parent = &usim_ck,
2682 .recalc = &followparent_recalc,
2683};
2684
0e433271
BC		 2685static struct clk usim_fck = {
2686 .name = "usim_fck",
972c5427
RN		 2687 .ops = &clkops_omap2_dflt,
2688 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
76cf5295 2689 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
972c5427
RN		 2690 .clkdm_name = "l4_wkup_clkdm",
2691 .parent = &sys_32k_ck,
2692 .recalc = &followparent_recalc,
2693};
2694
0e433271
BC		 2695static struct clk wd_timer2_fck = {
2696 .name = "wd_timer2_fck",
972c5427
RN		 2697 .ops = &clkops_omap2_dflt,
2698 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2699 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2700 .clkdm_name = "l4_wkup_clkdm",
2701 .parent = &sys_32k_ck,
2702 .recalc = &followparent_recalc,
2703};
2704
0e433271
BC		 2705static struct clk wd_timer3_fck = {
2706 .name = "wd_timer3_fck",
972c5427
RN		 2707 .ops = &clkops_omap2_dflt,
2708 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2709 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2710 .clkdm_name = "abe_clkdm",
2711 .parent = &sys_32k_ck,
2712 .recalc = &followparent_recalc,
2713};
2714
2715/* Remaining optional clocks */
972c5427
RN		 2716static const struct clksel stm_clk_div_div[] = {
2717 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2718 { .parent = NULL },
2719};
2720
2721static struct clk stm_clk_div_ck = {
2722 .name = "stm_clk_div_ck",
2723 .parent = &pmd_stm_clock_mux_ck,
2724 .clksel = stm_clk_div_div,
2725 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2726 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2727 .ops = &clkops_null,
2728 .recalc = &omap2_clksel_recalc,
2729 .round_rate = &omap2_clksel_round_rate,
2730 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 2731};
2732
2733static const struct clksel trace_clk_div_div[] = {
2734 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2735 { .parent = NULL },
2736};
2737
2738static struct clk trace_clk_div_ck = {
2739 .name = "trace_clk_div_ck",
2740 .parent = &pmd_trace_clk_mux_ck,
2741 .clksel = trace_clk_div_div,
2742 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2743 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2744 .ops = &clkops_null,
2745 .recalc = &omap2_clksel_recalc,
2746 .round_rate = &omap2_clksel_round_rate,
2747 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 2748};
2749
972c5427
RN		 2750/*
2751 * clkdev
2752 */
2753
2754static struct omap_clk omap44xx_clks[] = {
2755 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
2756 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
2757 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
2758 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
2759 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
2760 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
2761 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
2762 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
2763 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
2764 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
2765 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
2766 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2767 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2768 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
76cf5295 2769 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
972c5427
RN		 2770 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2771 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2772 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2773 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
76cf5295 2774 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
972c5427
RN		 2775 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2776 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2777 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2778 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2779 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2780 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2781 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
2782 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2783 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2784 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
2785 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2786 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2787 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2788 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
2789 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2790 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2791 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2792 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
2793 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2794 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2795 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
2796 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
2797 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2798 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2799 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
2800 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
2801 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2802 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2803 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2804 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2805 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2806 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
2807 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2808 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
2809 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
2810 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
2811 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
2812 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
2813 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
2814 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2815 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2816 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
2817 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
2818 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
2819 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
2820 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
2821 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
2822 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
2823 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
2824 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
2825 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
2826 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
2827 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
2828 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
2829 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
2830 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
2831 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
2832 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
2833 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
2834 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
2835 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
2836 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
2837 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
2838 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2839 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2840 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
54776050
RN		 2841 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2842 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2843 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1c03f42f 2844 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
54776050 2845 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
972c5427 2846 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
54776050 2847 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
0e433271 2848 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1c03f42f
BC		 2849 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
2850 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
2851 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
2852 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
54776050 2853 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
0e433271
BC		 2854 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
2855 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
2856 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
54776050 2857 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
0e433271 2858 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1c03f42f 2859 CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
54776050 2860 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1c03f42f 2861 CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
54776050 2862 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1c03f42f 2863 CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
54776050 2864 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1c03f42f 2865 CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
54776050 2866 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1c03f42f 2867 CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
54776050 2868 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1c03f42f 2869 CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
54776050
RN		 2870 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2871 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
0e433271 2872 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
54776050 2873 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
0e433271 2874 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
54776050
RN		 2875 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2876 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2877 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2878 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
0e433271 2879 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1c03f42f 2880 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
54776050 2881 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
0e433271
BC		 2882 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2883 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
2884 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
2885 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
972c5427 2886 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
54776050 2887 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
972c5427 2888 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
54776050 2889 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
972c5427 2890 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
54776050 2891 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
972c5427 2892 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
54776050 2893 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
972c5427 2894 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
54776050 2895 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
0e433271 2896 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
54776050
RN		 2897 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2898 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2899 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
2900 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
2901 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
2902 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
2903 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2904 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2905 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
1c03f42f 2906 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
0edc9e85 2907 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
0e433271 2908 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
54776050 2909 CLK("omap_rng", "ick", &rng_ick, CK_443X),
0e433271
BC		 2910 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2911 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1c03f42f
BC		 2912 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
2913 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
2914 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
2915 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
54776050 2916 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1c03f42f
BC		 2917 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
2918 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
2919 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
54776050 2920 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
0e433271
BC		 2921 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2922 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
2923 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
2924 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
2925 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
2926 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
2927 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
2928 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
2929 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
2930 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
2931 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
2932 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
2933 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
2934 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
54776050
RN		 2935 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2936 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2937 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2938 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
54776050 2939 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
5467e16d 2940 CLK("ehci-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
1c03f42f
BC		 2941 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2942 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
2943 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2944 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2945 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
2946 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
2947 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
2948 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
2949 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
2950 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
0e433271 2951 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
5467e16d
AG		 2952 CLK("ehci-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
2953 CLK("ehci-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
1c03f42f
BC		 2954 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
2955 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
05ac10dd 2956 CLK("musb-hdrc", "ick", &usb_otg_hs_ick, CK_443X),
0edc9e85 2957 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
1c03f42f
BC		 2958 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
2959 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
2960 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
0e433271 2961 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
5467e16d
AG		 2962 CLK("ehci-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
2963 CLK("ehci-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
0edc9e85
BC		 2964 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
2965 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
0e433271
BC		 2966 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2967 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2968 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
972c5427
RN		 2969 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2970 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
7c43d547
SS		 2971 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2972 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2973 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
2974 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
2975 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
2976 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
2977 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
2978 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
2979 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
2980 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
2981 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
2982 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
2983 CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
2984 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2985 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2986 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
0e433271
BC		 2987 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2988 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2989 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2990 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2991 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
7c43d547
SS		 2992 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2993 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2994 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2995 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
0e433271
BC		 2996 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2997 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2998 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2999 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
7c43d547
SS		 3000 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3001 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3002 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3003 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3004 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
972c5427
RN		 3005};
3006
e80a9729 3007int __init omap4xxx_clk_init(void)
972c5427 3008{
972c5427 3009 struct omap_clk *c;
972c5427
RN		 3010 u32 cpu_clkflg;
3011
3012 if (cpu_is_omap44xx()) {
3013 cpu_mask = RATE_IN_4430;
3014 cpu_clkflg = CK_443X;
3015 }
3016
3017 clk_init(&omap2_clk_functions);
3018
3019 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3020 c++)
3021 clk_preinit(c->lk.clk);
3022
3023 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3024 c++)
3025 if (c->cpu & cpu_clkflg) {
3026 clkdev_add(&c->lk);
3027 clk_register(c->lk.clk);
972c5427 3028 omap2_init_clk_clkdm(c->lk.clk);
972c5427
RN		 3029 }
3030
3031 recalculate_root_clocks();
3032
3033 /*
3034 * Only enable those clocks we will need, let the drivers
3035 * enable other clocks as necessary
3036 */
3037 clk_enable_init_clocks();
3038
3039 return 0;
3040}
Linux kernel - Deliverables
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