Commit | Line | Data |
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972c5427 RN |
1 | /* |
2 | * OMAP4 Clock data | |
3 | * | |
54776050 RN |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
972c5427 RN |
6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
76cf5295 RN |
20 | * |
21 | * XXX Some of the ES1 clocks have been removed/changed; once support | |
22 | * is added for discriminating clocks by ES level, these should be added back | |
23 | * in. | |
972c5427 RN |
24 | */ |
25 | ||
26 | #include <linux/kernel.h> | |
93340a22 | 27 | #include <linux/list.h> |
972c5427 | 28 | #include <linux/clk.h> |
972c5427 RN |
29 | #include <plat/clkdev_omap.h> |
30 | ||
31 | #include "clock.h" | |
32 | #include "clock44xx.h" | |
d198b514 PW |
33 | #include "cm1_44xx.h" |
34 | #include "cm2_44xx.h" | |
972c5427 | 35 | #include "cm-regbits-44xx.h" |
59fb659b | 36 | #include "prm44xx.h" |
d198b514 | 37 | #include "prm44xx.h" |
972c5427 | 38 | #include "prm-regbits-44xx.h" |
4814ced5 | 39 | #include "control.h" |
972c5427 | 40 | |
59fb659b PW |
41 | /* OMAP4 modulemode control */ |
42 | #define OMAP4430_MODULEMODE_HWCTRL 0 | |
43 | #define OMAP4430_MODULEMODE_SWCTRL 1 | |
44 | ||
972c5427 RN |
45 | /* Root clocks */ |
46 | ||
47 | static struct clk extalt_clkin_ck = { | |
48 | .name = "extalt_clkin_ck", | |
49 | .rate = 59000000, | |
50 | .ops = &clkops_null, | |
972c5427 RN |
51 | }; |
52 | ||
53 | static struct clk pad_clks_ck = { | |
54 | .name = "pad_clks_ck", | |
55 | .rate = 12000000, | |
d9b98f5f BC |
56 | .ops = &clkops_omap2_dflt, |
57 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
58 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, | |
972c5427 RN |
59 | }; |
60 | ||
61 | static struct clk pad_slimbus_core_clks_ck = { | |
62 | .name = "pad_slimbus_core_clks_ck", | |
63 | .rate = 12000000, | |
64 | .ops = &clkops_null, | |
972c5427 RN |
65 | }; |
66 | ||
67 | static struct clk secure_32k_clk_src_ck = { | |
68 | .name = "secure_32k_clk_src_ck", | |
69 | .rate = 32768, | |
70 | .ops = &clkops_null, | |
972c5427 RN |
71 | }; |
72 | ||
73 | static struct clk slimbus_clk = { | |
74 | .name = "slimbus_clk", | |
75 | .rate = 12000000, | |
d9b98f5f BC |
76 | .ops = &clkops_omap2_dflt, |
77 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
78 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | |
972c5427 RN |
79 | }; |
80 | ||
81 | static struct clk sys_32k_ck = { | |
82 | .name = "sys_32k_ck", | |
83 | .rate = 32768, | |
84 | .ops = &clkops_null, | |
972c5427 RN |
85 | }; |
86 | ||
87 | static struct clk virt_12000000_ck = { | |
88 | .name = "virt_12000000_ck", | |
89 | .ops = &clkops_null, | |
90 | .rate = 12000000, | |
91 | }; | |
92 | ||
93 | static struct clk virt_13000000_ck = { | |
94 | .name = "virt_13000000_ck", | |
95 | .ops = &clkops_null, | |
96 | .rate = 13000000, | |
97 | }; | |
98 | ||
99 | static struct clk virt_16800000_ck = { | |
100 | .name = "virt_16800000_ck", | |
101 | .ops = &clkops_null, | |
102 | .rate = 16800000, | |
103 | }; | |
104 | ||
105 | static struct clk virt_19200000_ck = { | |
106 | .name = "virt_19200000_ck", | |
107 | .ops = &clkops_null, | |
108 | .rate = 19200000, | |
109 | }; | |
110 | ||
111 | static struct clk virt_26000000_ck = { | |
112 | .name = "virt_26000000_ck", | |
113 | .ops = &clkops_null, | |
114 | .rate = 26000000, | |
115 | }; | |
116 | ||
117 | static struct clk virt_27000000_ck = { | |
118 | .name = "virt_27000000_ck", | |
119 | .ops = &clkops_null, | |
120 | .rate = 27000000, | |
121 | }; | |
122 | ||
123 | static struct clk virt_38400000_ck = { | |
124 | .name = "virt_38400000_ck", | |
125 | .ops = &clkops_null, | |
126 | .rate = 38400000, | |
127 | }; | |
128 | ||
129 | static const struct clksel_rate div_1_0_rates[] = { | |
130 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
131 | { .div = 0 }, | |
132 | }; | |
133 | ||
134 | static const struct clksel_rate div_1_1_rates[] = { | |
135 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | |
136 | { .div = 0 }, | |
137 | }; | |
138 | ||
139 | static const struct clksel_rate div_1_2_rates[] = { | |
140 | { .div = 1, .val = 2, .flags = RATE_IN_4430 }, | |
141 | { .div = 0 }, | |
142 | }; | |
143 | ||
144 | static const struct clksel_rate div_1_3_rates[] = { | |
145 | { .div = 1, .val = 3, .flags = RATE_IN_4430 }, | |
146 | { .div = 0 }, | |
147 | }; | |
148 | ||
149 | static const struct clksel_rate div_1_4_rates[] = { | |
150 | { .div = 1, .val = 4, .flags = RATE_IN_4430 }, | |
151 | { .div = 0 }, | |
152 | }; | |
153 | ||
154 | static const struct clksel_rate div_1_5_rates[] = { | |
155 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, | |
156 | { .div = 0 }, | |
157 | }; | |
158 | ||
159 | static const struct clksel_rate div_1_6_rates[] = { | |
160 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, | |
161 | { .div = 0 }, | |
162 | }; | |
163 | ||
164 | static const struct clksel_rate div_1_7_rates[] = { | |
165 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, | |
166 | { .div = 0 }, | |
167 | }; | |
168 | ||
169 | static const struct clksel sys_clkin_sel[] = { | |
170 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, | |
171 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, | |
172 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, | |
173 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, | |
174 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, | |
175 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, | |
176 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, | |
177 | { .parent = NULL }, | |
178 | }; | |
179 | ||
180 | static struct clk sys_clkin_ck = { | |
181 | .name = "sys_clkin_ck", | |
182 | .rate = 38400000, | |
183 | .clksel = sys_clkin_sel, | |
184 | .init = &omap2_init_clksel_parent, | |
185 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, | |
186 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | |
187 | .ops = &clkops_null, | |
188 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
189 | }; |
190 | ||
76cf5295 RN |
191 | static struct clk tie_low_clock_ck = { |
192 | .name = "tie_low_clock_ck", | |
193 | .rate = 0, | |
194 | .ops = &clkops_null, | |
195 | }; | |
196 | ||
972c5427 RN |
197 | static struct clk utmi_phy_clkout_ck = { |
198 | .name = "utmi_phy_clkout_ck", | |
76cf5295 | 199 | .rate = 60000000, |
972c5427 | 200 | .ops = &clkops_null, |
972c5427 RN |
201 | }; |
202 | ||
203 | static struct clk xclk60mhsp1_ck = { | |
204 | .name = "xclk60mhsp1_ck", | |
76cf5295 | 205 | .rate = 60000000, |
972c5427 | 206 | .ops = &clkops_null, |
972c5427 RN |
207 | }; |
208 | ||
209 | static struct clk xclk60mhsp2_ck = { | |
210 | .name = "xclk60mhsp2_ck", | |
76cf5295 | 211 | .rate = 60000000, |
972c5427 | 212 | .ops = &clkops_null, |
972c5427 RN |
213 | }; |
214 | ||
215 | static struct clk xclk60motg_ck = { | |
216 | .name = "xclk60motg_ck", | |
217 | .rate = 60000000, | |
218 | .ops = &clkops_null, | |
972c5427 RN |
219 | }; |
220 | ||
221 | /* Module clocks and DPLL outputs */ | |
222 | ||
76cf5295 RN |
223 | static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { |
224 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
225 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
226 | { .parent = NULL }, |
227 | }; | |
228 | ||
76cf5295 RN |
229 | static struct clk abe_dpll_bypass_clk_mux_ck = { |
230 | .name = "abe_dpll_bypass_clk_mux_ck", | |
972c5427 | 231 | .parent = &sys_clkin_ck, |
972c5427 | 232 | .ops = &clkops_null, |
76cf5295 | 233 | .recalc = &followparent_recalc, |
972c5427 RN |
234 | }; |
235 | ||
236 | static struct clk abe_dpll_refclk_mux_ck = { | |
237 | .name = "abe_dpll_refclk_mux_ck", | |
76cf5295 RN |
238 | .parent = &sys_clkin_ck, |
239 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
972c5427 RN |
240 | .init = &omap2_init_clksel_parent, |
241 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, | |
242 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
243 | .ops = &clkops_null, | |
244 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
245 | }; |
246 | ||
247 | /* DPLL_ABE */ | |
248 | static struct dpll_data dpll_abe_dd = { | |
249 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | |
76cf5295 | 250 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, |
972c5427 RN |
251 | .clk_ref = &abe_dpll_refclk_mux_ck, |
252 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | |
253 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
254 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | |
255 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | |
256 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
257 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
258 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
259 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
260 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
261 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
262 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
263 | .min_divider = 1, | |
264 | }; | |
265 | ||
266 | ||
267 | static struct clk dpll_abe_ck = { | |
268 | .name = "dpll_abe_ck", | |
269 | .parent = &abe_dpll_refclk_mux_ck, | |
270 | .dpll_data = &dpll_abe_dd, | |
911bd739 | 271 | .init = &omap2_init_dpll_parent, |
657ebfad | 272 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
273 | .recalc = &omap3_dpll_recalc, |
274 | .round_rate = &omap2_dpll_round_rate, | |
275 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
276 | }; |
277 | ||
032b5a7e TG |
278 | static struct clk dpll_abe_x2_ck = { |
279 | .name = "dpll_abe_x2_ck", | |
280 | .parent = &dpll_abe_ck, | |
281 | .ops = &clkops_null, | |
282 | .recalc = &omap3_clkoutx2_recalc, | |
283 | }; | |
284 | ||
285 | static const struct clksel_rate div31_1to31_rates[] = { | |
286 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | |
287 | { .div = 2, .val = 2, .flags = RATE_IN_4430 }, | |
288 | { .div = 3, .val = 3, .flags = RATE_IN_4430 }, | |
289 | { .div = 4, .val = 4, .flags = RATE_IN_4430 }, | |
290 | { .div = 5, .val = 5, .flags = RATE_IN_4430 }, | |
291 | { .div = 6, .val = 6, .flags = RATE_IN_4430 }, | |
292 | { .div = 7, .val = 7, .flags = RATE_IN_4430 }, | |
293 | { .div = 8, .val = 8, .flags = RATE_IN_4430 }, | |
294 | { .div = 9, .val = 9, .flags = RATE_IN_4430 }, | |
295 | { .div = 10, .val = 10, .flags = RATE_IN_4430 }, | |
296 | { .div = 11, .val = 11, .flags = RATE_IN_4430 }, | |
297 | { .div = 12, .val = 12, .flags = RATE_IN_4430 }, | |
298 | { .div = 13, .val = 13, .flags = RATE_IN_4430 }, | |
299 | { .div = 14, .val = 14, .flags = RATE_IN_4430 }, | |
300 | { .div = 15, .val = 15, .flags = RATE_IN_4430 }, | |
301 | { .div = 16, .val = 16, .flags = RATE_IN_4430 }, | |
302 | { .div = 17, .val = 17, .flags = RATE_IN_4430 }, | |
303 | { .div = 18, .val = 18, .flags = RATE_IN_4430 }, | |
304 | { .div = 19, .val = 19, .flags = RATE_IN_4430 }, | |
305 | { .div = 20, .val = 20, .flags = RATE_IN_4430 }, | |
306 | { .div = 21, .val = 21, .flags = RATE_IN_4430 }, | |
307 | { .div = 22, .val = 22, .flags = RATE_IN_4430 }, | |
308 | { .div = 23, .val = 23, .flags = RATE_IN_4430 }, | |
309 | { .div = 24, .val = 24, .flags = RATE_IN_4430 }, | |
310 | { .div = 25, .val = 25, .flags = RATE_IN_4430 }, | |
311 | { .div = 26, .val = 26, .flags = RATE_IN_4430 }, | |
312 | { .div = 27, .val = 27, .flags = RATE_IN_4430 }, | |
313 | { .div = 28, .val = 28, .flags = RATE_IN_4430 }, | |
314 | { .div = 29, .val = 29, .flags = RATE_IN_4430 }, | |
315 | { .div = 30, .val = 30, .flags = RATE_IN_4430 }, | |
316 | { .div = 31, .val = 31, .flags = RATE_IN_4430 }, | |
317 | { .div = 0 }, | |
318 | }; | |
319 | ||
320 | static const struct clksel dpll_abe_m2x2_div[] = { | |
321 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, | |
322 | { .parent = NULL }, | |
323 | }; | |
324 | ||
972c5427 RN |
325 | static struct clk dpll_abe_m2x2_ck = { |
326 | .name = "dpll_abe_m2x2_ck", | |
032b5a7e TG |
327 | .parent = &dpll_abe_x2_ck, |
328 | .clksel = dpll_abe_m2x2_div, | |
329 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | |
330 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
972c5427 | 331 | .ops = &clkops_null, |
032b5a7e TG |
332 | .recalc = &omap2_clksel_recalc, |
333 | .round_rate = &omap2_clksel_round_rate, | |
334 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
335 | }; |
336 | ||
337 | static struct clk abe_24m_fclk = { | |
338 | .name = "abe_24m_fclk", | |
339 | .parent = &dpll_abe_m2x2_ck, | |
340 | .ops = &clkops_null, | |
341 | .recalc = &followparent_recalc, | |
972c5427 RN |
342 | }; |
343 | ||
344 | static const struct clksel_rate div3_1to4_rates[] = { | |
345 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
346 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
347 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
348 | { .div = 0 }, | |
349 | }; | |
350 | ||
351 | static const struct clksel abe_clk_div[] = { | |
352 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, | |
353 | { .parent = NULL }, | |
354 | }; | |
355 | ||
356 | static struct clk abe_clk = { | |
357 | .name = "abe_clk", | |
358 | .parent = &dpll_abe_m2x2_ck, | |
359 | .clksel = abe_clk_div, | |
360 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, | |
361 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, | |
362 | .ops = &clkops_null, | |
363 | .recalc = &omap2_clksel_recalc, | |
364 | .round_rate = &omap2_clksel_round_rate, | |
365 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
366 | }; |
367 | ||
76cf5295 RN |
368 | static const struct clksel_rate div2_1to2_rates[] = { |
369 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
370 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
371 | { .div = 0 }, | |
372 | }; | |
373 | ||
972c5427 RN |
374 | static const struct clksel aess_fclk_div[] = { |
375 | { .parent = &abe_clk, .rates = div2_1to2_rates }, | |
376 | { .parent = NULL }, | |
377 | }; | |
378 | ||
379 | static struct clk aess_fclk = { | |
380 | .name = "aess_fclk", | |
381 | .parent = &abe_clk, | |
382 | .clksel = aess_fclk_div, | |
383 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
384 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, | |
385 | .ops = &clkops_null, | |
386 | .recalc = &omap2_clksel_recalc, | |
387 | .round_rate = &omap2_clksel_round_rate, | |
388 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
389 | }; |
390 | ||
032b5a7e TG |
391 | static struct clk dpll_abe_m3x2_ck = { |
392 | .name = "dpll_abe_m3x2_ck", | |
393 | .parent = &dpll_abe_x2_ck, | |
394 | .clksel = dpll_abe_m2x2_div, | |
972c5427 RN |
395 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
396 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
397 | .ops = &clkops_null, | |
398 | .recalc = &omap2_clksel_recalc, | |
399 | .round_rate = &omap2_clksel_round_rate, | |
400 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
401 | }; |
402 | ||
403 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 404 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
032b5a7e | 405 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
406 | { .parent = NULL }, |
407 | }; | |
408 | ||
409 | static struct clk core_hsd_byp_clk_mux_ck = { | |
410 | .name = "core_hsd_byp_clk_mux_ck", | |
76cf5295 | 411 | .parent = &sys_clkin_ck, |
972c5427 RN |
412 | .clksel = core_hsd_byp_clk_mux_sel, |
413 | .init = &omap2_init_clksel_parent, | |
414 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
415 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
416 | .ops = &clkops_null, | |
417 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
418 | }; |
419 | ||
420 | /* DPLL_CORE */ | |
421 | static struct dpll_data dpll_core_dd = { | |
422 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
423 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | |
76cf5295 | 424 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
425 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, |
426 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
427 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | |
428 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | |
429 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
430 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
431 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
432 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
433 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
434 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
435 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
436 | .min_divider = 1, | |
437 | }; | |
438 | ||
439 | ||
440 | static struct clk dpll_core_ck = { | |
441 | .name = "dpll_core_ck", | |
76cf5295 | 442 | .parent = &sys_clkin_ck, |
972c5427 | 443 | .dpll_data = &dpll_core_dd, |
911bd739 | 444 | .init = &omap2_init_dpll_parent, |
972c5427 RN |
445 | .ops = &clkops_null, |
446 | .recalc = &omap3_dpll_recalc, | |
972c5427 RN |
447 | }; |
448 | ||
032b5a7e TG |
449 | static struct clk dpll_core_x2_ck = { |
450 | .name = "dpll_core_x2_ck", | |
451 | .parent = &dpll_core_ck, | |
452 | .ops = &clkops_null, | |
453 | .recalc = &omap3_clkoutx2_recalc, | |
454 | }; | |
455 | ||
456 | static const struct clksel dpll_core_m6x2_div[] = { | |
457 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
458 | { .parent = NULL }, |
459 | }; | |
460 | ||
032b5a7e TG |
461 | static struct clk dpll_core_m6x2_ck = { |
462 | .name = "dpll_core_m6x2_ck", | |
463 | .parent = &dpll_core_x2_ck, | |
464 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
465 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
466 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
467 | .ops = &clkops_null, | |
468 | .recalc = &omap2_clksel_recalc, | |
469 | .round_rate = &omap2_clksel_round_rate, | |
470 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
471 | }; |
472 | ||
473 | static const struct clksel dbgclk_mux_sel[] = { | |
474 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 475 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
476 | { .parent = NULL }, |
477 | }; | |
478 | ||
479 | static struct clk dbgclk_mux_ck = { | |
480 | .name = "dbgclk_mux_ck", | |
481 | .parent = &sys_clkin_ck, | |
482 | .ops = &clkops_null, | |
483 | .recalc = &followparent_recalc, | |
972c5427 RN |
484 | }; |
485 | ||
032b5a7e TG |
486 | static const struct clksel dpll_core_m2_div[] = { |
487 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | |
488 | { .parent = NULL }, | |
489 | }; | |
490 | ||
972c5427 RN |
491 | static struct clk dpll_core_m2_ck = { |
492 | .name = "dpll_core_m2_ck", | |
493 | .parent = &dpll_core_ck, | |
032b5a7e | 494 | .clksel = dpll_core_m2_div, |
972c5427 RN |
495 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
496 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
497 | .ops = &clkops_null, | |
498 | .recalc = &omap2_clksel_recalc, | |
499 | .round_rate = &omap2_clksel_round_rate, | |
500 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
501 | }; |
502 | ||
503 | static struct clk ddrphy_ck = { | |
504 | .name = "ddrphy_ck", | |
505 | .parent = &dpll_core_m2_ck, | |
506 | .ops = &clkops_null, | |
507 | .recalc = &followparent_recalc, | |
972c5427 RN |
508 | }; |
509 | ||
032b5a7e TG |
510 | static struct clk dpll_core_m5x2_ck = { |
511 | .name = "dpll_core_m5x2_ck", | |
512 | .parent = &dpll_core_x2_ck, | |
513 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
514 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
515 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
516 | .ops = &clkops_null, | |
517 | .recalc = &omap2_clksel_recalc, | |
518 | .round_rate = &omap2_clksel_round_rate, | |
519 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
520 | }; |
521 | ||
522 | static const struct clksel div_core_div[] = { | |
032b5a7e | 523 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
972c5427 RN |
524 | { .parent = NULL }, |
525 | }; | |
526 | ||
527 | static struct clk div_core_ck = { | |
528 | .name = "div_core_ck", | |
032b5a7e | 529 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
530 | .clksel = div_core_div, |
531 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
532 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, | |
533 | .ops = &clkops_null, | |
534 | .recalc = &omap2_clksel_recalc, | |
535 | .round_rate = &omap2_clksel_round_rate, | |
536 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
537 | }; |
538 | ||
539 | static const struct clksel_rate div4_1to8_rates[] = { | |
540 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
541 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
542 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
543 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, | |
544 | { .div = 0 }, | |
545 | }; | |
546 | ||
547 | static const struct clksel div_iva_hs_clk_div[] = { | |
032b5a7e | 548 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
972c5427 RN |
549 | { .parent = NULL }, |
550 | }; | |
551 | ||
552 | static struct clk div_iva_hs_clk = { | |
553 | .name = "div_iva_hs_clk", | |
032b5a7e | 554 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
555 | .clksel = div_iva_hs_clk_div, |
556 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, | |
557 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
558 | .ops = &clkops_null, | |
559 | .recalc = &omap2_clksel_recalc, | |
560 | .round_rate = &omap2_clksel_round_rate, | |
561 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
562 | }; |
563 | ||
564 | static struct clk div_mpu_hs_clk = { | |
565 | .name = "div_mpu_hs_clk", | |
032b5a7e | 566 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
567 | .clksel = div_iva_hs_clk_div, |
568 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, | |
569 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
570 | .ops = &clkops_null, | |
571 | .recalc = &omap2_clksel_recalc, | |
572 | .round_rate = &omap2_clksel_round_rate, | |
573 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
574 | }; |
575 | ||
032b5a7e TG |
576 | static struct clk dpll_core_m4x2_ck = { |
577 | .name = "dpll_core_m4x2_ck", | |
578 | .parent = &dpll_core_x2_ck, | |
579 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
580 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
581 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
582 | .ops = &clkops_null, | |
583 | .recalc = &omap2_clksel_recalc, | |
584 | .round_rate = &omap2_clksel_round_rate, | |
585 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
586 | }; |
587 | ||
588 | static struct clk dll_clk_div_ck = { | |
589 | .name = "dll_clk_div_ck", | |
032b5a7e | 590 | .parent = &dpll_core_m4x2_ck, |
972c5427 RN |
591 | .ops = &clkops_null, |
592 | .recalc = &followparent_recalc, | |
972c5427 RN |
593 | }; |
594 | ||
032b5a7e TG |
595 | static const struct clksel dpll_abe_m2_div[] = { |
596 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | |
597 | { .parent = NULL }, | |
598 | }; | |
599 | ||
972c5427 RN |
600 | static struct clk dpll_abe_m2_ck = { |
601 | .name = "dpll_abe_m2_ck", | |
602 | .parent = &dpll_abe_ck, | |
032b5a7e | 603 | .clksel = dpll_abe_m2_div, |
972c5427 RN |
604 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
605 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
606 | .ops = &clkops_null, | |
607 | .recalc = &omap2_clksel_recalc, | |
608 | .round_rate = &omap2_clksel_round_rate, | |
609 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
610 | }; |
611 | ||
032b5a7e TG |
612 | static struct clk dpll_core_m3x2_ck = { |
613 | .name = "dpll_core_m3x2_ck", | |
614 | .parent = &dpll_core_x2_ck, | |
615 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
616 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
617 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
618 | .ops = &clkops_null, | |
619 | .recalc = &omap2_clksel_recalc, | |
620 | .round_rate = &omap2_clksel_round_rate, | |
621 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
622 | }; |
623 | ||
032b5a7e TG |
624 | static struct clk dpll_core_m7x2_ck = { |
625 | .name = "dpll_core_m7x2_ck", | |
626 | .parent = &dpll_core_x2_ck, | |
627 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
628 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
629 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
630 | .ops = &clkops_null, | |
631 | .recalc = &omap2_clksel_recalc, | |
632 | .round_rate = &omap2_clksel_round_rate, | |
633 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
634 | }; |
635 | ||
636 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 637 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
638 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, |
639 | { .parent = NULL }, | |
640 | }; | |
641 | ||
642 | static struct clk iva_hsd_byp_clk_mux_ck = { | |
643 | .name = "iva_hsd_byp_clk_mux_ck", | |
76cf5295 | 644 | .parent = &sys_clkin_ck, |
768ab94f JB |
645 | .clksel = iva_hsd_byp_clk_mux_sel, |
646 | .init = &omap2_init_clksel_parent, | |
647 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
648 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
972c5427 | 649 | .ops = &clkops_null, |
768ab94f | 650 | .recalc = &omap2_clksel_recalc, |
972c5427 RN |
651 | }; |
652 | ||
653 | /* DPLL_IVA */ | |
654 | static struct dpll_data dpll_iva_dd = { | |
655 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
656 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | |
76cf5295 | 657 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
658 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, |
659 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
660 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | |
661 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | |
662 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
663 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
664 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
665 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
666 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
667 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
668 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
669 | .min_divider = 1, | |
670 | }; | |
671 | ||
672 | ||
673 | static struct clk dpll_iva_ck = { | |
674 | .name = "dpll_iva_ck", | |
76cf5295 | 675 | .parent = &sys_clkin_ck, |
972c5427 | 676 | .dpll_data = &dpll_iva_dd, |
911bd739 | 677 | .init = &omap2_init_dpll_parent, |
657ebfad | 678 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
679 | .recalc = &omap3_dpll_recalc, |
680 | .round_rate = &omap2_dpll_round_rate, | |
681 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
682 | }; |
683 | ||
032b5a7e TG |
684 | static struct clk dpll_iva_x2_ck = { |
685 | .name = "dpll_iva_x2_ck", | |
686 | .parent = &dpll_iva_ck, | |
687 | .ops = &clkops_null, | |
688 | .recalc = &omap3_clkoutx2_recalc, | |
689 | }; | |
690 | ||
691 | static const struct clksel dpll_iva_m4x2_div[] = { | |
692 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
693 | { .parent = NULL }, |
694 | }; | |
695 | ||
032b5a7e TG |
696 | static struct clk dpll_iva_m4x2_ck = { |
697 | .name = "dpll_iva_m4x2_ck", | |
698 | .parent = &dpll_iva_x2_ck, | |
699 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
700 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
701 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
702 | .ops = &clkops_null, | |
703 | .recalc = &omap2_clksel_recalc, | |
704 | .round_rate = &omap2_clksel_round_rate, | |
705 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
706 | }; |
707 | ||
032b5a7e TG |
708 | static struct clk dpll_iva_m5x2_ck = { |
709 | .name = "dpll_iva_m5x2_ck", | |
710 | .parent = &dpll_iva_x2_ck, | |
711 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
712 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
713 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
714 | .ops = &clkops_null, | |
715 | .recalc = &omap2_clksel_recalc, | |
716 | .round_rate = &omap2_clksel_round_rate, | |
717 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
718 | }; |
719 | ||
720 | /* DPLL_MPU */ | |
721 | static struct dpll_data dpll_mpu_dd = { | |
722 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | |
723 | .clk_bypass = &div_mpu_hs_clk, | |
76cf5295 | 724 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
725 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, |
726 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
727 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | |
728 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | |
729 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
730 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
731 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
732 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
733 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
734 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
735 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
736 | .min_divider = 1, | |
737 | }; | |
738 | ||
739 | ||
740 | static struct clk dpll_mpu_ck = { | |
741 | .name = "dpll_mpu_ck", | |
76cf5295 | 742 | .parent = &sys_clkin_ck, |
972c5427 | 743 | .dpll_data = &dpll_mpu_dd, |
911bd739 | 744 | .init = &omap2_init_dpll_parent, |
657ebfad | 745 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
746 | .recalc = &omap3_dpll_recalc, |
747 | .round_rate = &omap2_dpll_round_rate, | |
748 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
749 | }; |
750 | ||
751 | static const struct clksel dpll_mpu_m2_div[] = { | |
752 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, | |
753 | { .parent = NULL }, | |
754 | }; | |
755 | ||
756 | static struct clk dpll_mpu_m2_ck = { | |
757 | .name = "dpll_mpu_m2_ck", | |
758 | .parent = &dpll_mpu_ck, | |
759 | .clksel = dpll_mpu_m2_div, | |
760 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, | |
761 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
762 | .ops = &clkops_null, | |
763 | .recalc = &omap2_clksel_recalc, | |
764 | .round_rate = &omap2_clksel_round_rate, | |
765 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
766 | }; |
767 | ||
768 | static struct clk per_hs_clk_div_ck = { | |
769 | .name = "per_hs_clk_div_ck", | |
032b5a7e | 770 | .parent = &dpll_abe_m3x2_ck, |
972c5427 RN |
771 | .ops = &clkops_null, |
772 | .recalc = &followparent_recalc, | |
972c5427 RN |
773 | }; |
774 | ||
775 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 776 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
777 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, |
778 | { .parent = NULL }, | |
779 | }; | |
780 | ||
781 | static struct clk per_hsd_byp_clk_mux_ck = { | |
782 | .name = "per_hsd_byp_clk_mux_ck", | |
76cf5295 | 783 | .parent = &sys_clkin_ck, |
972c5427 RN |
784 | .clksel = per_hsd_byp_clk_mux_sel, |
785 | .init = &omap2_init_clksel_parent, | |
786 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
787 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
788 | .ops = &clkops_null, | |
789 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
790 | }; |
791 | ||
792 | /* DPLL_PER */ | |
793 | static struct dpll_data dpll_per_dd = { | |
794 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
795 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | |
76cf5295 | 796 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
797 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, |
798 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
799 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | |
800 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | |
801 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
802 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
803 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
804 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
805 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
806 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
807 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
808 | .min_divider = 1, | |
809 | }; | |
810 | ||
811 | ||
812 | static struct clk dpll_per_ck = { | |
813 | .name = "dpll_per_ck", | |
76cf5295 | 814 | .parent = &sys_clkin_ck, |
972c5427 | 815 | .dpll_data = &dpll_per_dd, |
911bd739 | 816 | .init = &omap2_init_dpll_parent, |
657ebfad | 817 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
818 | .recalc = &omap3_dpll_recalc, |
819 | .round_rate = &omap2_dpll_round_rate, | |
820 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
821 | }; |
822 | ||
823 | static const struct clksel dpll_per_m2_div[] = { | |
824 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, | |
825 | { .parent = NULL }, | |
826 | }; | |
827 | ||
828 | static struct clk dpll_per_m2_ck = { | |
829 | .name = "dpll_per_m2_ck", | |
830 | .parent = &dpll_per_ck, | |
831 | .clksel = dpll_per_m2_div, | |
832 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
833 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
834 | .ops = &clkops_null, | |
835 | .recalc = &omap2_clksel_recalc, | |
836 | .round_rate = &omap2_clksel_round_rate, | |
837 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
838 | }; |
839 | ||
032b5a7e TG |
840 | static struct clk dpll_per_x2_ck = { |
841 | .name = "dpll_per_x2_ck", | |
842 | .parent = &dpll_per_ck, | |
843 | .ops = &clkops_null, | |
844 | .recalc = &omap3_clkoutx2_recalc, | |
845 | }; | |
846 | ||
847 | static const struct clksel dpll_per_m2x2_div[] = { | |
848 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | |
849 | { .parent = NULL }, | |
850 | }; | |
851 | ||
972c5427 RN |
852 | static struct clk dpll_per_m2x2_ck = { |
853 | .name = "dpll_per_m2x2_ck", | |
032b5a7e TG |
854 | .parent = &dpll_per_x2_ck, |
855 | .clksel = dpll_per_m2x2_div, | |
856 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
857 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
972c5427 | 858 | .ops = &clkops_null, |
032b5a7e TG |
859 | .recalc = &omap2_clksel_recalc, |
860 | .round_rate = &omap2_clksel_round_rate, | |
861 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
862 | }; |
863 | ||
032b5a7e TG |
864 | static struct clk dpll_per_m3x2_ck = { |
865 | .name = "dpll_per_m3x2_ck", | |
866 | .parent = &dpll_per_x2_ck, | |
867 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
868 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
869 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
870 | .ops = &clkops_null, | |
871 | .recalc = &omap2_clksel_recalc, | |
872 | .round_rate = &omap2_clksel_round_rate, | |
873 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
874 | }; |
875 | ||
032b5a7e TG |
876 | static struct clk dpll_per_m4x2_ck = { |
877 | .name = "dpll_per_m4x2_ck", | |
878 | .parent = &dpll_per_x2_ck, | |
879 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
880 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
881 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
882 | .ops = &clkops_null, | |
883 | .recalc = &omap2_clksel_recalc, | |
884 | .round_rate = &omap2_clksel_round_rate, | |
885 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
886 | }; |
887 | ||
032b5a7e TG |
888 | static struct clk dpll_per_m5x2_ck = { |
889 | .name = "dpll_per_m5x2_ck", | |
890 | .parent = &dpll_per_x2_ck, | |
891 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
892 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
893 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
894 | .ops = &clkops_null, | |
895 | .recalc = &omap2_clksel_recalc, | |
896 | .round_rate = &omap2_clksel_round_rate, | |
897 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
898 | }; |
899 | ||
032b5a7e TG |
900 | static struct clk dpll_per_m6x2_ck = { |
901 | .name = "dpll_per_m6x2_ck", | |
902 | .parent = &dpll_per_x2_ck, | |
903 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
904 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
905 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
906 | .ops = &clkops_null, | |
907 | .recalc = &omap2_clksel_recalc, | |
908 | .round_rate = &omap2_clksel_round_rate, | |
909 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
910 | }; |
911 | ||
032b5a7e TG |
912 | static struct clk dpll_per_m7x2_ck = { |
913 | .name = "dpll_per_m7x2_ck", | |
914 | .parent = &dpll_per_x2_ck, | |
915 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
916 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
917 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
918 | .ops = &clkops_null, | |
919 | .recalc = &omap2_clksel_recalc, | |
920 | .round_rate = &omap2_clksel_round_rate, | |
921 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
922 | }; |
923 | ||
924 | /* DPLL_UNIPRO */ | |
925 | static struct dpll_data dpll_unipro_dd = { | |
926 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, | |
76cf5295 RN |
927 | .clk_bypass = &sys_clkin_ck, |
928 | .clk_ref = &sys_clkin_ck, | |
972c5427 RN |
929 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, |
930 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
931 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, | |
932 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, | |
933 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
934 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
935 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
936 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
937 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
938 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
939 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
940 | .min_divider = 1, | |
941 | }; | |
942 | ||
943 | ||
944 | static struct clk dpll_unipro_ck = { | |
945 | .name = "dpll_unipro_ck", | |
76cf5295 | 946 | .parent = &sys_clkin_ck, |
972c5427 | 947 | .dpll_data = &dpll_unipro_dd, |
911bd739 | 948 | .init = &omap2_init_dpll_parent, |
657ebfad | 949 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
950 | .recalc = &omap3_dpll_recalc, |
951 | .round_rate = &omap2_dpll_round_rate, | |
952 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
953 | }; |
954 | ||
032b5a7e TG |
955 | static struct clk dpll_unipro_x2_ck = { |
956 | .name = "dpll_unipro_x2_ck", | |
957 | .parent = &dpll_unipro_ck, | |
958 | .ops = &clkops_null, | |
959 | .recalc = &omap3_clkoutx2_recalc, | |
960 | }; | |
961 | ||
972c5427 | 962 | static const struct clksel dpll_unipro_m2x2_div[] = { |
032b5a7e | 963 | { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, |
972c5427 RN |
964 | { .parent = NULL }, |
965 | }; | |
966 | ||
967 | static struct clk dpll_unipro_m2x2_ck = { | |
968 | .name = "dpll_unipro_m2x2_ck", | |
032b5a7e | 969 | .parent = &dpll_unipro_x2_ck, |
972c5427 RN |
970 | .clksel = dpll_unipro_m2x2_div, |
971 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, | |
972 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
973 | .ops = &clkops_null, | |
974 | .recalc = &omap2_clksel_recalc, | |
975 | .round_rate = &omap2_clksel_round_rate, | |
976 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
977 | }; |
978 | ||
979 | static struct clk usb_hs_clk_div_ck = { | |
980 | .name = "usb_hs_clk_div_ck", | |
032b5a7e | 981 | .parent = &dpll_abe_m3x2_ck, |
972c5427 RN |
982 | .ops = &clkops_null, |
983 | .recalc = &followparent_recalc, | |
972c5427 RN |
984 | }; |
985 | ||
986 | /* DPLL_USB */ | |
987 | static struct dpll_data dpll_usb_dd = { | |
988 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | |
989 | .clk_bypass = &usb_hs_clk_div_ck, | |
0e433271 | 990 | .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, |
76cf5295 | 991 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
992 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
993 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
994 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | |
995 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | |
996 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
997 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
998 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
999 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
1000 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
1001 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
1002 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
1003 | .min_divider = 1, | |
1004 | }; | |
1005 | ||
1006 | ||
1007 | static struct clk dpll_usb_ck = { | |
1008 | .name = "dpll_usb_ck", | |
76cf5295 | 1009 | .parent = &sys_clkin_ck, |
972c5427 | 1010 | .dpll_data = &dpll_usb_dd, |
911bd739 | 1011 | .init = &omap2_init_dpll_parent, |
657ebfad | 1012 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
1013 | .recalc = &omap3_dpll_recalc, |
1014 | .round_rate = &omap2_dpll_round_rate, | |
1015 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
1016 | }; |
1017 | ||
1018 | static struct clk dpll_usb_clkdcoldo_ck = { | |
1019 | .name = "dpll_usb_clkdcoldo_ck", | |
1020 | .parent = &dpll_usb_ck, | |
1021 | .ops = &clkops_null, | |
1022 | .recalc = &followparent_recalc, | |
972c5427 RN |
1023 | }; |
1024 | ||
1025 | static const struct clksel dpll_usb_m2_div[] = { | |
1026 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, | |
1027 | { .parent = NULL }, | |
1028 | }; | |
1029 | ||
1030 | static struct clk dpll_usb_m2_ck = { | |
1031 | .name = "dpll_usb_m2_ck", | |
1032 | .parent = &dpll_usb_ck, | |
1033 | .clksel = dpll_usb_m2_div, | |
1034 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, | |
1035 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, | |
1036 | .ops = &clkops_null, | |
1037 | .recalc = &omap2_clksel_recalc, | |
1038 | .round_rate = &omap2_clksel_round_rate, | |
1039 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1040 | }; |
1041 | ||
1042 | static const struct clksel ducati_clk_mux_sel[] = { | |
1043 | { .parent = &div_core_ck, .rates = div_1_0_rates }, | |
032b5a7e | 1044 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
1045 | { .parent = NULL }, |
1046 | }; | |
1047 | ||
1048 | static struct clk ducati_clk_mux_ck = { | |
1049 | .name = "ducati_clk_mux_ck", | |
1050 | .parent = &div_core_ck, | |
1051 | .clksel = ducati_clk_mux_sel, | |
1052 | .init = &omap2_init_clksel_parent, | |
1053 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, | |
1054 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1055 | .ops = &clkops_null, | |
1056 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1057 | }; |
1058 | ||
1059 | static struct clk func_12m_fclk = { | |
1060 | .name = "func_12m_fclk", | |
1061 | .parent = &dpll_per_m2x2_ck, | |
1062 | .ops = &clkops_null, | |
1063 | .recalc = &followparent_recalc, | |
972c5427 RN |
1064 | }; |
1065 | ||
1066 | static struct clk func_24m_clk = { | |
1067 | .name = "func_24m_clk", | |
1068 | .parent = &dpll_per_m2_ck, | |
1069 | .ops = &clkops_null, | |
1070 | .recalc = &followparent_recalc, | |
972c5427 RN |
1071 | }; |
1072 | ||
1073 | static struct clk func_24mc_fclk = { | |
1074 | .name = "func_24mc_fclk", | |
1075 | .parent = &dpll_per_m2x2_ck, | |
1076 | .ops = &clkops_null, | |
1077 | .recalc = &followparent_recalc, | |
972c5427 RN |
1078 | }; |
1079 | ||
1080 | static const struct clksel_rate div2_4to8_rates[] = { | |
1081 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, | |
1082 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
1083 | { .div = 0 }, | |
1084 | }; | |
1085 | ||
1086 | static const struct clksel func_48m_fclk_div[] = { | |
1087 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, | |
1088 | { .parent = NULL }, | |
1089 | }; | |
1090 | ||
1091 | static struct clk func_48m_fclk = { | |
1092 | .name = "func_48m_fclk", | |
1093 | .parent = &dpll_per_m2x2_ck, | |
1094 | .clksel = func_48m_fclk_div, | |
1095 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1096 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1097 | .ops = &clkops_null, | |
1098 | .recalc = &omap2_clksel_recalc, | |
1099 | .round_rate = &omap2_clksel_round_rate, | |
1100 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1101 | }; |
1102 | ||
1103 | static struct clk func_48mc_fclk = { | |
1104 | .name = "func_48mc_fclk", | |
1105 | .parent = &dpll_per_m2x2_ck, | |
1106 | .ops = &clkops_null, | |
1107 | .recalc = &followparent_recalc, | |
972c5427 RN |
1108 | }; |
1109 | ||
1110 | static const struct clksel_rate div2_2to4_rates[] = { | |
1111 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, | |
1112 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, | |
1113 | { .div = 0 }, | |
1114 | }; | |
1115 | ||
1116 | static const struct clksel func_64m_fclk_div[] = { | |
032b5a7e | 1117 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
972c5427 RN |
1118 | { .parent = NULL }, |
1119 | }; | |
1120 | ||
1121 | static struct clk func_64m_fclk = { | |
1122 | .name = "func_64m_fclk", | |
032b5a7e | 1123 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1124 | .clksel = func_64m_fclk_div, |
1125 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1126 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1127 | .ops = &clkops_null, | |
1128 | .recalc = &omap2_clksel_recalc, | |
1129 | .round_rate = &omap2_clksel_round_rate, | |
1130 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1131 | }; |
1132 | ||
1133 | static const struct clksel func_96m_fclk_div[] = { | |
1134 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, | |
1135 | { .parent = NULL }, | |
1136 | }; | |
1137 | ||
1138 | static struct clk func_96m_fclk = { | |
1139 | .name = "func_96m_fclk", | |
1140 | .parent = &dpll_per_m2x2_ck, | |
1141 | .clksel = func_96m_fclk_div, | |
1142 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1143 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1144 | .ops = &clkops_null, | |
1145 | .recalc = &omap2_clksel_recalc, | |
1146 | .round_rate = &omap2_clksel_round_rate, | |
1147 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1148 | }; |
1149 | ||
1150 | static const struct clksel hsmmc6_fclk_sel[] = { | |
1151 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | |
1152 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | |
1153 | { .parent = NULL }, | |
1154 | }; | |
1155 | ||
1156 | static struct clk hsmmc6_fclk = { | |
1157 | .name = "hsmmc6_fclk", | |
1158 | .parent = &func_64m_fclk, | |
1159 | .ops = &clkops_null, | |
1160 | .recalc = &followparent_recalc, | |
972c5427 RN |
1161 | }; |
1162 | ||
1163 | static const struct clksel_rate div2_1to8_rates[] = { | |
1164 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
1165 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
1166 | { .div = 0 }, | |
1167 | }; | |
1168 | ||
1169 | static const struct clksel init_60m_fclk_div[] = { | |
1170 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, | |
1171 | { .parent = NULL }, | |
1172 | }; | |
1173 | ||
1174 | static struct clk init_60m_fclk = { | |
1175 | .name = "init_60m_fclk", | |
1176 | .parent = &dpll_usb_m2_ck, | |
1177 | .clksel = init_60m_fclk_div, | |
1178 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, | |
1179 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1180 | .ops = &clkops_null, | |
1181 | .recalc = &omap2_clksel_recalc, | |
1182 | .round_rate = &omap2_clksel_round_rate, | |
1183 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1184 | }; |
1185 | ||
1186 | static const struct clksel l3_div_div[] = { | |
1187 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, | |
1188 | { .parent = NULL }, | |
1189 | }; | |
1190 | ||
1191 | static struct clk l3_div_ck = { | |
1192 | .name = "l3_div_ck", | |
1193 | .parent = &div_core_ck, | |
1194 | .clksel = l3_div_div, | |
1195 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1196 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, | |
1197 | .ops = &clkops_null, | |
1198 | .recalc = &omap2_clksel_recalc, | |
1199 | .round_rate = &omap2_clksel_round_rate, | |
1200 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1201 | }; |
1202 | ||
1203 | static const struct clksel l4_div_div[] = { | |
1204 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, | |
1205 | { .parent = NULL }, | |
1206 | }; | |
1207 | ||
1208 | static struct clk l4_div_ck = { | |
1209 | .name = "l4_div_ck", | |
1210 | .parent = &l3_div_ck, | |
1211 | .clksel = l4_div_div, | |
1212 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1213 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, | |
1214 | .ops = &clkops_null, | |
1215 | .recalc = &omap2_clksel_recalc, | |
1216 | .round_rate = &omap2_clksel_round_rate, | |
1217 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1218 | }; |
1219 | ||
1220 | static struct clk lp_clk_div_ck = { | |
1221 | .name = "lp_clk_div_ck", | |
1222 | .parent = &dpll_abe_m2x2_ck, | |
1223 | .ops = &clkops_null, | |
1224 | .recalc = &followparent_recalc, | |
972c5427 RN |
1225 | }; |
1226 | ||
1227 | static const struct clksel l4_wkup_clk_mux_sel[] = { | |
1228 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1229 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, | |
1230 | { .parent = NULL }, | |
1231 | }; | |
1232 | ||
1233 | static struct clk l4_wkup_clk_mux_ck = { | |
1234 | .name = "l4_wkup_clk_mux_ck", | |
1235 | .parent = &sys_clkin_ck, | |
1236 | .clksel = l4_wkup_clk_mux_sel, | |
1237 | .init = &omap2_init_clksel_parent, | |
1238 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, | |
1239 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1240 | .ops = &clkops_null, | |
1241 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1242 | }; |
1243 | ||
1244 | static const struct clksel per_abe_nc_fclk_div[] = { | |
1245 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, | |
1246 | { .parent = NULL }, | |
1247 | }; | |
1248 | ||
1249 | static struct clk per_abe_nc_fclk = { | |
1250 | .name = "per_abe_nc_fclk", | |
1251 | .parent = &dpll_abe_m2_ck, | |
1252 | .clksel = per_abe_nc_fclk_div, | |
1253 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1254 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1255 | .ops = &clkops_null, | |
1256 | .recalc = &omap2_clksel_recalc, | |
1257 | .round_rate = &omap2_clksel_round_rate, | |
1258 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1259 | }; |
1260 | ||
1261 | static const struct clksel mcasp2_fclk_sel[] = { | |
1262 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, | |
1263 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, | |
1264 | { .parent = NULL }, | |
1265 | }; | |
1266 | ||
1267 | static struct clk mcasp2_fclk = { | |
1268 | .name = "mcasp2_fclk", | |
1269 | .parent = &func_96m_fclk, | |
1270 | .ops = &clkops_null, | |
1271 | .recalc = &followparent_recalc, | |
972c5427 RN |
1272 | }; |
1273 | ||
1274 | static struct clk mcasp3_fclk = { | |
1275 | .name = "mcasp3_fclk", | |
1276 | .parent = &func_96m_fclk, | |
1277 | .ops = &clkops_null, | |
1278 | .recalc = &followparent_recalc, | |
972c5427 RN |
1279 | }; |
1280 | ||
1281 | static struct clk ocp_abe_iclk = { | |
1282 | .name = "ocp_abe_iclk", | |
1283 | .parent = &aess_fclk, | |
1284 | .ops = &clkops_null, | |
1285 | .recalc = &followparent_recalc, | |
972c5427 RN |
1286 | }; |
1287 | ||
1288 | static struct clk per_abe_24m_fclk = { | |
1289 | .name = "per_abe_24m_fclk", | |
1290 | .parent = &dpll_abe_m2_ck, | |
1291 | .ops = &clkops_null, | |
1292 | .recalc = &followparent_recalc, | |
972c5427 RN |
1293 | }; |
1294 | ||
1295 | static const struct clksel pmd_stm_clock_mux_sel[] = { | |
1296 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 1297 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
76cf5295 | 1298 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
972c5427 RN |
1299 | { .parent = NULL }, |
1300 | }; | |
1301 | ||
1302 | static struct clk pmd_stm_clock_mux_ck = { | |
1303 | .name = "pmd_stm_clock_mux_ck", | |
1304 | .parent = &sys_clkin_ck, | |
1305 | .ops = &clkops_null, | |
1306 | .recalc = &followparent_recalc, | |
972c5427 RN |
1307 | }; |
1308 | ||
1309 | static struct clk pmd_trace_clk_mux_ck = { | |
1310 | .name = "pmd_trace_clk_mux_ck", | |
1311 | .parent = &sys_clkin_ck, | |
1312 | .ops = &clkops_null, | |
1313 | .recalc = &followparent_recalc, | |
972c5427 RN |
1314 | }; |
1315 | ||
76cf5295 RN |
1316 | static const struct clksel syc_clk_div_div[] = { |
1317 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, | |
1318 | { .parent = NULL }, | |
1319 | }; | |
1320 | ||
972c5427 RN |
1321 | static struct clk syc_clk_div_ck = { |
1322 | .name = "syc_clk_div_ck", | |
1323 | .parent = &sys_clkin_ck, | |
76cf5295 | 1324 | .clksel = syc_clk_div_div, |
972c5427 RN |
1325 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, |
1326 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1327 | .ops = &clkops_null, | |
1328 | .recalc = &omap2_clksel_recalc, | |
1329 | .round_rate = &omap2_clksel_round_rate, | |
1330 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1331 | }; |
1332 | ||
1333 | /* Leaf clocks controlled by modules */ | |
1334 | ||
54776050 RN |
1335 | static struct clk aes1_fck = { |
1336 | .name = "aes1_fck", | |
972c5427 RN |
1337 | .ops = &clkops_omap2_dflt, |
1338 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | |
1339 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1340 | .clkdm_name = "l4_secure_clkdm", | |
1341 | .parent = &l3_div_ck, | |
1342 | .recalc = &followparent_recalc, | |
1343 | }; | |
1344 | ||
54776050 RN |
1345 | static struct clk aes2_fck = { |
1346 | .name = "aes2_fck", | |
972c5427 RN |
1347 | .ops = &clkops_omap2_dflt, |
1348 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | |
1349 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1350 | .clkdm_name = "l4_secure_clkdm", | |
1351 | .parent = &l3_div_ck, | |
1352 | .recalc = &followparent_recalc, | |
1353 | }; | |
1354 | ||
54776050 RN |
1355 | static struct clk aess_fck = { |
1356 | .name = "aess_fck", | |
972c5427 RN |
1357 | .ops = &clkops_omap2_dflt, |
1358 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
1359 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1360 | .clkdm_name = "abe_clkdm", | |
1361 | .parent = &aess_fclk, | |
1362 | .recalc = &followparent_recalc, | |
1363 | }; | |
1364 | ||
1c03f42f BC |
1365 | static struct clk bandgap_fclk = { |
1366 | .name = "bandgap_fclk", | |
1367 | .ops = &clkops_omap2_dflt, | |
1368 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
1369 | .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, | |
1370 | .clkdm_name = "l4_wkup_clkdm", | |
1371 | .parent = &sys_32k_ck, | |
1372 | .recalc = &followparent_recalc, | |
1373 | }; | |
1374 | ||
54776050 RN |
1375 | static struct clk des3des_fck = { |
1376 | .name = "des3des_fck", | |
972c5427 RN |
1377 | .ops = &clkops_omap2_dflt, |
1378 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | |
1379 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1380 | .clkdm_name = "l4_secure_clkdm", | |
1381 | .parent = &l4_div_ck, | |
1382 | .recalc = &followparent_recalc, | |
1383 | }; | |
1384 | ||
1385 | static const struct clksel dmic_sync_mux_sel[] = { | |
1386 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, | |
1387 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, | |
1388 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, | |
1389 | { .parent = NULL }, | |
1390 | }; | |
1391 | ||
1392 | static struct clk dmic_sync_mux_ck = { | |
1393 | .name = "dmic_sync_mux_ck", | |
1394 | .parent = &abe_24m_fclk, | |
1395 | .clksel = dmic_sync_mux_sel, | |
1396 | .init = &omap2_init_clksel_parent, | |
1397 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1398 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1399 | .ops = &clkops_null, | |
1400 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1401 | }; |
1402 | ||
1403 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | |
1404 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | |
1405 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1406 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1407 | { .parent = NULL }, | |
1408 | }; | |
1409 | ||
54776050 RN |
1410 | /* Merged func_dmic_abe_gfclk into dmic */ |
1411 | static struct clk dmic_fck = { | |
1412 | .name = "dmic_fck", | |
972c5427 RN |
1413 | .parent = &dmic_sync_mux_ck, |
1414 | .clksel = func_dmic_abe_gfclk_sel, | |
1415 | .init = &omap2_init_clksel_parent, | |
1416 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1417 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1418 | .ops = &clkops_omap2_dflt, | |
1419 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1420 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
1421 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1422 | .clkdm_name = "abe_clkdm", | |
1423 | }; | |
1424 | ||
0e433271 BC |
1425 | static struct clk dsp_fck = { |
1426 | .name = "dsp_fck", | |
1427 | .ops = &clkops_omap2_dflt, | |
1428 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | |
1429 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1430 | .clkdm_name = "tesla_clkdm", | |
032b5a7e | 1431 | .parent = &dpll_iva_m4x2_ck, |
0e433271 BC |
1432 | .recalc = &followparent_recalc, |
1433 | }; | |
1434 | ||
1c03f42f BC |
1435 | static struct clk dss_sys_clk = { |
1436 | .name = "dss_sys_clk", | |
1437 | .ops = &clkops_omap2_dflt, | |
1438 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1439 | .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, | |
1440 | .clkdm_name = "l3_dss_clkdm", | |
1441 | .parent = &syc_clk_div_ck, | |
1442 | .recalc = &followparent_recalc, | |
1443 | }; | |
1444 | ||
1445 | static struct clk dss_tv_clk = { | |
1446 | .name = "dss_tv_clk", | |
1447 | .ops = &clkops_omap2_dflt, | |
1448 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1449 | .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, | |
1450 | .clkdm_name = "l3_dss_clkdm", | |
1451 | .parent = &extalt_clkin_ck, | |
1452 | .recalc = &followparent_recalc, | |
1453 | }; | |
1454 | ||
1455 | static struct clk dss_dss_clk = { | |
1456 | .name = "dss_dss_clk", | |
1457 | .ops = &clkops_omap2_dflt, | |
1458 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1459 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | |
1460 | .clkdm_name = "l3_dss_clkdm", | |
032b5a7e | 1461 | .parent = &dpll_per_m5x2_ck, |
1c03f42f BC |
1462 | .recalc = &followparent_recalc, |
1463 | }; | |
1464 | ||
1465 | static struct clk dss_48mhz_clk = { | |
1466 | .name = "dss_48mhz_clk", | |
1467 | .ops = &clkops_omap2_dflt, | |
1468 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1469 | .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, | |
1470 | .clkdm_name = "l3_dss_clkdm", | |
1471 | .parent = &func_48mc_fclk, | |
1472 | .recalc = &followparent_recalc, | |
1473 | }; | |
1474 | ||
54776050 RN |
1475 | static struct clk dss_fck = { |
1476 | .name = "dss_fck", | |
972c5427 RN |
1477 | .ops = &clkops_omap2_dflt, |
1478 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1479 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1480 | .clkdm_name = "l3_dss_clkdm", | |
1481 | .parent = &l3_div_ck, | |
1482 | .recalc = &followparent_recalc, | |
1483 | }; | |
1484 | ||
0e433271 BC |
1485 | static struct clk efuse_ctrl_cust_fck = { |
1486 | .name = "efuse_ctrl_cust_fck", | |
972c5427 | 1487 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
1488 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
1489 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1490 | .clkdm_name = "l4_cefuse_clkdm", | |
1491 | .parent = &sys_clkin_ck, | |
972c5427 RN |
1492 | .recalc = &followparent_recalc, |
1493 | }; | |
1494 | ||
0e433271 BC |
1495 | static struct clk emif1_fck = { |
1496 | .name = "emif1_fck", | |
972c5427 RN |
1497 | .ops = &clkops_omap2_dflt, |
1498 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | |
1499 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1500 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1501 | .clkdm_name = "l3_emif_clkdm", |
1502 | .parent = &ddrphy_ck, | |
1503 | .recalc = &followparent_recalc, | |
1504 | }; | |
1505 | ||
0e433271 BC |
1506 | static struct clk emif2_fck = { |
1507 | .name = "emif2_fck", | |
972c5427 RN |
1508 | .ops = &clkops_omap2_dflt, |
1509 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | |
1510 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1511 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1512 | .clkdm_name = "l3_emif_clkdm", |
1513 | .parent = &ddrphy_ck, | |
1514 | .recalc = &followparent_recalc, | |
1515 | }; | |
1516 | ||
1517 | static const struct clksel fdif_fclk_div[] = { | |
032b5a7e | 1518 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
972c5427 RN |
1519 | { .parent = NULL }, |
1520 | }; | |
1521 | ||
54776050 RN |
1522 | /* Merged fdif_fclk into fdif */ |
1523 | static struct clk fdif_fck = { | |
1524 | .name = "fdif_fck", | |
032b5a7e | 1525 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1526 | .clksel = fdif_fclk_div, |
1527 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | |
1528 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, | |
1529 | .ops = &clkops_omap2_dflt, | |
1530 | .recalc = &omap2_clksel_recalc, | |
1531 | .round_rate = &omap2_clksel_round_rate, | |
1532 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1533 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
1534 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1535 | .clkdm_name = "iss_clkdm", | |
1536 | }; | |
1537 | ||
0e433271 BC |
1538 | static struct clk fpka_fck = { |
1539 | .name = "fpka_fck", | |
972c5427 | 1540 | .ops = &clkops_omap2_dflt, |
0e433271 | 1541 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
972c5427 | 1542 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 BC |
1543 | .clkdm_name = "l4_secure_clkdm", |
1544 | .parent = &l4_div_ck, | |
1545 | .recalc = &followparent_recalc, | |
972c5427 RN |
1546 | }; |
1547 | ||
1c03f42f BC |
1548 | static struct clk gpio1_dbclk = { |
1549 | .name = "gpio1_dbclk", | |
1550 | .ops = &clkops_omap2_dflt, | |
1551 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1552 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1553 | .clkdm_name = "l4_wkup_clkdm", | |
1554 | .parent = &sys_32k_ck, | |
1555 | .recalc = &followparent_recalc, | |
1556 | }; | |
1557 | ||
54776050 RN |
1558 | static struct clk gpio1_ick = { |
1559 | .name = "gpio1_ick", | |
972c5427 RN |
1560 | .ops = &clkops_omap2_dflt, |
1561 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1562 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1563 | .clkdm_name = "l4_wkup_clkdm", | |
1564 | .parent = &l4_wkup_clk_mux_ck, | |
1565 | .recalc = &followparent_recalc, | |
1566 | }; | |
1567 | ||
1c03f42f BC |
1568 | static struct clk gpio2_dbclk = { |
1569 | .name = "gpio2_dbclk", | |
1570 | .ops = &clkops_omap2_dflt, | |
1571 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1572 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1573 | .clkdm_name = "l4_per_clkdm", | |
1574 | .parent = &sys_32k_ck, | |
1575 | .recalc = &followparent_recalc, | |
1576 | }; | |
1577 | ||
54776050 RN |
1578 | static struct clk gpio2_ick = { |
1579 | .name = "gpio2_ick", | |
972c5427 RN |
1580 | .ops = &clkops_omap2_dflt, |
1581 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1582 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1583 | .clkdm_name = "l4_per_clkdm", | |
1584 | .parent = &l4_div_ck, | |
1585 | .recalc = &followparent_recalc, | |
1586 | }; | |
1587 | ||
1c03f42f BC |
1588 | static struct clk gpio3_dbclk = { |
1589 | .name = "gpio3_dbclk", | |
1590 | .ops = &clkops_omap2_dflt, | |
1591 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1592 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1593 | .clkdm_name = "l4_per_clkdm", | |
1594 | .parent = &sys_32k_ck, | |
1595 | .recalc = &followparent_recalc, | |
1596 | }; | |
1597 | ||
54776050 RN |
1598 | static struct clk gpio3_ick = { |
1599 | .name = "gpio3_ick", | |
972c5427 RN |
1600 | .ops = &clkops_omap2_dflt, |
1601 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1602 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1603 | .clkdm_name = "l4_per_clkdm", | |
1604 | .parent = &l4_div_ck, | |
1605 | .recalc = &followparent_recalc, | |
1606 | }; | |
1607 | ||
1c03f42f BC |
1608 | static struct clk gpio4_dbclk = { |
1609 | .name = "gpio4_dbclk", | |
1610 | .ops = &clkops_omap2_dflt, | |
1611 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1612 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1613 | .clkdm_name = "l4_per_clkdm", | |
1614 | .parent = &sys_32k_ck, | |
1615 | .recalc = &followparent_recalc, | |
1616 | }; | |
1617 | ||
54776050 RN |
1618 | static struct clk gpio4_ick = { |
1619 | .name = "gpio4_ick", | |
972c5427 RN |
1620 | .ops = &clkops_omap2_dflt, |
1621 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1622 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1623 | .clkdm_name = "l4_per_clkdm", | |
1624 | .parent = &l4_div_ck, | |
1625 | .recalc = &followparent_recalc, | |
1626 | }; | |
1627 | ||
1c03f42f BC |
1628 | static struct clk gpio5_dbclk = { |
1629 | .name = "gpio5_dbclk", | |
1630 | .ops = &clkops_omap2_dflt, | |
1631 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1632 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1633 | .clkdm_name = "l4_per_clkdm", | |
1634 | .parent = &sys_32k_ck, | |
1635 | .recalc = &followparent_recalc, | |
1636 | }; | |
1637 | ||
54776050 RN |
1638 | static struct clk gpio5_ick = { |
1639 | .name = "gpio5_ick", | |
972c5427 RN |
1640 | .ops = &clkops_omap2_dflt, |
1641 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1642 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1643 | .clkdm_name = "l4_per_clkdm", | |
1644 | .parent = &l4_div_ck, | |
1645 | .recalc = &followparent_recalc, | |
1646 | }; | |
1647 | ||
1c03f42f BC |
1648 | static struct clk gpio6_dbclk = { |
1649 | .name = "gpio6_dbclk", | |
1650 | .ops = &clkops_omap2_dflt, | |
1651 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1652 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1653 | .clkdm_name = "l4_per_clkdm", | |
1654 | .parent = &sys_32k_ck, | |
1655 | .recalc = &followparent_recalc, | |
1656 | }; | |
1657 | ||
54776050 RN |
1658 | static struct clk gpio6_ick = { |
1659 | .name = "gpio6_ick", | |
972c5427 RN |
1660 | .ops = &clkops_omap2_dflt, |
1661 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1662 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1663 | .clkdm_name = "l4_per_clkdm", | |
1664 | .parent = &l4_div_ck, | |
1665 | .recalc = &followparent_recalc, | |
1666 | }; | |
1667 | ||
54776050 RN |
1668 | static struct clk gpmc_ick = { |
1669 | .name = "gpmc_ick", | |
972c5427 RN |
1670 | .ops = &clkops_omap2_dflt, |
1671 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | |
1672 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1673 | .clkdm_name = "l3_2_clkdm", | |
1674 | .parent = &l3_div_ck, | |
1675 | .recalc = &followparent_recalc, | |
1676 | }; | |
1677 | ||
0e433271 | 1678 | static const struct clksel sgx_clk_mux_sel[] = { |
032b5a7e TG |
1679 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
1680 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
1681 | { .parent = NULL }, |
1682 | }; | |
1683 | ||
0e433271 BC |
1684 | /* Merged sgx_clk_mux into gpu */ |
1685 | static struct clk gpu_fck = { | |
1686 | .name = "gpu_fck", | |
032b5a7e | 1687 | .parent = &dpll_core_m7x2_ck, |
0e433271 | 1688 | .clksel = sgx_clk_mux_sel, |
972c5427 | 1689 | .init = &omap2_init_clksel_parent, |
0e433271 BC |
1690 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
1691 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | |
972c5427 RN |
1692 | .ops = &clkops_omap2_dflt, |
1693 | .recalc = &omap2_clksel_recalc, | |
0e433271 | 1694 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
972c5427 | 1695 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 | 1696 | .clkdm_name = "l3_gfx_clkdm", |
972c5427 RN |
1697 | }; |
1698 | ||
54776050 RN |
1699 | static struct clk hdq1w_fck = { |
1700 | .name = "hdq1w_fck", | |
972c5427 RN |
1701 | .ops = &clkops_omap2_dflt, |
1702 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | |
1703 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1704 | .clkdm_name = "l4_per_clkdm", | |
1705 | .parent = &func_12m_fclk, | |
1706 | .recalc = &followparent_recalc, | |
1707 | }; | |
1708 | ||
76cf5295 RN |
1709 | static const struct clksel hsi_fclk_div[] = { |
1710 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, | |
1711 | { .parent = NULL }, | |
1712 | }; | |
1713 | ||
54776050 | 1714 | /* Merged hsi_fclk into hsi */ |
0e433271 BC |
1715 | static struct clk hsi_fck = { |
1716 | .name = "hsi_fck", | |
972c5427 | 1717 | .parent = &dpll_per_m2x2_ck, |
76cf5295 | 1718 | .clksel = hsi_fclk_div, |
972c5427 RN |
1719 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1720 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, | |
1721 | .ops = &clkops_omap2_dflt, | |
1722 | .recalc = &omap2_clksel_recalc, | |
1723 | .round_rate = &omap2_clksel_round_rate, | |
1724 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1725 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1726 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1727 | .clkdm_name = "l3_init_clkdm", | |
1728 | }; | |
1729 | ||
54776050 RN |
1730 | static struct clk i2c1_fck = { |
1731 | .name = "i2c1_fck", | |
972c5427 RN |
1732 | .ops = &clkops_omap2_dflt, |
1733 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | |
1734 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1735 | .clkdm_name = "l4_per_clkdm", | |
1736 | .parent = &func_96m_fclk, | |
1737 | .recalc = &followparent_recalc, | |
1738 | }; | |
1739 | ||
54776050 RN |
1740 | static struct clk i2c2_fck = { |
1741 | .name = "i2c2_fck", | |
972c5427 RN |
1742 | .ops = &clkops_omap2_dflt, |
1743 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | |
1744 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1745 | .clkdm_name = "l4_per_clkdm", | |
1746 | .parent = &func_96m_fclk, | |
1747 | .recalc = &followparent_recalc, | |
1748 | }; | |
1749 | ||
54776050 RN |
1750 | static struct clk i2c3_fck = { |
1751 | .name = "i2c3_fck", | |
972c5427 RN |
1752 | .ops = &clkops_omap2_dflt, |
1753 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | |
1754 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1755 | .clkdm_name = "l4_per_clkdm", | |
1756 | .parent = &func_96m_fclk, | |
1757 | .recalc = &followparent_recalc, | |
1758 | }; | |
1759 | ||
54776050 RN |
1760 | static struct clk i2c4_fck = { |
1761 | .name = "i2c4_fck", | |
972c5427 RN |
1762 | .ops = &clkops_omap2_dflt, |
1763 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | |
1764 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1765 | .clkdm_name = "l4_per_clkdm", | |
1766 | .parent = &func_96m_fclk, | |
1767 | .recalc = &followparent_recalc, | |
1768 | }; | |
1769 | ||
0e433271 BC |
1770 | static struct clk ipu_fck = { |
1771 | .name = "ipu_fck", | |
1772 | .ops = &clkops_omap2_dflt, | |
1773 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | |
1774 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1775 | .clkdm_name = "ducati_clkdm", | |
1776 | .parent = &ducati_clk_mux_ck, | |
1777 | .recalc = &followparent_recalc, | |
1778 | }; | |
1779 | ||
1c03f42f BC |
1780 | static struct clk iss_ctrlclk = { |
1781 | .name = "iss_ctrlclk", | |
1782 | .ops = &clkops_omap2_dflt, | |
1783 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1784 | .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, | |
1785 | .clkdm_name = "iss_clkdm", | |
1786 | .parent = &func_96m_fclk, | |
1787 | .recalc = &followparent_recalc, | |
1788 | }; | |
1789 | ||
54776050 RN |
1790 | static struct clk iss_fck = { |
1791 | .name = "iss_fck", | |
972c5427 RN |
1792 | .ops = &clkops_omap2_dflt, |
1793 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1794 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1795 | .clkdm_name = "iss_clkdm", | |
1796 | .parent = &ducati_clk_mux_ck, | |
1797 | .recalc = &followparent_recalc, | |
1798 | }; | |
1799 | ||
0e433271 BC |
1800 | static struct clk iva_fck = { |
1801 | .name = "iva_fck", | |
972c5427 RN |
1802 | .ops = &clkops_omap2_dflt, |
1803 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | |
1804 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1805 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 1806 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
1807 | .recalc = &followparent_recalc, |
1808 | }; | |
1809 | ||
0e433271 BC |
1810 | static struct clk kbd_fck = { |
1811 | .name = "kbd_fck", | |
972c5427 RN |
1812 | .ops = &clkops_omap2_dflt, |
1813 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | |
1814 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1815 | .clkdm_name = "l4_wkup_clkdm", | |
1816 | .parent = &sys_32k_ck, | |
1817 | .recalc = &followparent_recalc, | |
1818 | }; | |
1819 | ||
0e433271 BC |
1820 | static struct clk l3_instr_ick = { |
1821 | .name = "l3_instr_ick", | |
972c5427 RN |
1822 | .ops = &clkops_omap2_dflt, |
1823 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | |
1824 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1825 | .clkdm_name = "l3_instr_clkdm", | |
1826 | .parent = &l3_div_ck, | |
1827 | .recalc = &followparent_recalc, | |
1828 | }; | |
1829 | ||
0e433271 BC |
1830 | static struct clk l3_main_3_ick = { |
1831 | .name = "l3_main_3_ick", | |
972c5427 RN |
1832 | .ops = &clkops_omap2_dflt, |
1833 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | |
1834 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1835 | .clkdm_name = "l3_instr_clkdm", | |
1836 | .parent = &l3_div_ck, | |
1837 | .recalc = &followparent_recalc, | |
1838 | }; | |
1839 | ||
1840 | static struct clk mcasp_sync_mux_ck = { | |
1841 | .name = "mcasp_sync_mux_ck", | |
1842 | .parent = &abe_24m_fclk, | |
1843 | .clksel = dmic_sync_mux_sel, | |
1844 | .init = &omap2_init_clksel_parent, | |
1845 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1846 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1847 | .ops = &clkops_null, | |
1848 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1849 | }; |
1850 | ||
1851 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |
1852 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | |
1853 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1854 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1855 | { .parent = NULL }, | |
1856 | }; | |
1857 | ||
54776050 RN |
1858 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
1859 | static struct clk mcasp_fck = { | |
1860 | .name = "mcasp_fck", | |
972c5427 RN |
1861 | .parent = &mcasp_sync_mux_ck, |
1862 | .clksel = func_mcasp_abe_gfclk_sel, | |
1863 | .init = &omap2_init_clksel_parent, | |
1864 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1865 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1866 | .ops = &clkops_omap2_dflt, | |
1867 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1868 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
1869 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1870 | .clkdm_name = "abe_clkdm", | |
1871 | }; | |
1872 | ||
1873 | static struct clk mcbsp1_sync_mux_ck = { | |
1874 | .name = "mcbsp1_sync_mux_ck", | |
1875 | .parent = &abe_24m_fclk, | |
1876 | .clksel = dmic_sync_mux_sel, | |
1877 | .init = &omap2_init_clksel_parent, | |
1878 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1879 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1880 | .ops = &clkops_null, | |
1881 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1882 | }; |
1883 | ||
1884 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | |
1885 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | |
1886 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1887 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1888 | { .parent = NULL }, | |
1889 | }; | |
1890 | ||
54776050 RN |
1891 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
1892 | static struct clk mcbsp1_fck = { | |
1893 | .name = "mcbsp1_fck", | |
972c5427 RN |
1894 | .parent = &mcbsp1_sync_mux_ck, |
1895 | .clksel = func_mcbsp1_gfclk_sel, | |
1896 | .init = &omap2_init_clksel_parent, | |
1897 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1898 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1899 | .ops = &clkops_omap2_dflt, | |
1900 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1901 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
1902 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1903 | .clkdm_name = "abe_clkdm", | |
1904 | }; | |
1905 | ||
1906 | static struct clk mcbsp2_sync_mux_ck = { | |
1907 | .name = "mcbsp2_sync_mux_ck", | |
1908 | .parent = &abe_24m_fclk, | |
1909 | .clksel = dmic_sync_mux_sel, | |
1910 | .init = &omap2_init_clksel_parent, | |
1911 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1912 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1913 | .ops = &clkops_null, | |
1914 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1915 | }; |
1916 | ||
1917 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | |
1918 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | |
1919 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1920 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1921 | { .parent = NULL }, | |
1922 | }; | |
1923 | ||
54776050 RN |
1924 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
1925 | static struct clk mcbsp2_fck = { | |
1926 | .name = "mcbsp2_fck", | |
972c5427 RN |
1927 | .parent = &mcbsp2_sync_mux_ck, |
1928 | .clksel = func_mcbsp2_gfclk_sel, | |
1929 | .init = &omap2_init_clksel_parent, | |
1930 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1931 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1932 | .ops = &clkops_omap2_dflt, | |
1933 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1934 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
1935 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1936 | .clkdm_name = "abe_clkdm", | |
1937 | }; | |
1938 | ||
1939 | static struct clk mcbsp3_sync_mux_ck = { | |
1940 | .name = "mcbsp3_sync_mux_ck", | |
1941 | .parent = &abe_24m_fclk, | |
1942 | .clksel = dmic_sync_mux_sel, | |
1943 | .init = &omap2_init_clksel_parent, | |
1944 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1945 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1946 | .ops = &clkops_null, | |
1947 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1948 | }; |
1949 | ||
1950 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | |
1951 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | |
1952 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1953 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1954 | { .parent = NULL }, | |
1955 | }; | |
1956 | ||
54776050 RN |
1957 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
1958 | static struct clk mcbsp3_fck = { | |
1959 | .name = "mcbsp3_fck", | |
972c5427 RN |
1960 | .parent = &mcbsp3_sync_mux_ck, |
1961 | .clksel = func_mcbsp3_gfclk_sel, | |
1962 | .init = &omap2_init_clksel_parent, | |
1963 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1964 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1965 | .ops = &clkops_omap2_dflt, | |
1966 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1967 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
1968 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1969 | .clkdm_name = "abe_clkdm", | |
1970 | }; | |
1971 | ||
1972 | static struct clk mcbsp4_sync_mux_ck = { | |
1973 | .name = "mcbsp4_sync_mux_ck", | |
1974 | .parent = &func_96m_fclk, | |
1975 | .clksel = mcasp2_fclk_sel, | |
1976 | .init = &omap2_init_clksel_parent, | |
1977 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1978 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1979 | .ops = &clkops_null, | |
1980 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1981 | }; |
1982 | ||
1983 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | |
1984 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | |
1985 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1986 | { .parent = NULL }, | |
1987 | }; | |
1988 | ||
54776050 RN |
1989 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
1990 | static struct clk mcbsp4_fck = { | |
1991 | .name = "mcbsp4_fck", | |
972c5427 RN |
1992 | .parent = &mcbsp4_sync_mux_ck, |
1993 | .clksel = per_mcbsp4_gfclk_sel, | |
1994 | .init = &omap2_init_clksel_parent, | |
1995 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1996 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | |
1997 | .ops = &clkops_omap2_dflt, | |
1998 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1999 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
2000 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2001 | .clkdm_name = "l4_per_clkdm", | |
2002 | }; | |
2003 | ||
0e433271 BC |
2004 | static struct clk mcpdm_fck = { |
2005 | .name = "mcpdm_fck", | |
2006 | .ops = &clkops_omap2_dflt, | |
2007 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | |
2008 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2009 | .clkdm_name = "abe_clkdm", | |
2010 | .parent = &pad_clks_ck, | |
2011 | .recalc = &followparent_recalc, | |
2012 | }; | |
2013 | ||
54776050 RN |
2014 | static struct clk mcspi1_fck = { |
2015 | .name = "mcspi1_fck", | |
972c5427 RN |
2016 | .ops = &clkops_omap2_dflt, |
2017 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | |
2018 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2019 | .clkdm_name = "l4_per_clkdm", | |
2020 | .parent = &func_48m_fclk, | |
2021 | .recalc = &followparent_recalc, | |
2022 | }; | |
2023 | ||
54776050 RN |
2024 | static struct clk mcspi2_fck = { |
2025 | .name = "mcspi2_fck", | |
972c5427 RN |
2026 | .ops = &clkops_omap2_dflt, |
2027 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | |
2028 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2029 | .clkdm_name = "l4_per_clkdm", | |
2030 | .parent = &func_48m_fclk, | |
2031 | .recalc = &followparent_recalc, | |
2032 | }; | |
2033 | ||
54776050 RN |
2034 | static struct clk mcspi3_fck = { |
2035 | .name = "mcspi3_fck", | |
972c5427 RN |
2036 | .ops = &clkops_omap2_dflt, |
2037 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | |
2038 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2039 | .clkdm_name = "l4_per_clkdm", | |
2040 | .parent = &func_48m_fclk, | |
2041 | .recalc = &followparent_recalc, | |
2042 | }; | |
2043 | ||
54776050 RN |
2044 | static struct clk mcspi4_fck = { |
2045 | .name = "mcspi4_fck", | |
972c5427 RN |
2046 | .ops = &clkops_omap2_dflt, |
2047 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | |
2048 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2049 | .clkdm_name = "l4_per_clkdm", | |
2050 | .parent = &func_48m_fclk, | |
2051 | .recalc = &followparent_recalc, | |
2052 | }; | |
2053 | ||
54776050 RN |
2054 | /* Merged hsmmc1_fclk into mmc1 */ |
2055 | static struct clk mmc1_fck = { | |
2056 | .name = "mmc1_fck", | |
972c5427 RN |
2057 | .parent = &func_64m_fclk, |
2058 | .clksel = hsmmc6_fclk_sel, | |
2059 | .init = &omap2_init_clksel_parent, | |
2060 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | |
2061 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2062 | .ops = &clkops_omap2_dflt, | |
2063 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2064 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
2065 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2066 | .clkdm_name = "l3_init_clkdm", | |
2067 | }; | |
2068 | ||
54776050 RN |
2069 | /* Merged hsmmc2_fclk into mmc2 */ |
2070 | static struct clk mmc2_fck = { | |
2071 | .name = "mmc2_fck", | |
972c5427 RN |
2072 | .parent = &func_64m_fclk, |
2073 | .clksel = hsmmc6_fclk_sel, | |
2074 | .init = &omap2_init_clksel_parent, | |
2075 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | |
2076 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2077 | .ops = &clkops_omap2_dflt, | |
2078 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2079 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
2080 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2081 | .clkdm_name = "l3_init_clkdm", | |
2082 | }; | |
2083 | ||
54776050 RN |
2084 | static struct clk mmc3_fck = { |
2085 | .name = "mmc3_fck", | |
972c5427 RN |
2086 | .ops = &clkops_omap2_dflt, |
2087 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | |
2088 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2089 | .clkdm_name = "l4_per_clkdm", | |
2090 | .parent = &func_48m_fclk, | |
2091 | .recalc = &followparent_recalc, | |
2092 | }; | |
2093 | ||
54776050 RN |
2094 | static struct clk mmc4_fck = { |
2095 | .name = "mmc4_fck", | |
972c5427 RN |
2096 | .ops = &clkops_omap2_dflt, |
2097 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | |
2098 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2099 | .clkdm_name = "l4_per_clkdm", | |
2100 | .parent = &func_48m_fclk, | |
2101 | .recalc = &followparent_recalc, | |
2102 | }; | |
2103 | ||
54776050 RN |
2104 | static struct clk mmc5_fck = { |
2105 | .name = "mmc5_fck", | |
972c5427 RN |
2106 | .ops = &clkops_omap2_dflt, |
2107 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | |
2108 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2109 | .clkdm_name = "l4_per_clkdm", | |
2110 | .parent = &func_48m_fclk, | |
2111 | .recalc = &followparent_recalc, | |
2112 | }; | |
2113 | ||
0edc9e85 BC |
2114 | static struct clk ocp2scp_usb_phy_phy_48m = { |
2115 | .name = "ocp2scp_usb_phy_phy_48m", | |
1c03f42f BC |
2116 | .ops = &clkops_omap2_dflt, |
2117 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2118 | .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, |
1c03f42f | 2119 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2120 | .parent = &func_48m_fclk, |
1c03f42f BC |
2121 | .recalc = &followparent_recalc, |
2122 | }; | |
2123 | ||
0edc9e85 BC |
2124 | static struct clk ocp2scp_usb_phy_ick = { |
2125 | .name = "ocp2scp_usb_phy_ick", | |
1c03f42f BC |
2126 | .ops = &clkops_omap2_dflt, |
2127 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2128 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
1c03f42f | 2129 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2130 | .parent = &l4_div_ck, |
1c03f42f BC |
2131 | .recalc = &followparent_recalc, |
2132 | }; | |
2133 | ||
0e433271 BC |
2134 | static struct clk ocp_wp_noc_ick = { |
2135 | .name = "ocp_wp_noc_ick", | |
972c5427 RN |
2136 | .ops = &clkops_omap2_dflt, |
2137 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | |
2138 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2139 | .clkdm_name = "l3_instr_clkdm", | |
2140 | .parent = &l3_div_ck, | |
2141 | .recalc = &followparent_recalc, | |
2142 | }; | |
2143 | ||
54776050 RN |
2144 | static struct clk rng_ick = { |
2145 | .name = "rng_ick", | |
972c5427 RN |
2146 | .ops = &clkops_omap2_dflt, |
2147 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | |
2148 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2149 | .clkdm_name = "l4_secure_clkdm", | |
2150 | .parent = &l4_div_ck, | |
2151 | .recalc = &followparent_recalc, | |
2152 | }; | |
2153 | ||
0e433271 BC |
2154 | static struct clk sha2md5_fck = { |
2155 | .name = "sha2md5_fck", | |
972c5427 RN |
2156 | .ops = &clkops_omap2_dflt, |
2157 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | |
2158 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2159 | .clkdm_name = "l4_secure_clkdm", | |
2160 | .parent = &l3_div_ck, | |
2161 | .recalc = &followparent_recalc, | |
2162 | }; | |
2163 | ||
0e433271 BC |
2164 | static struct clk sl2if_ick = { |
2165 | .name = "sl2if_ick", | |
972c5427 RN |
2166 | .ops = &clkops_omap2_dflt, |
2167 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | |
2168 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2169 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 2170 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
2171 | .recalc = &followparent_recalc, |
2172 | }; | |
2173 | ||
1c03f42f BC |
2174 | static struct clk slimbus1_fclk_1 = { |
2175 | .name = "slimbus1_fclk_1", | |
2176 | .ops = &clkops_omap2_dflt, | |
2177 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2178 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, | |
2179 | .clkdm_name = "abe_clkdm", | |
2180 | .parent = &func_24m_clk, | |
2181 | .recalc = &followparent_recalc, | |
2182 | }; | |
2183 | ||
2184 | static struct clk slimbus1_fclk_0 = { | |
2185 | .name = "slimbus1_fclk_0", | |
2186 | .ops = &clkops_omap2_dflt, | |
2187 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2188 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, | |
2189 | .clkdm_name = "abe_clkdm", | |
2190 | .parent = &abe_24m_fclk, | |
2191 | .recalc = &followparent_recalc, | |
2192 | }; | |
2193 | ||
2194 | static struct clk slimbus1_fclk_2 = { | |
2195 | .name = "slimbus1_fclk_2", | |
2196 | .ops = &clkops_omap2_dflt, | |
2197 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2198 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, | |
2199 | .clkdm_name = "abe_clkdm", | |
2200 | .parent = &pad_clks_ck, | |
2201 | .recalc = &followparent_recalc, | |
2202 | }; | |
2203 | ||
2204 | static struct clk slimbus1_slimbus_clk = { | |
2205 | .name = "slimbus1_slimbus_clk", | |
2206 | .ops = &clkops_omap2_dflt, | |
2207 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2208 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, | |
2209 | .clkdm_name = "abe_clkdm", | |
2210 | .parent = &slimbus_clk, | |
2211 | .recalc = &followparent_recalc, | |
2212 | }; | |
2213 | ||
54776050 RN |
2214 | static struct clk slimbus1_fck = { |
2215 | .name = "slimbus1_fck", | |
972c5427 RN |
2216 | .ops = &clkops_omap2_dflt, |
2217 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2218 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2219 | .clkdm_name = "abe_clkdm", | |
2220 | .parent = &ocp_abe_iclk, | |
2221 | .recalc = &followparent_recalc, | |
2222 | }; | |
2223 | ||
1c03f42f BC |
2224 | static struct clk slimbus2_fclk_1 = { |
2225 | .name = "slimbus2_fclk_1", | |
2226 | .ops = &clkops_omap2_dflt, | |
2227 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2228 | .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, | |
2229 | .clkdm_name = "l4_per_clkdm", | |
2230 | .parent = &per_abe_24m_fclk, | |
2231 | .recalc = &followparent_recalc, | |
2232 | }; | |
2233 | ||
2234 | static struct clk slimbus2_fclk_0 = { | |
2235 | .name = "slimbus2_fclk_0", | |
2236 | .ops = &clkops_omap2_dflt, | |
2237 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2238 | .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, | |
2239 | .clkdm_name = "l4_per_clkdm", | |
2240 | .parent = &func_24mc_fclk, | |
2241 | .recalc = &followparent_recalc, | |
2242 | }; | |
2243 | ||
2244 | static struct clk slimbus2_slimbus_clk = { | |
2245 | .name = "slimbus2_slimbus_clk", | |
2246 | .ops = &clkops_omap2_dflt, | |
2247 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2248 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, | |
2249 | .clkdm_name = "l4_per_clkdm", | |
2250 | .parent = &pad_slimbus_core_clks_ck, | |
2251 | .recalc = &followparent_recalc, | |
2252 | }; | |
2253 | ||
54776050 RN |
2254 | static struct clk slimbus2_fck = { |
2255 | .name = "slimbus2_fck", | |
972c5427 RN |
2256 | .ops = &clkops_omap2_dflt, |
2257 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2258 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2259 | .clkdm_name = "l4_per_clkdm", | |
2260 | .parent = &l4_div_ck, | |
2261 | .recalc = &followparent_recalc, | |
2262 | }; | |
2263 | ||
0e433271 BC |
2264 | static struct clk smartreflex_core_fck = { |
2265 | .name = "smartreflex_core_fck", | |
972c5427 RN |
2266 | .ops = &clkops_omap2_dflt, |
2267 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
2268 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2269 | .clkdm_name = "l4_ao_clkdm", | |
2270 | .parent = &l4_wkup_clk_mux_ck, | |
2271 | .recalc = &followparent_recalc, | |
2272 | }; | |
2273 | ||
0e433271 BC |
2274 | static struct clk smartreflex_iva_fck = { |
2275 | .name = "smartreflex_iva_fck", | |
972c5427 RN |
2276 | .ops = &clkops_omap2_dflt, |
2277 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
2278 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2279 | .clkdm_name = "l4_ao_clkdm", | |
2280 | .parent = &l4_wkup_clk_mux_ck, | |
2281 | .recalc = &followparent_recalc, | |
2282 | }; | |
2283 | ||
0e433271 BC |
2284 | static struct clk smartreflex_mpu_fck = { |
2285 | .name = "smartreflex_mpu_fck", | |
972c5427 RN |
2286 | .ops = &clkops_omap2_dflt, |
2287 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
2288 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2289 | .clkdm_name = "l4_ao_clkdm", | |
2290 | .parent = &l4_wkup_clk_mux_ck, | |
2291 | .recalc = &followparent_recalc, | |
2292 | }; | |
2293 | ||
0e433271 BC |
2294 | /* Merged dmt1_clk_mux into timer1 */ |
2295 | static struct clk timer1_fck = { | |
2296 | .name = "timer1_fck", | |
2297 | .parent = &sys_clkin_ck, | |
2298 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2299 | .init = &omap2_init_clksel_parent, | |
2300 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2301 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
972c5427 | 2302 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
2303 | .recalc = &omap2_clksel_recalc, |
2304 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2305 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2306 | .clkdm_name = "l4_wkup_clkdm", | |
2307 | }; | |
2308 | ||
2309 | /* Merged cm2_dm10_mux into timer10 */ | |
2310 | static struct clk timer10_fck = { | |
2311 | .name = "timer10_fck", | |
2312 | .parent = &sys_clkin_ck, | |
2313 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2314 | .init = &omap2_init_clksel_parent, | |
2315 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2316 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2317 | .ops = &clkops_omap2_dflt, | |
2318 | .recalc = &omap2_clksel_recalc, | |
2319 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2320 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2321 | .clkdm_name = "l4_per_clkdm", | |
2322 | }; | |
2323 | ||
2324 | /* Merged cm2_dm11_mux into timer11 */ | |
2325 | static struct clk timer11_fck = { | |
2326 | .name = "timer11_fck", | |
2327 | .parent = &sys_clkin_ck, | |
2328 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2329 | .init = &omap2_init_clksel_parent, | |
2330 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2331 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2332 | .ops = &clkops_omap2_dflt, | |
2333 | .recalc = &omap2_clksel_recalc, | |
2334 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2335 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2336 | .clkdm_name = "l4_per_clkdm", | |
2337 | }; | |
2338 | ||
2339 | /* Merged cm2_dm2_mux into timer2 */ | |
2340 | static struct clk timer2_fck = { | |
2341 | .name = "timer2_fck", | |
2342 | .parent = &sys_clkin_ck, | |
2343 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2344 | .init = &omap2_init_clksel_parent, | |
2345 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2346 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2347 | .ops = &clkops_omap2_dflt, | |
2348 | .recalc = &omap2_clksel_recalc, | |
2349 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2350 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2351 | .clkdm_name = "l4_per_clkdm", | |
2352 | }; | |
2353 | ||
2354 | /* Merged cm2_dm3_mux into timer3 */ | |
2355 | static struct clk timer3_fck = { | |
2356 | .name = "timer3_fck", | |
2357 | .parent = &sys_clkin_ck, | |
2358 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2359 | .init = &omap2_init_clksel_parent, | |
2360 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2361 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2362 | .ops = &clkops_omap2_dflt, | |
2363 | .recalc = &omap2_clksel_recalc, | |
2364 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2365 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2366 | .clkdm_name = "l4_per_clkdm", | |
2367 | }; | |
2368 | ||
2369 | /* Merged cm2_dm4_mux into timer4 */ | |
2370 | static struct clk timer4_fck = { | |
2371 | .name = "timer4_fck", | |
2372 | .parent = &sys_clkin_ck, | |
2373 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2374 | .init = &omap2_init_clksel_parent, | |
2375 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2376 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2377 | .ops = &clkops_omap2_dflt, | |
2378 | .recalc = &omap2_clksel_recalc, | |
2379 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2380 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2381 | .clkdm_name = "l4_per_clkdm", | |
2382 | }; | |
2383 | ||
2384 | static const struct clksel timer5_sync_mux_sel[] = { | |
2385 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | |
2386 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
2387 | { .parent = NULL }, | |
2388 | }; | |
2389 | ||
2390 | /* Merged timer5_sync_mux into timer5 */ | |
2391 | static struct clk timer5_fck = { | |
2392 | .name = "timer5_fck", | |
2393 | .parent = &syc_clk_div_ck, | |
2394 | .clksel = timer5_sync_mux_sel, | |
2395 | .init = &omap2_init_clksel_parent, | |
2396 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2397 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2398 | .ops = &clkops_omap2_dflt, | |
2399 | .recalc = &omap2_clksel_recalc, | |
2400 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2401 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2402 | .clkdm_name = "abe_clkdm", | |
2403 | }; | |
2404 | ||
2405 | /* Merged timer6_sync_mux into timer6 */ | |
2406 | static struct clk timer6_fck = { | |
2407 | .name = "timer6_fck", | |
2408 | .parent = &syc_clk_div_ck, | |
2409 | .clksel = timer5_sync_mux_sel, | |
2410 | .init = &omap2_init_clksel_parent, | |
2411 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2412 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2413 | .ops = &clkops_omap2_dflt, | |
2414 | .recalc = &omap2_clksel_recalc, | |
2415 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2416 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2417 | .clkdm_name = "abe_clkdm", | |
2418 | }; | |
2419 | ||
2420 | /* Merged timer7_sync_mux into timer7 */ | |
2421 | static struct clk timer7_fck = { | |
2422 | .name = "timer7_fck", | |
2423 | .parent = &syc_clk_div_ck, | |
2424 | .clksel = timer5_sync_mux_sel, | |
2425 | .init = &omap2_init_clksel_parent, | |
2426 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2427 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2428 | .ops = &clkops_omap2_dflt, | |
2429 | .recalc = &omap2_clksel_recalc, | |
2430 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2431 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2432 | .clkdm_name = "abe_clkdm", | |
2433 | }; | |
2434 | ||
2435 | /* Merged timer8_sync_mux into timer8 */ | |
2436 | static struct clk timer8_fck = { | |
2437 | .name = "timer8_fck", | |
2438 | .parent = &syc_clk_div_ck, | |
2439 | .clksel = timer5_sync_mux_sel, | |
2440 | .init = &omap2_init_clksel_parent, | |
2441 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2442 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2443 | .ops = &clkops_omap2_dflt, | |
2444 | .recalc = &omap2_clksel_recalc, | |
2445 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2446 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2447 | .clkdm_name = "abe_clkdm", | |
2448 | }; | |
2449 | ||
2450 | /* Merged cm2_dm9_mux into timer9 */ | |
2451 | static struct clk timer9_fck = { | |
2452 | .name = "timer9_fck", | |
2453 | .parent = &sys_clkin_ck, | |
2454 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2455 | .init = &omap2_init_clksel_parent, | |
2456 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2457 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2458 | .ops = &clkops_omap2_dflt, | |
2459 | .recalc = &omap2_clksel_recalc, | |
2460 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2461 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2462 | .clkdm_name = "l4_per_clkdm", | |
972c5427 RN |
2463 | }; |
2464 | ||
54776050 RN |
2465 | static struct clk uart1_fck = { |
2466 | .name = "uart1_fck", | |
972c5427 RN |
2467 | .ops = &clkops_omap2_dflt, |
2468 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | |
2469 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2470 | .clkdm_name = "l4_per_clkdm", | |
2471 | .parent = &func_48m_fclk, | |
2472 | .recalc = &followparent_recalc, | |
2473 | }; | |
2474 | ||
54776050 RN |
2475 | static struct clk uart2_fck = { |
2476 | .name = "uart2_fck", | |
972c5427 RN |
2477 | .ops = &clkops_omap2_dflt, |
2478 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | |
2479 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2480 | .clkdm_name = "l4_per_clkdm", | |
2481 | .parent = &func_48m_fclk, | |
2482 | .recalc = &followparent_recalc, | |
2483 | }; | |
2484 | ||
54776050 RN |
2485 | static struct clk uart3_fck = { |
2486 | .name = "uart3_fck", | |
972c5427 RN |
2487 | .ops = &clkops_omap2_dflt, |
2488 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | |
2489 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2490 | .clkdm_name = "l4_per_clkdm", | |
2491 | .parent = &func_48m_fclk, | |
2492 | .recalc = &followparent_recalc, | |
2493 | }; | |
2494 | ||
54776050 RN |
2495 | static struct clk uart4_fck = { |
2496 | .name = "uart4_fck", | |
972c5427 RN |
2497 | .ops = &clkops_omap2_dflt, |
2498 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | |
2499 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2500 | .clkdm_name = "l4_per_clkdm", | |
2501 | .parent = &func_48m_fclk, | |
2502 | .recalc = &followparent_recalc, | |
2503 | }; | |
2504 | ||
0e433271 BC |
2505 | static struct clk usb_host_fs_fck = { |
2506 | .name = "usb_host_fs_fck", | |
972c5427 | 2507 | .ops = &clkops_omap2_dflt, |
0e433271 | 2508 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
972c5427 RN |
2509 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2510 | .clkdm_name = "l3_init_clkdm", | |
0e433271 | 2511 | .parent = &func_48mc_fclk, |
972c5427 RN |
2512 | .recalc = &followparent_recalc, |
2513 | }; | |
2514 | ||
1c03f42f BC |
2515 | static const struct clksel utmi_p1_gfclk_sel[] = { |
2516 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2517 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, | |
2518 | { .parent = NULL }, | |
2519 | }; | |
2520 | ||
2521 | static struct clk utmi_p1_gfclk = { | |
2522 | .name = "utmi_p1_gfclk", | |
2523 | .parent = &init_60m_fclk, | |
2524 | .clksel = utmi_p1_gfclk_sel, | |
2525 | .init = &omap2_init_clksel_parent, | |
2526 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2527 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | |
2528 | .ops = &clkops_null, | |
2529 | .recalc = &omap2_clksel_recalc, | |
2530 | }; | |
2531 | ||
2532 | static struct clk usb_host_hs_utmi_p1_clk = { | |
2533 | .name = "usb_host_hs_utmi_p1_clk", | |
2534 | .ops = &clkops_omap2_dflt, | |
2535 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2536 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, | |
2537 | .clkdm_name = "l3_init_clkdm", | |
2538 | .parent = &utmi_p1_gfclk, | |
2539 | .recalc = &followparent_recalc, | |
2540 | }; | |
2541 | ||
2542 | static const struct clksel utmi_p2_gfclk_sel[] = { | |
2543 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2544 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, | |
2545 | { .parent = NULL }, | |
2546 | }; | |
2547 | ||
2548 | static struct clk utmi_p2_gfclk = { | |
2549 | .name = "utmi_p2_gfclk", | |
2550 | .parent = &init_60m_fclk, | |
2551 | .clksel = utmi_p2_gfclk_sel, | |
2552 | .init = &omap2_init_clksel_parent, | |
2553 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2554 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | |
2555 | .ops = &clkops_null, | |
2556 | .recalc = &omap2_clksel_recalc, | |
2557 | }; | |
2558 | ||
2559 | static struct clk usb_host_hs_utmi_p2_clk = { | |
2560 | .name = "usb_host_hs_utmi_p2_clk", | |
2561 | .ops = &clkops_omap2_dflt, | |
2562 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2563 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, | |
2564 | .clkdm_name = "l3_init_clkdm", | |
2565 | .parent = &utmi_p2_gfclk, | |
2566 | .recalc = &followparent_recalc, | |
2567 | }; | |
2568 | ||
032b5a7e TG |
2569 | static struct clk usb_host_hs_utmi_p3_clk = { |
2570 | .name = "usb_host_hs_utmi_p3_clk", | |
2571 | .ops = &clkops_omap2_dflt, | |
2572 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2573 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, | |
2574 | .clkdm_name = "l3_init_clkdm", | |
2575 | .parent = &init_60m_fclk, | |
2576 | .recalc = &followparent_recalc, | |
2577 | }; | |
2578 | ||
1c03f42f BC |
2579 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
2580 | .name = "usb_host_hs_hsic480m_p1_clk", | |
2581 | .ops = &clkops_omap2_dflt, | |
2582 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2583 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, | |
2584 | .clkdm_name = "l3_init_clkdm", | |
2585 | .parent = &dpll_usb_m2_ck, | |
2586 | .recalc = &followparent_recalc, | |
2587 | }; | |
2588 | ||
032b5a7e TG |
2589 | static struct clk usb_host_hs_hsic60m_p1_clk = { |
2590 | .name = "usb_host_hs_hsic60m_p1_clk", | |
2591 | .ops = &clkops_omap2_dflt, | |
2592 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2593 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, | |
2594 | .clkdm_name = "l3_init_clkdm", | |
2595 | .parent = &init_60m_fclk, | |
2596 | .recalc = &followparent_recalc, | |
2597 | }; | |
2598 | ||
2599 | static struct clk usb_host_hs_hsic60m_p2_clk = { | |
2600 | .name = "usb_host_hs_hsic60m_p2_clk", | |
2601 | .ops = &clkops_omap2_dflt, | |
2602 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2603 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, | |
2604 | .clkdm_name = "l3_init_clkdm", | |
2605 | .parent = &init_60m_fclk, | |
2606 | .recalc = &followparent_recalc, | |
2607 | }; | |
2608 | ||
1c03f42f BC |
2609 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
2610 | .name = "usb_host_hs_hsic480m_p2_clk", | |
2611 | .ops = &clkops_omap2_dflt, | |
2612 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2613 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, | |
2614 | .clkdm_name = "l3_init_clkdm", | |
2615 | .parent = &dpll_usb_m2_ck, | |
2616 | .recalc = &followparent_recalc, | |
2617 | }; | |
2618 | ||
2619 | static struct clk usb_host_hs_func48mclk = { | |
2620 | .name = "usb_host_hs_func48mclk", | |
2621 | .ops = &clkops_omap2_dflt, | |
2622 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2623 | .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, | |
2624 | .clkdm_name = "l3_init_clkdm", | |
2625 | .parent = &func_48mc_fclk, | |
2626 | .recalc = &followparent_recalc, | |
2627 | }; | |
2628 | ||
0e433271 BC |
2629 | static struct clk usb_host_hs_fck = { |
2630 | .name = "usb_host_hs_fck", | |
972c5427 RN |
2631 | .ops = &clkops_omap2_dflt, |
2632 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2633 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2634 | .clkdm_name = "l3_init_clkdm", | |
2635 | .parent = &init_60m_fclk, | |
2636 | .recalc = &followparent_recalc, | |
2637 | }; | |
2638 | ||
1c03f42f BC |
2639 | static const struct clksel otg_60m_gfclk_sel[] = { |
2640 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, | |
2641 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, | |
2642 | { .parent = NULL }, | |
2643 | }; | |
2644 | ||
2645 | static struct clk otg_60m_gfclk = { | |
2646 | .name = "otg_60m_gfclk", | |
2647 | .parent = &utmi_phy_clkout_ck, | |
2648 | .clksel = otg_60m_gfclk_sel, | |
2649 | .init = &omap2_init_clksel_parent, | |
2650 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2651 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | |
2652 | .ops = &clkops_null, | |
2653 | .recalc = &omap2_clksel_recalc, | |
2654 | }; | |
2655 | ||
2656 | static struct clk usb_otg_hs_xclk = { | |
2657 | .name = "usb_otg_hs_xclk", | |
2658 | .ops = &clkops_omap2_dflt, | |
2659 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2660 | .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, | |
2661 | .clkdm_name = "l3_init_clkdm", | |
2662 | .parent = &otg_60m_gfclk, | |
2663 | .recalc = &followparent_recalc, | |
2664 | }; | |
2665 | ||
0e433271 BC |
2666 | static struct clk usb_otg_hs_ick = { |
2667 | .name = "usb_otg_hs_ick", | |
972c5427 RN |
2668 | .ops = &clkops_omap2_dflt, |
2669 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2670 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2671 | .clkdm_name = "l3_init_clkdm", | |
2672 | .parent = &l3_div_ck, | |
2673 | .recalc = &followparent_recalc, | |
2674 | }; | |
2675 | ||
0edc9e85 BC |
2676 | static struct clk usb_phy_cm_clk32k = { |
2677 | .name = "usb_phy_cm_clk32k", | |
2678 | .ops = &clkops_omap2_dflt, | |
2679 | .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, | |
2680 | .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, | |
2681 | .clkdm_name = "l4_ao_clkdm", | |
2682 | .parent = &sys_32k_ck, | |
2683 | .recalc = &followparent_recalc, | |
2684 | }; | |
2685 | ||
1c03f42f BC |
2686 | static struct clk usb_tll_hs_usb_ch2_clk = { |
2687 | .name = "usb_tll_hs_usb_ch2_clk", | |
2688 | .ops = &clkops_omap2_dflt, | |
2689 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2690 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, | |
2691 | .clkdm_name = "l3_init_clkdm", | |
2692 | .parent = &init_60m_fclk, | |
2693 | .recalc = &followparent_recalc, | |
2694 | }; | |
2695 | ||
2696 | static struct clk usb_tll_hs_usb_ch0_clk = { | |
2697 | .name = "usb_tll_hs_usb_ch0_clk", | |
2698 | .ops = &clkops_omap2_dflt, | |
2699 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2700 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, | |
2701 | .clkdm_name = "l3_init_clkdm", | |
2702 | .parent = &init_60m_fclk, | |
2703 | .recalc = &followparent_recalc, | |
2704 | }; | |
2705 | ||
2706 | static struct clk usb_tll_hs_usb_ch1_clk = { | |
2707 | .name = "usb_tll_hs_usb_ch1_clk", | |
2708 | .ops = &clkops_omap2_dflt, | |
2709 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2710 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, | |
2711 | .clkdm_name = "l3_init_clkdm", | |
2712 | .parent = &init_60m_fclk, | |
2713 | .recalc = &followparent_recalc, | |
2714 | }; | |
2715 | ||
0e433271 BC |
2716 | static struct clk usb_tll_hs_ick = { |
2717 | .name = "usb_tll_hs_ick", | |
972c5427 RN |
2718 | .ops = &clkops_omap2_dflt, |
2719 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2720 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2721 | .clkdm_name = "l3_init_clkdm", | |
2722 | .parent = &l4_div_ck, | |
2723 | .recalc = &followparent_recalc, | |
2724 | }; | |
2725 | ||
0edc9e85 BC |
2726 | static const struct clksel_rate div2_14to18_rates[] = { |
2727 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, | |
2728 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, | |
2729 | { .div = 0 }, | |
2730 | }; | |
2731 | ||
2732 | static const struct clksel usim_fclk_div[] = { | |
032b5a7e | 2733 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
0edc9e85 BC |
2734 | { .parent = NULL }, |
2735 | }; | |
2736 | ||
2737 | static struct clk usim_ck = { | |
2738 | .name = "usim_ck", | |
032b5a7e | 2739 | .parent = &dpll_per_m4x2_ck, |
0edc9e85 BC |
2740 | .clksel = usim_fclk_div, |
2741 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2742 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, | |
2743 | .ops = &clkops_null, | |
2744 | .recalc = &omap2_clksel_recalc, | |
2745 | .round_rate = &omap2_clksel_round_rate, | |
2746 | .set_rate = &omap2_clksel_set_rate, | |
2747 | }; | |
2748 | ||
2749 | static struct clk usim_fclk = { | |
2750 | .name = "usim_fclk", | |
2751 | .ops = &clkops_omap2_dflt, | |
2752 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2753 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, | |
2754 | .clkdm_name = "l4_wkup_clkdm", | |
2755 | .parent = &usim_ck, | |
2756 | .recalc = &followparent_recalc, | |
2757 | }; | |
2758 | ||
0e433271 BC |
2759 | static struct clk usim_fck = { |
2760 | .name = "usim_fck", | |
972c5427 RN |
2761 | .ops = &clkops_omap2_dflt, |
2762 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
76cf5295 | 2763 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
972c5427 RN |
2764 | .clkdm_name = "l4_wkup_clkdm", |
2765 | .parent = &sys_32k_ck, | |
2766 | .recalc = &followparent_recalc, | |
2767 | }; | |
2768 | ||
0e433271 BC |
2769 | static struct clk wd_timer2_fck = { |
2770 | .name = "wd_timer2_fck", | |
972c5427 RN |
2771 | .ops = &clkops_omap2_dflt, |
2772 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | |
2773 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2774 | .clkdm_name = "l4_wkup_clkdm", | |
2775 | .parent = &sys_32k_ck, | |
2776 | .recalc = &followparent_recalc, | |
2777 | }; | |
2778 | ||
0e433271 BC |
2779 | static struct clk wd_timer3_fck = { |
2780 | .name = "wd_timer3_fck", | |
972c5427 RN |
2781 | .ops = &clkops_omap2_dflt, |
2782 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | |
2783 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2784 | .clkdm_name = "abe_clkdm", | |
2785 | .parent = &sys_32k_ck, | |
2786 | .recalc = &followparent_recalc, | |
2787 | }; | |
2788 | ||
2789 | /* Remaining optional clocks */ | |
972c5427 RN |
2790 | static const struct clksel stm_clk_div_div[] = { |
2791 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, | |
2792 | { .parent = NULL }, | |
2793 | }; | |
2794 | ||
2795 | static struct clk stm_clk_div_ck = { | |
2796 | .name = "stm_clk_div_ck", | |
2797 | .parent = &pmd_stm_clock_mux_ck, | |
2798 | .clksel = stm_clk_div_div, | |
2799 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2800 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, | |
2801 | .ops = &clkops_null, | |
2802 | .recalc = &omap2_clksel_recalc, | |
2803 | .round_rate = &omap2_clksel_round_rate, | |
2804 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2805 | }; |
2806 | ||
2807 | static const struct clksel trace_clk_div_div[] = { | |
2808 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | |
2809 | { .parent = NULL }, | |
2810 | }; | |
2811 | ||
2812 | static struct clk trace_clk_div_ck = { | |
2813 | .name = "trace_clk_div_ck", | |
2814 | .parent = &pmd_trace_clk_mux_ck, | |
2815 | .clksel = trace_clk_div_div, | |
2816 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2817 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | |
2818 | .ops = &clkops_null, | |
2819 | .recalc = &omap2_clksel_recalc, | |
2820 | .round_rate = &omap2_clksel_round_rate, | |
2821 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2822 | }; |
2823 | ||
972c5427 RN |
2824 | /* |
2825 | * clkdev | |
2826 | */ | |
2827 | ||
2828 | static struct omap_clk omap44xx_clks[] = { | |
2829 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | |
2830 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | |
2831 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | |
2832 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | |
2833 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | |
2834 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | |
2835 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | |
2836 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | |
2837 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | |
2838 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | |
2839 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | |
2840 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | |
2841 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | |
2842 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | |
76cf5295 | 2843 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), |
972c5427 RN |
2844 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), |
2845 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | |
2846 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | |
2847 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | |
76cf5295 | 2848 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
972c5427 RN |
2849 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
2850 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | |
032b5a7e | 2851 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), |
972c5427 RN |
2852 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
2853 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | |
2854 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | |
2855 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | |
032b5a7e | 2856 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
972c5427 RN |
2857 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
2858 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | |
032b5a7e TG |
2859 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
2860 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | |
972c5427 RN |
2861 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
2862 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | |
2863 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | |
032b5a7e | 2864 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
972c5427 RN |
2865 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
2866 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | |
2867 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | |
032b5a7e | 2868 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
972c5427 RN |
2869 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
2870 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | |
032b5a7e TG |
2871 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
2872 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), | |
972c5427 RN |
2873 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
2874 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | |
032b5a7e TG |
2875 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
2876 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), | |
2877 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | |
972c5427 RN |
2878 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
2879 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | |
2880 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | |
2881 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | |
2882 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | |
2883 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | |
032b5a7e | 2884 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), |
972c5427 | 2885 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
032b5a7e TG |
2886 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
2887 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), | |
2888 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), | |
2889 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), | |
2890 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), | |
972c5427 | 2891 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), |
032b5a7e | 2892 | CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), |
972c5427 RN |
2893 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), |
2894 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | |
2895 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | |
2896 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | |
2897 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | |
2898 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | |
2899 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | |
2900 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | |
2901 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | |
2902 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | |
2903 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | |
2904 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | |
2905 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | |
2906 | CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), | |
2907 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), | |
2908 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | |
2909 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | |
2910 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | |
2911 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | |
2912 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), | |
2913 | CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), | |
2914 | CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), | |
2915 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), | |
2916 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | |
2917 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | |
2918 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | |
2919 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | |
54776050 RN |
2920 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
2921 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), | |
2922 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), | |
1c03f42f | 2923 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), |
54776050 | 2924 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
972c5427 | 2925 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
54776050 | 2926 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
0e433271 | 2927 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), |
1c03f42f BC |
2928 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), |
2929 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), | |
2930 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), | |
2931 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), | |
54776050 | 2932 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
0e433271 BC |
2933 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), |
2934 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), | |
2935 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), | |
54776050 | 2936 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
0e433271 | 2937 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
1c03f42f | 2938 | CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), |
54776050 | 2939 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
1c03f42f | 2940 | CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), |
54776050 | 2941 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
1c03f42f | 2942 | CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), |
54776050 | 2943 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
1c03f42f | 2944 | CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), |
54776050 | 2945 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
1c03f42f | 2946 | CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), |
54776050 | 2947 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
1c03f42f | 2948 | CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), |
54776050 RN |
2949 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
2950 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), | |
0e433271 | 2951 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
54776050 | 2952 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
0e433271 | 2953 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
f7bb0d9a BC |
2954 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), |
2955 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), | |
2956 | CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), | |
2957 | CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), | |
0e433271 | 2958 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
1c03f42f | 2959 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
54776050 | 2960 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
0e433271 BC |
2961 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), |
2962 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), | |
2963 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), | |
2964 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), | |
972c5427 | 2965 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
54776050 | 2966 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
972c5427 | 2967 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
54776050 | 2968 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), |
972c5427 | 2969 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
54776050 | 2970 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), |
972c5427 | 2971 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
54776050 | 2972 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), |
972c5427 | 2973 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
54776050 | 2974 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), |
0e433271 | 2975 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), |
54776050 RN |
2976 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), |
2977 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), | |
2978 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), | |
2979 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), | |
2980 | CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), | |
2981 | CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), | |
2982 | CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), | |
2983 | CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), | |
2984 | CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), | |
1c03f42f | 2985 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), |
0edc9e85 | 2986 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), |
0e433271 | 2987 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), |
54776050 | 2988 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
0e433271 BC |
2989 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
2990 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), | |
1c03f42f BC |
2991 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
2992 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | |
2993 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), | |
2994 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), | |
54776050 | 2995 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
1c03f42f BC |
2996 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), |
2997 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), | |
2998 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), | |
54776050 | 2999 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
0e433271 BC |
3000 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), |
3001 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), | |
3002 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), | |
3003 | CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), | |
3004 | CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), | |
3005 | CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), | |
3006 | CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), | |
3007 | CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), | |
3008 | CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), | |
3009 | CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), | |
3010 | CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), | |
3011 | CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), | |
3012 | CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), | |
3013 | CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), | |
54776050 RN |
3014 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
3015 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), | |
3016 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), | |
3017 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), | |
54776050 | 3018 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
1c03f42f BC |
3019 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
3020 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | |
3021 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | |
3022 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | |
032b5a7e | 3023 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), |
1c03f42f | 3024 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
032b5a7e TG |
3025 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), |
3026 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | |
1c03f42f BC |
3027 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
3028 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | |
0e433271 | 3029 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
1c03f42f BC |
3030 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
3031 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | |
0e433271 | 3032 | CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), |
0edc9e85 | 3033 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
1c03f42f BC |
3034 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
3035 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | |
3036 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | |
0e433271 | 3037 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
0edc9e85 BC |
3038 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
3039 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | |
0e433271 BC |
3040 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
3041 | CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), | |
3042 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), | |
972c5427 RN |
3043 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
3044 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | |
7c43d547 SS |
3045 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), |
3046 | CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), | |
3047 | CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), | |
3048 | CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), | |
3049 | CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), | |
3050 | CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), | |
3051 | CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), | |
3052 | CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), | |
3053 | CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), | |
3054 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), | |
3055 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), | |
3056 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), | |
f7bb0d9a BC |
3057 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
3058 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), | |
3059 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), | |
3060 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), | |
0e433271 BC |
3061 | CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), |
3062 | CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), | |
3063 | CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), | |
3064 | CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), | |
3065 | CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3066 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), |
3067 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | |
3068 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | |
3069 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | |
0e433271 BC |
3070 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), |
3071 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), | |
3072 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), | |
3073 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3074 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), |
3075 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | |
3076 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | |
3077 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | |
3078 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | |
972c5427 RN |
3079 | }; |
3080 | ||
e80a9729 | 3081 | int __init omap4xxx_clk_init(void) |
972c5427 | 3082 | { |
972c5427 | 3083 | struct omap_clk *c; |
972c5427 RN |
3084 | u32 cpu_clkflg; |
3085 | ||
3086 | if (cpu_is_omap44xx()) { | |
3087 | cpu_mask = RATE_IN_4430; | |
3088 | cpu_clkflg = CK_443X; | |
3089 | } | |
3090 | ||
3091 | clk_init(&omap2_clk_functions); | |
3092 | ||
3093 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3094 | c++) | |
3095 | clk_preinit(c->lk.clk); | |
3096 | ||
3097 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3098 | c++) | |
3099 | if (c->cpu & cpu_clkflg) { | |
3100 | clkdev_add(&c->lk); | |
3101 | clk_register(c->lk.clk); | |
972c5427 | 3102 | omap2_init_clk_clkdm(c->lk.clk); |
972c5427 RN |
3103 | } |
3104 | ||
3105 | recalculate_root_clocks(); | |
3106 | ||
3107 | /* | |
3108 | * Only enable those clocks we will need, let the drivers | |
3109 | * enable other clocks as necessary | |
3110 | */ | |
3111 | clk_enable_init_clocks(); | |
3112 | ||
3113 | return 0; | |
3114 | } |