[deliverable/linux.git] / arch / arm / mach-omap2 / clockdomains.h

/*
 * OMAP2/3 clockdomains
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Copyright (C) 2008 Nokia Corporation
 *
 * Written by Paul Walmsley
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H

#include <plat/clockdomain.h>
#include "cm.h"
#include "prm44xx.h"

/*
 * OMAP2/3-common clockdomains
 *
 * Even though the 2420 has a single PRCM module from the
 * interconnect's perspective, internally it does appear to have
 * separate PRM and CM clockdomains.  The usual test case is
 * sys_clkout/sys_clkout2.
 */

/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
	.name		= "wkup_clkdm",
	.pwrdm		= { .name = "wkup_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

static struct clockdomain prm_clkdm = {
	.name		= "prm_clkdm",
	.pwrdm		= { .name = "wkup_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

static struct clockdomain cm_clkdm = {
	.name		= "cm_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

/*
 * 2420-only clockdomains
 */

#if defined(CONFIG_ARCH_OMAP2420)

static struct clockdomain mpu_2420_clkdm = {
	.name		= "mpu_clkdm",
	.pwrdm		= { .name = "mpu_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain iva1_2420_clkdm = {
	.name		= "iva1_clkdm",
	.pwrdm		= { .name = "dsp_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain dsp_2420_clkdm = {
	.name		= "dsp_clkdm",
	.pwrdm		= { .name = "dsp_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain gfx_2420_clkdm = {
	.name		= "gfx_clkdm",
	.pwrdm		= { .name = "gfx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain core_l3_2420_clkdm = {
	.name		= "core_l3_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain core_l4_2420_clkdm = {
	.name		= "core_l4_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain dss_2420_clkdm = {
	.name		= "dss_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

#endif   /* CONFIG_ARCH_OMAP2420 */


/*
 * 2430-only clockdomains
 */

#if defined(CONFIG_ARCH_OMAP2430)

static struct clockdomain mpu_2430_clkdm = {
	.name		= "mpu_clkdm",
	.pwrdm		= { .name = "mpu_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain mdm_clkdm = {
	.name		= "mdm_clkdm",
	.pwrdm		= { .name = "mdm_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain dsp_2430_clkdm = {
	.name		= "dsp_clkdm",
	.pwrdm		= { .name = "dsp_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain gfx_2430_clkdm = {
	.name		= "gfx_clkdm",
	.pwrdm		= { .name = "gfx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain core_l3_2430_clkdm = {
	.name		= "core_l3_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain core_l4_2430_clkdm = {
	.name		= "core_l4_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static struct clockdomain dss_2430_clkdm = {
	.name		= "dss_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

#endif    /* CONFIG_ARCH_OMAP2430 */


/*
 * 34xx clockdomains
 */

#if defined(CONFIG_ARCH_OMAP34XX)

static struct clockdomain mpu_34xx_clkdm = {
	.name		= "mpu_clkdm",
	.pwrdm		= { .name = "mpu_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain neon_clkdm = {
	.name		= "neon_clkdm",
	.pwrdm		= { .name = "neon_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain iva2_clkdm = {
	.name		= "iva2_clkdm",
	.pwrdm		= { .name = "iva2_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain gfx_3430es1_clkdm = {
	.name		= "gfx_clkdm",
	.pwrdm		= { .name = "gfx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};

static struct clockdomain sgx_clkdm = {
	.name		= "sgx_clkdm",
	.pwrdm		= { .name = "sgx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};

/*
 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 * then that information was removed from the 34xx ES2+ TRM.  It is
 * unclear whether the core is still there, but the clockdomain logic
 * is there, and must be programmed to an appropriate state if the
 * CORE clockdomain is to become inactive.
 */
static struct clockdomain d2d_clkdm = {
	.name		= "d2d_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain core_l3_34xx_clkdm = {
	.name		= "core_l3_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain core_l4_34xx_clkdm = {
	.name		= "core_l4_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dss_34xx_clkdm = {
	.name		= "dss_clkdm",
	.pwrdm		= { .name = "dss_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain cam_clkdm = {
	.name		= "cam_clkdm",
	.pwrdm		= { .name = "cam_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain usbhost_clkdm = {
	.name		= "usbhost_clkdm",
	.pwrdm		= { .name = "usbhost_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};

static struct clockdomain per_clkdm = {
	.name		= "per_clkdm",
	.pwrdm		= { .name = "per_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

/*
 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 * switched of even if sdti is in use
 */
static struct clockdomain emu_clkdm = {
	.name		= "emu_clkdm",
	.pwrdm		= { .name = "emu_pwrdm" },
	.flags		= /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
	.clkstctrl_reg	= OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
						 OMAP2_CM_CLKSTCTRL),
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll1_clkdm = {
	.name		= "dpll1_clkdm",
	.pwrdm		= { .name = "dpll1_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll2_clkdm = {
	.name		= "dpll2_clkdm",
	.pwrdm		= { .name = "dpll2_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll3_clkdm = {
	.name		= "dpll3_clkdm",
	.pwrdm		= { .name = "dpll3_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll4_clkdm = {
	.name		= "dpll4_clkdm",
	.pwrdm		= { .name = "dpll4_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll5_clkdm = {
	.name		= "dpll5_clkdm",
	.pwrdm		= { .name = "dpll5_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};

#endif   /* CONFIG_ARCH_OMAP34XX */

/*
 * Clockdomain-powerdomain hwsup dependencies (34XX only)
 */

static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
	{
		.pwrdm	   = { .name = "mpu_pwrdm" },
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.pwrdm	   = { .name = "iva2_pwrdm" },
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.pwrdm	   = { .name = NULL },
	}
};

/*
 *
 */

static struct clockdomain *clockdomains_omap[] = {

	&wkup_clkdm,
	&cm_clkdm,
	&prm_clkdm,

#ifdef CONFIG_ARCH_OMAP2420
	&mpu_2420_clkdm,
	&iva1_2420_clkdm,
	&dsp_2420_clkdm,
	&gfx_2420_clkdm,
	&core_l3_2420_clkdm,
	&core_l4_2420_clkdm,
	&dss_2420_clkdm,
#endif

#ifdef CONFIG_ARCH_OMAP2430
	&mpu_2430_clkdm,
	&mdm_clkdm,
	&dsp_2430_clkdm,
	&gfx_2430_clkdm,
	&core_l3_2430_clkdm,
	&core_l4_2430_clkdm,
	&dss_2430_clkdm,
#endif

#ifdef CONFIG_ARCH_OMAP34XX
	&mpu_34xx_clkdm,
	&neon_clkdm,
	&iva2_clkdm,
	&gfx_3430es1_clkdm,
	&sgx_clkdm,
	&d2d_clkdm,
	&core_l3_34xx_clkdm,
	&core_l4_34xx_clkdm,
	&dss_34xx_clkdm,
	&cam_clkdm,
	&usbhost_clkdm,
	&per_clkdm,
	&emu_clkdm,
	&dpll1_clkdm,
	&dpll2_clkdm,
	&dpll3_clkdm,
	&dpll4_clkdm,
	&dpll5_clkdm,
#endif

	NULL,
};

#endif
Commit	Line	Data
801954d3 PW	1	/*
	2	* OMAP2/3 clockdomains
	3	*
	4	* Copyright (C) 2008 Texas Instruments, Inc.
	5	* Copyright (C) 2008 Nokia Corporation
	6	*
	7	* Written by Paul Walmsley
	8	*/
	9
	10	#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
	11	#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
	12
ce491cf8	13	#include <plat/clockdomain.h>
84c0c39a AP	14	#include "cm.h"
84c0c39a AP	15	#include "prm44xx.h"
801954d3 PW	16
	17	/*
	18	* OMAP2/3-common clockdomains
d37f1a13 PW	19	*
	20	* Even though the 2420 has a single PRCM module from the
	21	* interconnect's perspective, internally it does appear to have
	22	* separate PRM and CM clockdomains. The usual test case is
	23	* sys_clkout/sys_clkout2.
801954d3 PW	24	*/
	25
	26	/* This is an implicit clockdomain - it is never defined as such in TRM */
	27	static struct clockdomain wkup_clkdm = {
	28	.name = "wkup_clkdm",
5b74c676	29	.pwrdm = { .name = "wkup_pwrdm" },
801954d3 PW	30	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX \| CHIP_IS_OMAP3430),
	31	};
	32
d37f1a13 PW	33	static struct clockdomain prm_clkdm = {
	34	.name = "prm_clkdm",
	35	.pwrdm = { .name = "wkup_pwrdm" },
	36	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX \| CHIP_IS_OMAP3430),
	37	};
	38
	39	static struct clockdomain cm_clkdm = {
	40	.name = "cm_clkdm",
	41	.pwrdm = { .name = "core_pwrdm" },
	42	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX \| CHIP_IS_OMAP3430),
	43	};
	44
801954d3 PW	45	/*
	46	* 2420-only clockdomains
	47	*/
	48
	49	#if defined(CONFIG_ARCH_OMAP2420)
	50
	51	static struct clockdomain mpu_2420_clkdm = {
	52	.name = "mpu_clkdm",
5b74c676	53	.pwrdm = { .name = "mpu_pwrdm" },
801954d3	54	.flags = CLKDM_CAN_HWSUP,
84c0c39a	55	.clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
801954d3 PW	56	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	57	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	58	};
	59
	60	static struct clockdomain iva1_2420_clkdm = {
	61	.name = "iva1_clkdm",
5b74c676	62	.pwrdm = { .name = "dsp_pwrdm" },
801954d3	63	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	64	.clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
84c0c39a AP	65	OMAP2_CM_CLKSTCTRL),
801954d3 PW	66	.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
	67	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	68	};
	69
84c0c39a AP	70	static struct clockdomain dsp_2420_clkdm = {
	71	.name = "dsp_clkdm",
	72	.pwrdm = { .name = "dsp_pwrdm" },
	73	.flags = CLKDM_CAN_HWSUP_SWSUP,
	74	.clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
	75	OMAP2_CM_CLKSTCTRL),
	76	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
	77	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	78	};
	79
	80	static struct clockdomain gfx_2420_clkdm = {
	81	.name = "gfx_clkdm",
	82	.pwrdm = { .name = "gfx_pwrdm" },
	83	.flags = CLKDM_CAN_HWSUP_SWSUP,
	84	.clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
	85	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
	86	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	87	};
	88
	89	static struct clockdomain core_l3_2420_clkdm = {
	90	.name = "core_l3_clkdm",
	91	.pwrdm = { .name = "core_pwrdm" },
	92	.flags = CLKDM_CAN_HWSUP,
	93	.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	94	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
	95	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	96	};
	97
	98	static struct clockdomain core_l4_2420_clkdm = {
	99	.name = "core_l4_clkdm",
	100	.pwrdm = { .name = "core_pwrdm" },
	101	.flags = CLKDM_CAN_HWSUP,
	102	.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	103	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
	104	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	105	};
	106
	107	static struct clockdomain dss_2420_clkdm = {
	108	.name = "dss_clkdm",
	109	.pwrdm = { .name = "core_pwrdm" },
	110	.flags = CLKDM_CAN_HWSUP,
	111	.clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
	112	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
	113	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
	114	};
	115
	116	#endif /* CONFIG_ARCH_OMAP2420 */
801954d3 PW	117
	118
	119	/*
	120	* 2430-only clockdomains
	121	*/
	122
	123	#if defined(CONFIG_ARCH_OMAP2430)
	124
	125	static struct clockdomain mpu_2430_clkdm = {
	126	.name = "mpu_clkdm",
5b74c676	127	.pwrdm = { .name = "mpu_pwrdm" },
801954d3	128	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	129	.clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD,
84c0c39a AP	130	OMAP2_CM_CLKSTCTRL),
801954d3 PW	131	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	132	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	133	};
	134
	135	static struct clockdomain mdm_clkdm = {
	136	.name = "mdm_clkdm",
5b74c676	137	.pwrdm = { .name = "mdm_pwrdm" },
801954d3	138	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	139	.clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
84c0c39a AP	140	OMAP2_CM_CLKSTCTRL),
801954d3 PW	141	.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
	142	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	143	};
	144
84c0c39a	145	static struct clockdomain dsp_2430_clkdm = {
801954d3	146	.name = "dsp_clkdm",
5b74c676	147	.pwrdm = { .name = "dsp_pwrdm" },
801954d3	148	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	149	.clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
84c0c39a AP	150	OMAP2_CM_CLKSTCTRL),
801954d3	151	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
84c0c39a	152	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
801954d3 PW	153	};
801954d3 PW	154
84c0c39a	155	static struct clockdomain gfx_2430_clkdm = {
801954d3	156	.name = "gfx_clkdm",
5b74c676	157	.pwrdm = { .name = "gfx_pwrdm" },
801954d3	158	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a	159	.clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
801954d3	160	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
84c0c39a	161	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
801954d3 PW	162	};
801954d3 PW	163
84c0c39a	164	static struct clockdomain core_l3_2430_clkdm = {
801954d3	165	.name = "core_l3_clkdm",
5b74c676	166	.pwrdm = { .name = "core_pwrdm" },
801954d3	167	.flags = CLKDM_CAN_HWSUP,
84c0c39a	168	.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3	169	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
84c0c39a	170	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
801954d3 PW	171	};
801954d3 PW	172
84c0c39a	173	static struct clockdomain core_l4_2430_clkdm = {
801954d3	174	.name = "core_l4_clkdm",
5b74c676	175	.pwrdm = { .name = "core_pwrdm" },
801954d3	176	.flags = CLKDM_CAN_HWSUP,
84c0c39a	177	.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3	178	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
84c0c39a	179	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
801954d3 PW	180	};
801954d3 PW	181
84c0c39a	182	static struct clockdomain dss_2430_clkdm = {
801954d3	183	.name = "dss_clkdm",
5b74c676	184	.pwrdm = { .name = "core_pwrdm" },
801954d3	185	.flags = CLKDM_CAN_HWSUP,
84c0c39a	186	.clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3	187	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
84c0c39a	188	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
801954d3 PW	189	};
801954d3 PW	190
84c0c39a	191	#endif /* CONFIG_ARCH_OMAP2430 */
801954d3 PW	192
	193
	194	/*
	195	* 34xx clockdomains
	196	*/
	197
	198	#if defined(CONFIG_ARCH_OMAP34XX)
	199
	200	static struct clockdomain mpu_34xx_clkdm = {
	201	.name = "mpu_clkdm",
5b74c676	202	.pwrdm = { .name = "mpu_pwrdm" },
801954d3	203	.flags = CLKDM_CAN_HWSUP \| CLKDM_CAN_FORCE_WAKEUP,
84c0c39a	204	.clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
801954d3 PW	205	.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
	206	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	207	};
	208
	209	static struct clockdomain neon_clkdm = {
	210	.name = "neon_clkdm",
5b74c676	211	.pwrdm = { .name = "neon_pwrdm" },
801954d3	212	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	213	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
84c0c39a AP	214	OMAP2_CM_CLKSTCTRL),
801954d3 PW	215	.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
	216	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	217	};
	218
	219	static struct clockdomain iva2_clkdm = {
	220	.name = "iva2_clkdm",
5b74c676	221	.pwrdm = { .name = "iva2_pwrdm" },
801954d3	222	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	223	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
84c0c39a AP	224	OMAP2_CM_CLKSTCTRL),
801954d3 PW	225	.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
	226	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	227	};
	228
	229	static struct clockdomain gfx_3430es1_clkdm = {
	230	.name = "gfx_clkdm",
5b74c676	231	.pwrdm = { .name = "gfx_pwrdm" },
801954d3	232	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a	233	.clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
801954d3 PW	234	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
	235	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
	236	};
	237
	238	static struct clockdomain sgx_clkdm = {
	239	.name = "sgx_clkdm",
5b74c676	240	.pwrdm = { .name = "sgx_pwrdm" },
801954d3	241	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	242	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
84c0c39a AP	243	OMAP2_CM_CLKSTCTRL),
801954d3	244	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
d41ad520	245	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
801954d3 PW	246	};
801954d3 PW	247
333943ba PW	248	/*
	249	* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
	250	* then that information was removed from the 34xx ES2+ TRM. It is
	251	* unclear whether the core is still there, but the clockdomain logic
	252	* is there, and must be programmed to an appropriate state if the
	253	* CORE clockdomain is to become inactive.
	254	*/
801954d3 PW	255	static struct clockdomain d2d_clkdm = {
801954d3 PW	256	.name = "d2d_clkdm",
5b74c676	257	.pwrdm = { .name = "core_pwrdm" },
01cbd4d1	258	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a	259	.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3	260	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
333943ba	261	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
801954d3 PW	262	};
	263
	264	static struct clockdomain core_l3_34xx_clkdm = {
	265	.name = "core_l3_clkdm",
5b74c676	266	.pwrdm = { .name = "core_pwrdm" },
801954d3	267	.flags = CLKDM_CAN_HWSUP,
84c0c39a	268	.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3 PW	269	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
	270	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	271	};
	272
	273	static struct clockdomain core_l4_34xx_clkdm = {
	274	.name = "core_l4_clkdm",
5b74c676	275	.pwrdm = { .name = "core_pwrdm" },
801954d3	276	.flags = CLKDM_CAN_HWSUP,
84c0c39a	277	.clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
801954d3 PW	278	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
	279	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	280	};
	281
	282	static struct clockdomain dss_34xx_clkdm = {
	283	.name = "dss_clkdm",
5b74c676	284	.pwrdm = { .name = "dss_pwrdm" },
801954d3	285	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	286	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
84c0c39a AP	287	OMAP2_CM_CLKSTCTRL),
801954d3 PW	288	.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
	289	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	290	};
	291
	292	static struct clockdomain cam_clkdm = {
	293	.name = "cam_clkdm",
5b74c676	294	.pwrdm = { .name = "cam_pwrdm" },
801954d3	295	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	296	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
84c0c39a AP	297	OMAP2_CM_CLKSTCTRL),
801954d3 PW	298	.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
	299	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	300	};
	301
	302	static struct clockdomain usbhost_clkdm = {
	303	.name = "usbhost_clkdm",
5b74c676	304	.pwrdm = { .name = "usbhost_pwrdm" },
801954d3	305	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	306	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
84c0c39a AP	307	OMAP2_CM_CLKSTCTRL),
801954d3	308	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
d41ad520	309	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
801954d3 PW	310	};
	311
	312	static struct clockdomain per_clkdm = {
	313	.name = "per_clkdm",
5b74c676	314	.pwrdm = { .name = "per_pwrdm" },
801954d3	315	.flags = CLKDM_CAN_HWSUP_SWSUP,
84c0c39a AP	316	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
84c0c39a AP	317	OMAP2_CM_CLKSTCTRL),
801954d3 PW	318	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
	319	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	320	};
	321
f266950d JH	322	/*
	323	* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
	324	* switched of even if sdti is in use
	325	*/
801954d3 PW	326	static struct clockdomain emu_clkdm = {
801954d3 PW	327	.name = "emu_clkdm",
5b74c676	328	.pwrdm = { .name = "emu_pwrdm" },
f266950d	329	.flags = /* CLKDM_CAN_ENABLE_AUTO \| */CLKDM_CAN_SWSUP,
84c0c39a AP	330	.clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
84c0c39a AP	331	OMAP2_CM_CLKSTCTRL),
801954d3 PW	332	.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
	333	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	334	};
	335
46e0ccf8 PW	336	static struct clockdomain dpll1_clkdm = {
	337	.name = "dpll1_clkdm",
	338	.pwrdm = { .name = "dpll1_pwrdm" },
	339	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	340	};
	341
	342	static struct clockdomain dpll2_clkdm = {
	343	.name = "dpll2_clkdm",
	344	.pwrdm = { .name = "dpll2_pwrdm" },
	345	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	346	};
	347
	348	static struct clockdomain dpll3_clkdm = {
	349	.name = "dpll3_clkdm",
	350	.pwrdm = { .name = "dpll3_pwrdm" },
	351	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	352	};
	353
	354	static struct clockdomain dpll4_clkdm = {
	355	.name = "dpll4_clkdm",
	356	.pwrdm = { .name = "dpll4_pwrdm" },
	357	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	358	};
	359
	360	static struct clockdomain dpll5_clkdm = {
	361	.name = "dpll5_clkdm",
	362	.pwrdm = { .name = "dpll5_pwrdm" },
d41ad520	363	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
46e0ccf8 PW	364	};
46e0ccf8 PW	365
801954d3 PW	366	#endif /* CONFIG_ARCH_OMAP34XX */
	367
	368	/*
	369	* Clockdomain-powerdomain hwsup dependencies (34XX only)
	370	*/
	371
	372	static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
	373	{
5b74c676	374	.pwrdm = { .name = "mpu_pwrdm" },
801954d3 PW	375	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	376	},
	377	{
5b74c676	378	.pwrdm = { .name = "iva2_pwrdm" },
801954d3 PW	379	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
801954d3 PW	380	},
5b74c676 PW	381	{
	382	.pwrdm = { .name = NULL },
	383	}
801954d3 PW	384	};
	385
	386	/*
	387	*
	388	*/
	389
	390	static struct clockdomain *clockdomains_omap[] = {
	391
	392	&wkup_clkdm,
d37f1a13 PW	393	&cm_clkdm,
d37f1a13 PW	394	&prm_clkdm,
801954d3 PW	395
	396	#ifdef CONFIG_ARCH_OMAP2420
	397	&mpu_2420_clkdm,
	398	&iva1_2420_clkdm,
84c0c39a AP	399	&dsp_2420_clkdm,
	400	&gfx_2420_clkdm,
	401	&core_l3_2420_clkdm,
	402	&core_l4_2420_clkdm,
	403	&dss_2420_clkdm,
801954d3 PW	404	#endif
	405
	406	#ifdef CONFIG_ARCH_OMAP2430
	407	&mpu_2430_clkdm,
	408	&mdm_clkdm,
84c0c39a AP	409	&dsp_2430_clkdm,
	410	&gfx_2430_clkdm,
	411	&core_l3_2430_clkdm,
	412	&core_l4_2430_clkdm,
	413	&dss_2430_clkdm,
801954d3 PW	414	#endif
	415
	416	#ifdef CONFIG_ARCH_OMAP34XX
	417	&mpu_34xx_clkdm,
	418	&neon_clkdm,
	419	&iva2_clkdm,
	420	&gfx_3430es1_clkdm,
	421	&sgx_clkdm,
	422	&d2d_clkdm,
	423	&core_l3_34xx_clkdm,
	424	&core_l4_34xx_clkdm,
	425	&dss_34xx_clkdm,
	426	&cam_clkdm,
	427	&usbhost_clkdm,
	428	&per_clkdm,
	429	&emu_clkdm,
46e0ccf8 PW	430	&dpll1_clkdm,
	431	&dpll2_clkdm,
	432	&dpll3_clkdm,
	433	&dpll4_clkdm,
	434	&dpll5_clkdm,
801954d3 PW	435	#endif
	436
	437	NULL,
	438	};
	439
	440	#endif