Commit | Line | Data |
---|---|---|
801954d3 PW |
1 | /* |
2 | * OMAP2/3 clockdomains | |
3 | * | |
98fa3d8a PW |
4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2008-2010 Nokia Corporation | |
801954d3 | 6 | * |
dc0b3a70 | 7 | * Paul Walmsley, Jouni Högander |
55ed9694 PW |
8 | * |
9 | * This file contains clockdomains and clockdomain wakeup/sleep | |
10 | * dependencies for the OMAP2/3 chips. Some notes: | |
11 | * | |
12 | * A useful validation rule for struct clockdomain: Any clockdomain | |
13 | * referenced by a wkdep_srcs or sleepdep_srcs array must have a | |
14 | * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just | |
15 | * software-controllable dependencies. Non-software-controllable | |
16 | * dependencies do exist, but they are not encoded below (yet). | |
17 | * | |
18 | * 24xx does not support programmable sleep dependencies (SLEEPDEP) | |
19 | * | |
20 | * The overly-specific dep_bit names are due to a bit name collision | |
21 | * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift | |
22 | * value are the same for all powerdomains: 2 | |
23 | * | |
24 | * XXX should dep_bit be a mask, so we can test to see if it is 0 as a | |
25 | * sanity check? | |
26 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE | |
801954d3 PW |
27 | */ |
28 | ||
1a422724 AP |
29 | /* |
30 | * To-Do List | |
31 | * -> Port the Sleep/Wakeup dependencies for the domains | |
32 | * from the Power domain framework | |
33 | */ | |
34 | ||
dc0b3a70 PW |
35 | #include <linux/kernel.h> |
36 | #include <linux/io.h> | |
801954d3 | 37 | |
1540f214 | 38 | #include "clockdomain.h" |
59fb659b PW |
39 | #include "prm2xxx_3xxx.h" |
40 | #include "cm2xxx_3xxx.h" | |
74bea6b9 RN |
41 | #include "cm-regbits-24xx.h" |
42 | #include "cm-regbits-34xx.h" | |
43 | #include "cm-regbits-44xx.h" | |
44 | #include "prm-regbits-24xx.h" | |
45 | #include "prm-regbits-34xx.h" | |
801954d3 | 46 | |
55ed9694 PW |
47 | /* |
48 | * Clockdomain dependencies for wkdeps/sleepdeps | |
49 | * | |
50 | * XXX Hardware dependencies (e.g., dependencies that cannot be | |
51 | * changed in software) are not included here yet, but should be. | |
52 | */ | |
53 | ||
54 | /* OMAP2/3-common wakeup dependencies */ | |
55 | ||
56 | /* | |
57 | * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP | |
58 | * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE | |
59 | * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE | |
a2601700 PW |
60 | * These can share data since they will never be present simultaneously |
61 | * on the same device. | |
55ed9694 PW |
62 | */ |
63 | static struct clkdm_dep gfx_sgx_wkdeps[] = { | |
64 | { | |
65 | .clkdm_name = "core_l3_clkdm", | |
66 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
67 | }, | |
68 | { | |
69 | .clkdm_name = "core_l4_clkdm", | |
70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
71 | }, | |
72 | { | |
73 | .clkdm_name = "iva2_clkdm", | |
74 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
75 | }, | |
76 | { | |
77 | .clkdm_name = "mpu_clkdm", | |
78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | |
79 | CHIP_IS_OMAP3430) | |
80 | }, | |
81 | { | |
82 | .clkdm_name = "wkup_clkdm", | |
83 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | |
84 | CHIP_IS_OMAP3430) | |
85 | }, | |
86 | { NULL }, | |
87 | }; | |
88 | ||
89 | ||
90 | /* 24XX-specific possible dependencies */ | |
91 | ||
55ed9694 PW |
92 | /* Wakeup dependency source arrays */ |
93 | ||
a2601700 PW |
94 | /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ |
95 | static struct clkdm_dep dsp_24xx_wkdeps[] = { | |
96 | { | |
97 | .clkdm_name = "core_l3_clkdm", | |
98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
99 | }, | |
100 | { | |
101 | .clkdm_name = "core_l4_clkdm", | |
102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
103 | }, | |
104 | { | |
105 | .clkdm_name = "mpu_clkdm", | |
106 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
107 | }, | |
108 | { | |
109 | .clkdm_name = "wkup_clkdm", | |
110 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
111 | }, | |
112 | { NULL }, | |
113 | }; | |
114 | ||
55ed9694 | 115 | /* |
3d309cde PW |
116 | * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP |
117 | * 2430 adds MDM | |
55ed9694 | 118 | */ |
3d309cde | 119 | static struct clkdm_dep mpu_24xx_wkdeps[] = { |
55ed9694 PW |
120 | { |
121 | .clkdm_name = "core_l3_clkdm", | |
122 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
123 | }, | |
124 | { | |
125 | .clkdm_name = "core_l4_clkdm", | |
126 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
127 | }, | |
128 | { | |
3d309cde | 129 | .clkdm_name = "dsp_clkdm", |
55ed9694 PW |
130 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
131 | }, | |
132 | { | |
133 | .clkdm_name = "wkup_clkdm", | |
134 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
135 | }, | |
3d309cde PW |
136 | { |
137 | .clkdm_name = "mdm_clkdm", | |
138 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
139 | }, | |
55ed9694 PW |
140 | { NULL }, |
141 | }; | |
142 | ||
143 | /* | |
3d309cde | 144 | * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP |
55ed9694 PW |
145 | * 2430 adds MDM |
146 | */ | |
3d309cde | 147 | static struct clkdm_dep core_24xx_wkdeps[] = { |
55ed9694 | 148 | { |
3d309cde | 149 | .clkdm_name = "dsp_clkdm", |
55ed9694 PW |
150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
151 | }, | |
152 | { | |
3d309cde | 153 | .clkdm_name = "gfx_clkdm", |
55ed9694 PW |
154 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
155 | }, | |
156 | { | |
3d309cde | 157 | .clkdm_name = "mpu_clkdm", |
55ed9694 PW |
158 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
159 | }, | |
160 | { | |
161 | .clkdm_name = "wkup_clkdm", | |
162 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
163 | }, | |
164 | { | |
165 | .clkdm_name = "mdm_clkdm", | |
166 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
167 | }, | |
168 | { NULL }, | |
169 | }; | |
170 | ||
3d309cde PW |
171 | |
172 | /* 2430-specific possible wakeup dependencies */ | |
173 | ||
174 | #ifdef CONFIG_ARCH_OMAP2430 | |
175 | ||
176 | /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ | |
177 | static struct clkdm_dep mdm_2430_wkdeps[] = { | |
55ed9694 | 178 | { |
3d309cde | 179 | .clkdm_name = "core_l3_clkdm", |
55ed9694 PW |
180 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
181 | }, | |
182 | { | |
3d309cde | 183 | .clkdm_name = "core_l4_clkdm", |
55ed9694 PW |
184 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) |
185 | }, | |
186 | { | |
187 | .clkdm_name = "mpu_clkdm", | |
188 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
189 | }, | |
190 | { | |
191 | .clkdm_name = "wkup_clkdm", | |
192 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) | |
193 | }, | |
55ed9694 PW |
194 | { NULL }, |
195 | }; | |
196 | ||
3d309cde PW |
197 | #endif /* CONFIG_ARCH_OMAP2430 */ |
198 | ||
55ed9694 | 199 | |
98fa3d8a | 200 | /* OMAP3-specific possible dependencies */ |
55ed9694 | 201 | |
98fa3d8a | 202 | #ifdef CONFIG_ARCH_OMAP3 |
55ed9694 | 203 | |
a2601700 PW |
204 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ |
205 | static struct clkdm_dep per_wkdeps[] = { | |
55ed9694 PW |
206 | { |
207 | .clkdm_name = "core_l3_clkdm", | |
208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
209 | }, | |
210 | { | |
211 | .clkdm_name = "core_l4_clkdm", | |
212 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
213 | }, | |
214 | { | |
215 | .clkdm_name = "iva2_clkdm", | |
216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
217 | }, | |
218 | { | |
219 | .clkdm_name = "mpu_clkdm", | |
220 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
221 | }, | |
222 | { | |
223 | .clkdm_name = "wkup_clkdm", | |
224 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
225 | }, | |
226 | { NULL }, | |
227 | }; | |
228 | ||
a2601700 PW |
229 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ |
230 | static struct clkdm_dep usbhost_wkdeps[] = { | |
231 | { | |
232 | .clkdm_name = "core_l3_clkdm", | |
233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
234 | }, | |
235 | { | |
236 | .clkdm_name = "core_l4_clkdm", | |
237 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
238 | }, | |
239 | { | |
240 | .clkdm_name = "iva2_clkdm", | |
241 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
242 | }, | |
243 | { | |
244 | .clkdm_name = "mpu_clkdm", | |
245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
246 | }, | |
247 | { | |
248 | .clkdm_name = "wkup_clkdm", | |
249 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
250 | }, | |
251 | { NULL }, | |
252 | }; | |
253 | ||
254 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ | |
98fa3d8a | 255 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { |
55ed9694 PW |
256 | { |
257 | .clkdm_name = "core_l3_clkdm", | |
258 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
259 | }, | |
260 | { | |
261 | .clkdm_name = "core_l4_clkdm", | |
262 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
263 | }, | |
264 | { | |
265 | .clkdm_name = "iva2_clkdm", | |
266 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
267 | }, | |
268 | { | |
269 | .clkdm_name = "dss_clkdm", | |
270 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
271 | }, | |
272 | { | |
273 | .clkdm_name = "per_clkdm", | |
274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
275 | }, | |
276 | { NULL }, | |
277 | }; | |
278 | ||
a2601700 | 279 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ |
55ed9694 PW |
280 | static struct clkdm_dep iva2_wkdeps[] = { |
281 | { | |
282 | .clkdm_name = "core_l3_clkdm", | |
283 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
284 | }, | |
285 | { | |
286 | .clkdm_name = "core_l4_clkdm", | |
287 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
288 | }, | |
289 | { | |
290 | .clkdm_name = "mpu_clkdm", | |
291 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
292 | }, | |
293 | { | |
294 | .clkdm_name = "wkup_clkdm", | |
295 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
296 | }, | |
297 | { | |
298 | .clkdm_name = "dss_clkdm", | |
299 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
300 | }, | |
301 | { | |
302 | .clkdm_name = "per_clkdm", | |
303 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
304 | }, | |
305 | { NULL }, | |
306 | }; | |
307 | ||
308 | ||
a2601700 PW |
309 | /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ |
310 | static struct clkdm_dep cam_wkdeps[] = { | |
311 | { | |
312 | .clkdm_name = "iva2_clkdm", | |
313 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
314 | }, | |
315 | { | |
316 | .clkdm_name = "mpu_clkdm", | |
317 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
318 | }, | |
319 | { | |
320 | .clkdm_name = "wkup_clkdm", | |
321 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
322 | }, | |
323 | { NULL }, | |
324 | }; | |
325 | ||
326 | /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ | |
327 | static struct clkdm_dep dss_wkdeps[] = { | |
55ed9694 PW |
328 | { |
329 | .clkdm_name = "iva2_clkdm", | |
330 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
331 | }, | |
332 | { | |
333 | .clkdm_name = "mpu_clkdm", | |
334 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
335 | }, | |
336 | { | |
337 | .clkdm_name = "wkup_clkdm", | |
338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
339 | }, | |
340 | { NULL }, | |
341 | }; | |
342 | ||
343 | /* 3430: PM_WKDEP_NEON: MPU */ | |
344 | static struct clkdm_dep neon_wkdeps[] = { | |
345 | { | |
346 | .clkdm_name = "mpu_clkdm", | |
347 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
348 | }, | |
349 | { NULL }, | |
350 | }; | |
351 | ||
352 | ||
98fa3d8a | 353 | /* Sleep dependency source arrays for OMAP3-specific clkdms */ |
55ed9694 | 354 | |
a2601700 PW |
355 | /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ |
356 | static struct clkdm_dep dss_sleepdeps[] = { | |
55ed9694 PW |
357 | { |
358 | .clkdm_name = "mpu_clkdm", | |
359 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
360 | }, | |
361 | { | |
362 | .clkdm_name = "iva2_clkdm", | |
363 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
364 | }, | |
365 | { NULL }, | |
366 | }; | |
367 | ||
a2601700 PW |
368 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ |
369 | static struct clkdm_dep per_sleepdeps[] = { | |
370 | { | |
371 | .clkdm_name = "mpu_clkdm", | |
372 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
373 | }, | |
374 | { | |
375 | .clkdm_name = "iva2_clkdm", | |
376 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
377 | }, | |
378 | { NULL }, | |
379 | }; | |
380 | ||
381 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ | |
382 | static struct clkdm_dep usbhost_sleepdeps[] = { | |
383 | { | |
384 | .clkdm_name = "mpu_clkdm", | |
385 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
386 | }, | |
387 | { | |
388 | .clkdm_name = "iva2_clkdm", | |
389 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
390 | }, | |
391 | { NULL }, | |
392 | }; | |
393 | ||
394 | /* 3430: CM_SLEEPDEP_CAM: MPU */ | |
395 | static struct clkdm_dep cam_sleepdeps[] = { | |
396 | { | |
397 | .clkdm_name = "mpu_clkdm", | |
398 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
399 | }, | |
400 | { NULL }, | |
401 | }; | |
402 | ||
55ed9694 | 403 | /* |
55ed9694 PW |
404 | * 3430ES1: CM_SLEEPDEP_GFX: MPU |
405 | * 3430ES2: CM_SLEEPDEP_SGX: MPU | |
a2601700 PW |
406 | * These can share data since they will never be present simultaneously |
407 | * on the same device. | |
55ed9694 | 408 | */ |
a2601700 | 409 | static struct clkdm_dep gfx_sgx_sleepdeps[] = { |
55ed9694 PW |
410 | { |
411 | .clkdm_name = "mpu_clkdm", | |
412 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
413 | }, | |
414 | { NULL }, | |
415 | }; | |
416 | ||
98fa3d8a | 417 | #endif /* CONFIG_ARCH_OMAP3 */ |
55ed9694 PW |
418 | |
419 | ||
801954d3 PW |
420 | /* |
421 | * OMAP2/3-common clockdomains | |
d37f1a13 PW |
422 | * |
423 | * Even though the 2420 has a single PRCM module from the | |
424 | * interconnect's perspective, internally it does appear to have | |
425 | * separate PRM and CM clockdomains. The usual test case is | |
426 | * sys_clkout/sys_clkout2. | |
801954d3 PW |
427 | */ |
428 | ||
429 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | |
430 | static struct clockdomain wkup_clkdm = { | |
431 | .name = "wkup_clkdm", | |
5b74c676 | 432 | .pwrdm = { .name = "wkup_pwrdm" }, |
55ed9694 | 433 | .dep_bit = OMAP_EN_WKUP_SHIFT, |
801954d3 PW |
434 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
435 | }; | |
436 | ||
d37f1a13 PW |
437 | static struct clockdomain prm_clkdm = { |
438 | .name = "prm_clkdm", | |
439 | .pwrdm = { .name = "wkup_pwrdm" }, | |
440 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | |
441 | }; | |
442 | ||
443 | static struct clockdomain cm_clkdm = { | |
444 | .name = "cm_clkdm", | |
445 | .pwrdm = { .name = "core_pwrdm" }, | |
446 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | |
447 | }; | |
448 | ||
801954d3 PW |
449 | /* |
450 | * 2420-only clockdomains | |
451 | */ | |
452 | ||
453 | #if defined(CONFIG_ARCH_OMAP2420) | |
454 | ||
455 | static struct clockdomain mpu_2420_clkdm = { | |
456 | .name = "mpu_clkdm", | |
5b74c676 | 457 | .pwrdm = { .name = "mpu_pwrdm" }, |
801954d3 | 458 | .flags = CLKDM_CAN_HWSUP, |
55ed9694 | 459 | .wkdep_srcs = mpu_24xx_wkdeps, |
801954d3 PW |
460 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
461 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
462 | }; | |
463 | ||
464 | static struct clockdomain iva1_2420_clkdm = { | |
465 | .name = "iva1_clkdm", | |
5b74c676 | 466 | .pwrdm = { .name = "dsp_pwrdm" }, |
801954d3 | 467 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 468 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, |
a2601700 | 469 | .wkdep_srcs = dsp_24xx_wkdeps, |
801954d3 PW |
470 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
471 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
472 | }; | |
473 | ||
84c0c39a AP |
474 | static struct clockdomain dsp_2420_clkdm = { |
475 | .name = "dsp_clkdm", | |
476 | .pwrdm = { .name = "dsp_pwrdm" }, | |
477 | .flags = CLKDM_CAN_HWSUP_SWSUP, | |
84c0c39a AP |
478 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
479 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
480 | }; | |
481 | ||
482 | static struct clockdomain gfx_2420_clkdm = { | |
483 | .name = "gfx_clkdm", | |
484 | .pwrdm = { .name = "gfx_pwrdm" }, | |
485 | .flags = CLKDM_CAN_HWSUP_SWSUP, | |
55ed9694 | 486 | .wkdep_srcs = gfx_sgx_wkdeps, |
84c0c39a AP |
487 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
488 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
489 | }; | |
490 | ||
491 | static struct clockdomain core_l3_2420_clkdm = { | |
492 | .name = "core_l3_clkdm", | |
493 | .pwrdm = { .name = "core_pwrdm" }, | |
494 | .flags = CLKDM_CAN_HWSUP, | |
55ed9694 | 495 | .wkdep_srcs = core_24xx_wkdeps, |
84c0c39a AP |
496 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
497 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
498 | }; | |
499 | ||
500 | static struct clockdomain core_l4_2420_clkdm = { | |
501 | .name = "core_l4_clkdm", | |
502 | .pwrdm = { .name = "core_pwrdm" }, | |
503 | .flags = CLKDM_CAN_HWSUP, | |
55ed9694 | 504 | .wkdep_srcs = core_24xx_wkdeps, |
84c0c39a AP |
505 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
506 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
507 | }; | |
508 | ||
509 | static struct clockdomain dss_2420_clkdm = { | |
510 | .name = "dss_clkdm", | |
511 | .pwrdm = { .name = "core_pwrdm" }, | |
512 | .flags = CLKDM_CAN_HWSUP, | |
84c0c39a AP |
513 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
514 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
515 | }; | |
516 | ||
517 | #endif /* CONFIG_ARCH_OMAP2420 */ | |
801954d3 PW |
518 | |
519 | ||
520 | /* | |
521 | * 2430-only clockdomains | |
522 | */ | |
523 | ||
524 | #if defined(CONFIG_ARCH_OMAP2430) | |
525 | ||
526 | static struct clockdomain mpu_2430_clkdm = { | |
527 | .name = "mpu_clkdm", | |
5b74c676 | 528 | .pwrdm = { .name = "mpu_pwrdm" }, |
801954d3 | 529 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 530 | .wkdep_srcs = mpu_24xx_wkdeps, |
801954d3 PW |
531 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
532 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
533 | }; | |
534 | ||
55ed9694 | 535 | /* Another case of bit name collisions between several registers: EN_MDM */ |
801954d3 PW |
536 | static struct clockdomain mdm_clkdm = { |
537 | .name = "mdm_clkdm", | |
5b74c676 | 538 | .pwrdm = { .name = "mdm_pwrdm" }, |
801954d3 | 539 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 540 | .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, |
3d309cde | 541 | .wkdep_srcs = mdm_2430_wkdeps, |
801954d3 PW |
542 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
543 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
544 | }; | |
545 | ||
84c0c39a | 546 | static struct clockdomain dsp_2430_clkdm = { |
801954d3 | 547 | .name = "dsp_clkdm", |
5b74c676 | 548 | .pwrdm = { .name = "dsp_pwrdm" }, |
801954d3 | 549 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 550 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, |
a2601700 | 551 | .wkdep_srcs = dsp_24xx_wkdeps, |
801954d3 | 552 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
84c0c39a | 553 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
801954d3 PW |
554 | }; |
555 | ||
84c0c39a | 556 | static struct clockdomain gfx_2430_clkdm = { |
801954d3 | 557 | .name = "gfx_clkdm", |
5b74c676 | 558 | .pwrdm = { .name = "gfx_pwrdm" }, |
801954d3 | 559 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 560 | .wkdep_srcs = gfx_sgx_wkdeps, |
801954d3 | 561 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
84c0c39a | 562 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
801954d3 PW |
563 | }; |
564 | ||
55ed9694 PW |
565 | /* |
566 | * XXX add usecounting for clkdm dependencies, otherwise the presence | |
567 | * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm | |
568 | * could cause trouble | |
569 | */ | |
84c0c39a | 570 | static struct clockdomain core_l3_2430_clkdm = { |
801954d3 | 571 | .name = "core_l3_clkdm", |
5b74c676 | 572 | .pwrdm = { .name = "core_pwrdm" }, |
801954d3 | 573 | .flags = CLKDM_CAN_HWSUP, |
55ed9694 PW |
574 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, |
575 | .wkdep_srcs = core_24xx_wkdeps, | |
801954d3 | 576 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
84c0c39a | 577 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
801954d3 PW |
578 | }; |
579 | ||
55ed9694 PW |
580 | /* |
581 | * XXX add usecounting for clkdm dependencies, otherwise the presence | |
582 | * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm | |
583 | * could cause trouble | |
584 | */ | |
84c0c39a | 585 | static struct clockdomain core_l4_2430_clkdm = { |
801954d3 | 586 | .name = "core_l4_clkdm", |
5b74c676 | 587 | .pwrdm = { .name = "core_pwrdm" }, |
801954d3 | 588 | .flags = CLKDM_CAN_HWSUP, |
55ed9694 PW |
589 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, |
590 | .wkdep_srcs = core_24xx_wkdeps, | |
801954d3 | 591 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
84c0c39a | 592 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
801954d3 PW |
593 | }; |
594 | ||
84c0c39a | 595 | static struct clockdomain dss_2430_clkdm = { |
801954d3 | 596 | .name = "dss_clkdm", |
5b74c676 | 597 | .pwrdm = { .name = "core_pwrdm" }, |
801954d3 PW |
598 | .flags = CLKDM_CAN_HWSUP, |
599 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | |
84c0c39a | 600 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
801954d3 PW |
601 | }; |
602 | ||
84c0c39a | 603 | #endif /* CONFIG_ARCH_OMAP2430 */ |
801954d3 PW |
604 | |
605 | ||
606 | /* | |
98fa3d8a | 607 | * OMAP3 clockdomains |
801954d3 PW |
608 | */ |
609 | ||
98fa3d8a | 610 | #if defined(CONFIG_ARCH_OMAP3) |
801954d3 | 611 | |
98fa3d8a | 612 | static struct clockdomain mpu_3xxx_clkdm = { |
801954d3 | 613 | .name = "mpu_clkdm", |
5b74c676 | 614 | .pwrdm = { .name = "mpu_pwrdm" }, |
801954d3 | 615 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
55ed9694 | 616 | .dep_bit = OMAP3430_EN_MPU_SHIFT, |
98fa3d8a | 617 | .wkdep_srcs = mpu_3xxx_wkdeps, |
801954d3 PW |
618 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
619 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
620 | }; | |
621 | ||
622 | static struct clockdomain neon_clkdm = { | |
623 | .name = "neon_clkdm", | |
5b74c676 | 624 | .pwrdm = { .name = "neon_pwrdm" }, |
801954d3 | 625 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 626 | .wkdep_srcs = neon_wkdeps, |
801954d3 PW |
627 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
628 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
629 | }; | |
630 | ||
631 | static struct clockdomain iva2_clkdm = { | |
632 | .name = "iva2_clkdm", | |
5b74c676 | 633 | .pwrdm = { .name = "iva2_pwrdm" }, |
801954d3 | 634 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 PW |
635 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, |
636 | .wkdep_srcs = iva2_wkdeps, | |
801954d3 PW |
637 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
638 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
639 | }; | |
640 | ||
641 | static struct clockdomain gfx_3430es1_clkdm = { | |
642 | .name = "gfx_clkdm", | |
5b74c676 | 643 | .pwrdm = { .name = "gfx_pwrdm" }, |
801954d3 | 644 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 645 | .wkdep_srcs = gfx_sgx_wkdeps, |
a2601700 | 646 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
801954d3 PW |
647 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
648 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | |
649 | }; | |
650 | ||
651 | static struct clockdomain sgx_clkdm = { | |
652 | .name = "sgx_clkdm", | |
5b74c676 | 653 | .pwrdm = { .name = "sgx_pwrdm" }, |
801954d3 | 654 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 655 | .wkdep_srcs = gfx_sgx_wkdeps, |
a2601700 | 656 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
801954d3 | 657 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
d41ad520 | 658 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
801954d3 PW |
659 | }; |
660 | ||
333943ba PW |
661 | /* |
662 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but | |
663 | * then that information was removed from the 34xx ES2+ TRM. It is | |
664 | * unclear whether the core is still there, but the clockdomain logic | |
665 | * is there, and must be programmed to an appropriate state if the | |
666 | * CORE clockdomain is to become inactive. | |
667 | */ | |
801954d3 PW |
668 | static struct clockdomain d2d_clkdm = { |
669 | .name = "d2d_clkdm", | |
5b74c676 | 670 | .pwrdm = { .name = "core_pwrdm" }, |
01cbd4d1 | 671 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
801954d3 | 672 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
333943ba | 673 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
801954d3 PW |
674 | }; |
675 | ||
55ed9694 PW |
676 | /* |
677 | * XXX add usecounting for clkdm dependencies, otherwise the presence | |
98fa3d8a | 678 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm |
55ed9694 PW |
679 | * could cause trouble |
680 | */ | |
98fa3d8a | 681 | static struct clockdomain core_l3_3xxx_clkdm = { |
801954d3 | 682 | .name = "core_l3_clkdm", |
5b74c676 | 683 | .pwrdm = { .name = "core_pwrdm" }, |
801954d3 | 684 | .flags = CLKDM_CAN_HWSUP, |
55ed9694 | 685 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
801954d3 PW |
686 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
687 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
688 | }; | |
689 | ||
55ed9694 PW |
690 | /* |
691 | * XXX add usecounting for clkdm dependencies, otherwise the presence | |
98fa3d8a | 692 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm |
55ed9694 PW |
693 | * could cause trouble |
694 | */ | |
98fa3d8a | 695 | static struct clockdomain core_l4_3xxx_clkdm = { |
801954d3 | 696 | .name = "core_l4_clkdm", |
5b74c676 | 697 | .pwrdm = { .name = "core_pwrdm" }, |
801954d3 | 698 | .flags = CLKDM_CAN_HWSUP, |
55ed9694 | 699 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
801954d3 PW |
700 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
701 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
702 | }; | |
703 | ||
55ed9694 | 704 | /* Another case of bit name collisions between several registers: EN_DSS */ |
98fa3d8a | 705 | static struct clockdomain dss_3xxx_clkdm = { |
801954d3 | 706 | .name = "dss_clkdm", |
5b74c676 | 707 | .pwrdm = { .name = "dss_pwrdm" }, |
801954d3 | 708 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 709 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, |
a2601700 PW |
710 | .wkdep_srcs = dss_wkdeps, |
711 | .sleepdep_srcs = dss_sleepdeps, | |
801954d3 PW |
712 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
713 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
714 | }; | |
715 | ||
716 | static struct clockdomain cam_clkdm = { | |
717 | .name = "cam_clkdm", | |
5b74c676 | 718 | .pwrdm = { .name = "cam_pwrdm" }, |
801954d3 | 719 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
a2601700 PW |
720 | .wkdep_srcs = cam_wkdeps, |
721 | .sleepdep_srcs = cam_sleepdeps, | |
801954d3 PW |
722 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
723 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
724 | }; | |
725 | ||
726 | static struct clockdomain usbhost_clkdm = { | |
727 | .name = "usbhost_clkdm", | |
5b74c676 | 728 | .pwrdm = { .name = "usbhost_pwrdm" }, |
801954d3 | 729 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
a2601700 PW |
730 | .wkdep_srcs = usbhost_wkdeps, |
731 | .sleepdep_srcs = usbhost_sleepdeps, | |
801954d3 | 732 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
d41ad520 | 733 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
801954d3 PW |
734 | }; |
735 | ||
736 | static struct clockdomain per_clkdm = { | |
737 | .name = "per_clkdm", | |
5b74c676 | 738 | .pwrdm = { .name = "per_pwrdm" }, |
801954d3 | 739 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
55ed9694 | 740 | .dep_bit = OMAP3430_EN_PER_SHIFT, |
a2601700 PW |
741 | .wkdep_srcs = per_wkdeps, |
742 | .sleepdep_srcs = per_sleepdeps, | |
801954d3 PW |
743 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
744 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
745 | }; | |
746 | ||
f266950d JH |
747 | /* |
748 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | |
749 | * switched of even if sdti is in use | |
750 | */ | |
801954d3 PW |
751 | static struct clockdomain emu_clkdm = { |
752 | .name = "emu_clkdm", | |
5b74c676 | 753 | .pwrdm = { .name = "emu_pwrdm" }, |
f266950d | 754 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
801954d3 PW |
755 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
756 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
757 | }; | |
758 | ||
46e0ccf8 PW |
759 | static struct clockdomain dpll1_clkdm = { |
760 | .name = "dpll1_clkdm", | |
761 | .pwrdm = { .name = "dpll1_pwrdm" }, | |
762 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
763 | }; | |
764 | ||
765 | static struct clockdomain dpll2_clkdm = { | |
766 | .name = "dpll2_clkdm", | |
767 | .pwrdm = { .name = "dpll2_pwrdm" }, | |
768 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
769 | }; | |
770 | ||
771 | static struct clockdomain dpll3_clkdm = { | |
772 | .name = "dpll3_clkdm", | |
773 | .pwrdm = { .name = "dpll3_pwrdm" }, | |
774 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
775 | }; | |
776 | ||
777 | static struct clockdomain dpll4_clkdm = { | |
778 | .name = "dpll4_clkdm", | |
779 | .pwrdm = { .name = "dpll4_pwrdm" }, | |
780 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
781 | }; | |
782 | ||
783 | static struct clockdomain dpll5_clkdm = { | |
784 | .name = "dpll5_clkdm", | |
785 | .pwrdm = { .name = "dpll5_pwrdm" }, | |
d41ad520 | 786 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
46e0ccf8 PW |
787 | }; |
788 | ||
98fa3d8a | 789 | #endif /* CONFIG_ARCH_OMAP3 */ |
801954d3 PW |
790 | |
791 | /* | |
98fa3d8a | 792 | * Clockdomain hwsup dependencies (OMAP3 only) |
801954d3 PW |
793 | */ |
794 | ||
55ed9694 | 795 | static struct clkdm_autodep clkdm_autodeps[] = { |
801954d3 | 796 | { |
55ed9694 | 797 | .clkdm = { .name = "mpu_clkdm" }, |
801954d3 PW |
798 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
799 | }, | |
800 | { | |
55ed9694 | 801 | .clkdm = { .name = "iva2_clkdm" }, |
801954d3 PW |
802 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
803 | }, | |
5b74c676 | 804 | { |
55ed9694 | 805 | .clkdm = { .name = NULL }, |
5b74c676 | 806 | } |
801954d3 PW |
807 | }; |
808 | ||
dc0b3a70 | 809 | static struct clockdomain *clockdomains_omap2[] __initdata = { |
801954d3 | 810 | &wkup_clkdm, |
d37f1a13 PW |
811 | &cm_clkdm, |
812 | &prm_clkdm, | |
801954d3 PW |
813 | |
814 | #ifdef CONFIG_ARCH_OMAP2420 | |
815 | &mpu_2420_clkdm, | |
816 | &iva1_2420_clkdm, | |
84c0c39a AP |
817 | &dsp_2420_clkdm, |
818 | &gfx_2420_clkdm, | |
819 | &core_l3_2420_clkdm, | |
820 | &core_l4_2420_clkdm, | |
821 | &dss_2420_clkdm, | |
801954d3 PW |
822 | #endif |
823 | ||
824 | #ifdef CONFIG_ARCH_OMAP2430 | |
825 | &mpu_2430_clkdm, | |
826 | &mdm_clkdm, | |
84c0c39a AP |
827 | &dsp_2430_clkdm, |
828 | &gfx_2430_clkdm, | |
829 | &core_l3_2430_clkdm, | |
830 | &core_l4_2430_clkdm, | |
831 | &dss_2430_clkdm, | |
801954d3 PW |
832 | #endif |
833 | ||
98fa3d8a PW |
834 | #ifdef CONFIG_ARCH_OMAP3 |
835 | &mpu_3xxx_clkdm, | |
801954d3 PW |
836 | &neon_clkdm, |
837 | &iva2_clkdm, | |
838 | &gfx_3430es1_clkdm, | |
839 | &sgx_clkdm, | |
840 | &d2d_clkdm, | |
98fa3d8a PW |
841 | &core_l3_3xxx_clkdm, |
842 | &core_l4_3xxx_clkdm, | |
843 | &dss_3xxx_clkdm, | |
801954d3 PW |
844 | &cam_clkdm, |
845 | &usbhost_clkdm, | |
846 | &per_clkdm, | |
847 | &emu_clkdm, | |
46e0ccf8 PW |
848 | &dpll1_clkdm, |
849 | &dpll2_clkdm, | |
850 | &dpll3_clkdm, | |
851 | &dpll4_clkdm, | |
852 | &dpll5_clkdm, | |
801954d3 | 853 | #endif |
801954d3 PW |
854 | NULL, |
855 | }; | |
856 | ||
dc0b3a70 PW |
857 | void __init omap2_clockdomains_init(void) |
858 | { | |
859 | clkdm_init(clockdomains_omap2, clkdm_autodeps); | |
860 | } |