Commit | Line | Data |
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30b8863d AP |
1 | /* |
2 | * OMAP4 Clock domains framework | |
3 | * | |
3c95b707 BC |
4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2011 Nokia Corporation | |
30b8863d AP |
6 | * |
7 | * Abhijit Pagare (abhijitpagare@ti.com) | |
8 | * Benoit Cousson (b-cousson@ti.com) | |
3c95b707 | 9 | * Paul Walmsley (paul@pwsan.com) |
30b8863d AP |
10 | * |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
dc0b3a70 PW |
22 | #include <linux/kernel.h> |
23 | #include <linux/io.h> | |
30b8863d | 24 | |
1540f214 | 25 | #include "clockdomain.h" |
59fb659b PW |
26 | #include "cm1_44xx.h" |
27 | #include "cm2_44xx.h" | |
30b8863d | 28 | |
dc0b3a70 | 29 | #include "cm-regbits-44xx.h" |
d198b514 | 30 | #include "prm44xx.h" |
bd2122ca | 31 | #include "prcm44xx.h" |
d198b514 PW |
32 | #include "prcm_mpu44xx.h" |
33 | ||
514c5948 RN |
34 | /* Static Dependencies for OMAP4 Clock Domains */ |
35 | ||
3c95b707 | 36 | static struct clkdm_dep d2d_wkup_sleep_deps[] = { |
a5ffef6a PW |
37 | { .clkdm_name = "abe_clkdm" }, |
38 | { .clkdm_name = "ivahd_clkdm" }, | |
39 | { .clkdm_name = "l3_1_clkdm" }, | |
40 | { .clkdm_name = "l3_2_clkdm" }, | |
41 | { .clkdm_name = "l3_emif_clkdm" }, | |
42 | { .clkdm_name = "l3_init_clkdm" }, | |
43 | { .clkdm_name = "l4_cfg_clkdm" }, | |
44 | { .clkdm_name = "l4_per_clkdm" }, | |
3c95b707 BC |
45 | { NULL }, |
46 | }; | |
47 | ||
48 | static struct clkdm_dep ducati_wkup_sleep_deps[] = { | |
a5ffef6a PW |
49 | { .clkdm_name = "abe_clkdm" }, |
50 | { .clkdm_name = "ivahd_clkdm" }, | |
51 | { .clkdm_name = "l3_1_clkdm" }, | |
52 | { .clkdm_name = "l3_2_clkdm" }, | |
53 | { .clkdm_name = "l3_dss_clkdm" }, | |
54 | { .clkdm_name = "l3_emif_clkdm" }, | |
55 | { .clkdm_name = "l3_gfx_clkdm" }, | |
56 | { .clkdm_name = "l3_init_clkdm" }, | |
57 | { .clkdm_name = "l4_cfg_clkdm" }, | |
58 | { .clkdm_name = "l4_per_clkdm" }, | |
59 | { .clkdm_name = "l4_secure_clkdm" }, | |
60 | { .clkdm_name = "l4_wkup_clkdm" }, | |
61 | { .clkdm_name = "tesla_clkdm" }, | |
3c95b707 BC |
62 | { NULL }, |
63 | }; | |
64 | ||
65 | static struct clkdm_dep iss_wkup_sleep_deps[] = { | |
a5ffef6a PW |
66 | { .clkdm_name = "ivahd_clkdm" }, |
67 | { .clkdm_name = "l3_1_clkdm" }, | |
68 | { .clkdm_name = "l3_emif_clkdm" }, | |
3c95b707 BC |
69 | { NULL }, |
70 | }; | |
71 | ||
72 | static struct clkdm_dep ivahd_wkup_sleep_deps[] = { | |
a5ffef6a PW |
73 | { .clkdm_name = "l3_1_clkdm" }, |
74 | { .clkdm_name = "l3_emif_clkdm" }, | |
514c5948 RN |
75 | { NULL }, |
76 | }; | |
77 | ||
78 | static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { | |
a5ffef6a PW |
79 | { .clkdm_name = "abe_clkdm" }, |
80 | { .clkdm_name = "ducati_clkdm" }, | |
81 | { .clkdm_name = "ivahd_clkdm" }, | |
82 | { .clkdm_name = "l3_1_clkdm" }, | |
83 | { .clkdm_name = "l3_dss_clkdm" }, | |
84 | { .clkdm_name = "l3_emif_clkdm" }, | |
85 | { .clkdm_name = "l3_init_clkdm" }, | |
86 | { .clkdm_name = "l4_cfg_clkdm" }, | |
87 | { .clkdm_name = "l4_per_clkdm" }, | |
88 | { .clkdm_name = "l4_secure_clkdm" }, | |
89 | { .clkdm_name = "l4_wkup_clkdm" }, | |
514c5948 RN |
90 | { NULL }, |
91 | }; | |
92 | ||
93 | static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { | |
a5ffef6a PW |
94 | { .clkdm_name = "ivahd_clkdm" }, |
95 | { .clkdm_name = "l3_2_clkdm" }, | |
96 | { .clkdm_name = "l3_emif_clkdm" }, | |
514c5948 RN |
97 | { NULL }, |
98 | }; | |
99 | ||
100 | static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { | |
a5ffef6a PW |
101 | { .clkdm_name = "ivahd_clkdm" }, |
102 | { .clkdm_name = "l3_1_clkdm" }, | |
103 | { .clkdm_name = "l3_emif_clkdm" }, | |
514c5948 RN |
104 | { NULL }, |
105 | }; | |
106 | ||
107 | static struct clkdm_dep l3_init_wkup_sleep_deps[] = { | |
a5ffef6a PW |
108 | { .clkdm_name = "abe_clkdm" }, |
109 | { .clkdm_name = "ivahd_clkdm" }, | |
110 | { .clkdm_name = "l3_emif_clkdm" }, | |
111 | { .clkdm_name = "l4_cfg_clkdm" }, | |
112 | { .clkdm_name = "l4_per_clkdm" }, | |
113 | { .clkdm_name = "l4_secure_clkdm" }, | |
114 | { .clkdm_name = "l4_wkup_clkdm" }, | |
514c5948 RN |
115 | { NULL }, |
116 | }; | |
117 | ||
118 | static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { | |
a5ffef6a PW |
119 | { .clkdm_name = "l3_1_clkdm" }, |
120 | { .clkdm_name = "l3_emif_clkdm" }, | |
121 | { .clkdm_name = "l4_per_clkdm" }, | |
514c5948 RN |
122 | { NULL }, |
123 | }; | |
124 | ||
3c95b707 | 125 | static struct clkdm_dep mpu_wkup_sleep_deps[] = { |
a5ffef6a PW |
126 | { .clkdm_name = "abe_clkdm" }, |
127 | { .clkdm_name = "ducati_clkdm" }, | |
128 | { .clkdm_name = "ivahd_clkdm" }, | |
129 | { .clkdm_name = "l3_1_clkdm" }, | |
130 | { .clkdm_name = "l3_2_clkdm" }, | |
131 | { .clkdm_name = "l3_dss_clkdm" }, | |
132 | { .clkdm_name = "l3_emif_clkdm" }, | |
133 | { .clkdm_name = "l3_gfx_clkdm" }, | |
134 | { .clkdm_name = "l3_init_clkdm" }, | |
135 | { .clkdm_name = "l4_cfg_clkdm" }, | |
136 | { .clkdm_name = "l4_per_clkdm" }, | |
137 | { .clkdm_name = "l4_secure_clkdm" }, | |
138 | { .clkdm_name = "l4_wkup_clkdm" }, | |
139 | { .clkdm_name = "tesla_clkdm" }, | |
514c5948 RN |
140 | { NULL }, |
141 | }; | |
142 | ||
143 | static struct clkdm_dep tesla_wkup_sleep_deps[] = { | |
a5ffef6a PW |
144 | { .clkdm_name = "abe_clkdm" }, |
145 | { .clkdm_name = "ivahd_clkdm" }, | |
146 | { .clkdm_name = "l3_1_clkdm" }, | |
147 | { .clkdm_name = "l3_2_clkdm" }, | |
148 | { .clkdm_name = "l3_emif_clkdm" }, | |
149 | { .clkdm_name = "l3_init_clkdm" }, | |
150 | { .clkdm_name = "l4_cfg_clkdm" }, | |
151 | { .clkdm_name = "l4_per_clkdm" }, | |
152 | { .clkdm_name = "l4_wkup_clkdm" }, | |
514c5948 RN |
153 | { NULL }, |
154 | }; | |
30b8863d AP |
155 | |
156 | static struct clockdomain l4_cefuse_44xx_clkdm = { | |
157 | .name = "l4_cefuse_clkdm", | |
158 | .pwrdm = { .name = "cefuse_pwrdm" }, | |
bd2122ca PW |
159 | .prcm_partition = OMAP4430_CM2_PARTITION, |
160 | .cm_inst = OMAP4430_CM2_CEFUSE_INST, | |
161 | .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, | |
30b8863d | 162 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
163 | }; |
164 | ||
165 | static struct clockdomain l4_cfg_44xx_clkdm = { | |
166 | .name = "l4_cfg_clkdm", | |
167 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
168 | .prcm_partition = OMAP4430_CM2_PARTITION, |
169 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
170 | .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, | |
514c5948 | 171 | .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT, |
30b8863d | 172 | .flags = CLKDM_CAN_HWSUP, |
30b8863d AP |
173 | }; |
174 | ||
175 | static struct clockdomain tesla_44xx_clkdm = { | |
176 | .name = "tesla_clkdm", | |
177 | .pwrdm = { .name = "tesla_pwrdm" }, | |
bd2122ca PW |
178 | .prcm_partition = OMAP4430_CM1_PARTITION, |
179 | .cm_inst = OMAP4430_CM1_TESLA_INST, | |
180 | .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, | |
514c5948 RN |
181 | .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT, |
182 | .wkdep_srcs = tesla_wkup_sleep_deps, | |
183 | .sleepdep_srcs = tesla_wkup_sleep_deps, | |
30b8863d | 184 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
185 | }; |
186 | ||
187 | static struct clockdomain l3_gfx_44xx_clkdm = { | |
188 | .name = "l3_gfx_clkdm", | |
189 | .pwrdm = { .name = "gfx_pwrdm" }, | |
bd2122ca PW |
190 | .prcm_partition = OMAP4430_CM2_PARTITION, |
191 | .cm_inst = OMAP4430_CM2_GFX_INST, | |
192 | .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, | |
514c5948 RN |
193 | .dep_bit = OMAP4430_GFX_STATDEP_SHIFT, |
194 | .wkdep_srcs = l3_gfx_wkup_sleep_deps, | |
195 | .sleepdep_srcs = l3_gfx_wkup_sleep_deps, | |
30b8863d | 196 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
197 | }; |
198 | ||
199 | static struct clockdomain ivahd_44xx_clkdm = { | |
200 | .name = "ivahd_clkdm", | |
201 | .pwrdm = { .name = "ivahd_pwrdm" }, | |
bd2122ca PW |
202 | .prcm_partition = OMAP4430_CM2_PARTITION, |
203 | .cm_inst = OMAP4430_CM2_IVAHD_INST, | |
204 | .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, | |
514c5948 RN |
205 | .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT, |
206 | .wkdep_srcs = ivahd_wkup_sleep_deps, | |
207 | .sleepdep_srcs = ivahd_wkup_sleep_deps, | |
30b8863d | 208 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
209 | }; |
210 | ||
211 | static struct clockdomain l4_secure_44xx_clkdm = { | |
212 | .name = "l4_secure_clkdm", | |
213 | .pwrdm = { .name = "l4per_pwrdm" }, | |
bd2122ca PW |
214 | .prcm_partition = OMAP4430_CM2_PARTITION, |
215 | .cm_inst = OMAP4430_CM2_L4PER_INST, | |
216 | .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, | |
514c5948 RN |
217 | .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT, |
218 | .wkdep_srcs = l4_secure_wkup_sleep_deps, | |
219 | .sleepdep_srcs = l4_secure_wkup_sleep_deps, | |
30b8863d | 220 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
221 | }; |
222 | ||
223 | static struct clockdomain l4_per_44xx_clkdm = { | |
224 | .name = "l4_per_clkdm", | |
225 | .pwrdm = { .name = "l4per_pwrdm" }, | |
bd2122ca PW |
226 | .prcm_partition = OMAP4430_CM2_PARTITION, |
227 | .cm_inst = OMAP4430_CM2_L4PER_INST, | |
228 | .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, | |
514c5948 | 229 | .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT, |
30b8863d | 230 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
231 | }; |
232 | ||
233 | static struct clockdomain abe_44xx_clkdm = { | |
234 | .name = "abe_clkdm", | |
235 | .pwrdm = { .name = "abe_pwrdm" }, | |
bd2122ca PW |
236 | .prcm_partition = OMAP4430_CM1_PARTITION, |
237 | .cm_inst = OMAP4430_CM1_ABE_INST, | |
238 | .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, | |
514c5948 | 239 | .dep_bit = OMAP4430_ABE_STATDEP_SHIFT, |
30b8863d | 240 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
241 | }; |
242 | ||
6b04e0d9 AP |
243 | static struct clockdomain l3_instr_44xx_clkdm = { |
244 | .name = "l3_instr_clkdm", | |
245 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
246 | .prcm_partition = OMAP4430_CM2_PARTITION, |
247 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
248 | .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, | |
6b04e0d9 AP |
249 | }; |
250 | ||
30b8863d AP |
251 | static struct clockdomain l3_init_44xx_clkdm = { |
252 | .name = "l3_init_clkdm", | |
253 | .pwrdm = { .name = "l3init_pwrdm" }, | |
bd2122ca PW |
254 | .prcm_partition = OMAP4430_CM2_PARTITION, |
255 | .cm_inst = OMAP4430_CM2_L3INIT_INST, | |
256 | .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, | |
514c5948 RN |
257 | .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT, |
258 | .wkdep_srcs = l3_init_wkup_sleep_deps, | |
259 | .sleepdep_srcs = l3_init_wkup_sleep_deps, | |
30b8863d | 260 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
261 | }; |
262 | ||
3c95b707 BC |
263 | static struct clockdomain d2d_44xx_clkdm = { |
264 | .name = "d2d_clkdm", | |
265 | .pwrdm = { .name = "core_pwrdm" }, | |
266 | .prcm_partition = OMAP4430_CM2_PARTITION, | |
267 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
268 | .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, | |
269 | .wkdep_srcs = d2d_wkup_sleep_deps, | |
270 | .sleepdep_srcs = d2d_wkup_sleep_deps, | |
30b8863d | 271 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
272 | }; |
273 | ||
274 | static struct clockdomain mpu0_44xx_clkdm = { | |
275 | .name = "mpu0_clkdm", | |
276 | .pwrdm = { .name = "cpu0_pwrdm" }, | |
bd2122ca PW |
277 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
278 | .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, | |
1a9f5e89 | 279 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS, |
30b8863d | 280 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
281 | }; |
282 | ||
283 | static struct clockdomain mpu1_44xx_clkdm = { | |
284 | .name = "mpu1_clkdm", | |
285 | .pwrdm = { .name = "cpu1_pwrdm" }, | |
bd2122ca PW |
286 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
287 | .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, | |
1a9f5e89 | 288 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS, |
30b8863d | 289 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
290 | }; |
291 | ||
292 | static struct clockdomain l3_emif_44xx_clkdm = { | |
293 | .name = "l3_emif_clkdm", | |
294 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
295 | .prcm_partition = OMAP4430_CM2_PARTITION, |
296 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
297 | .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, | |
514c5948 | 298 | .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT, |
30b8863d | 299 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
300 | }; |
301 | ||
302 | static struct clockdomain l4_ao_44xx_clkdm = { | |
303 | .name = "l4_ao_clkdm", | |
304 | .pwrdm = { .name = "always_on_core_pwrdm" }, | |
bd2122ca PW |
305 | .prcm_partition = OMAP4430_CM2_PARTITION, |
306 | .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, | |
307 | .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, | |
30b8863d | 308 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
309 | }; |
310 | ||
311 | static struct clockdomain ducati_44xx_clkdm = { | |
312 | .name = "ducati_clkdm", | |
313 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
314 | .prcm_partition = OMAP4430_CM2_PARTITION, |
315 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
316 | .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, | |
514c5948 RN |
317 | .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT, |
318 | .wkdep_srcs = ducati_wkup_sleep_deps, | |
319 | .sleepdep_srcs = ducati_wkup_sleep_deps, | |
30b8863d | 320 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
321 | }; |
322 | ||
3c95b707 | 323 | static struct clockdomain mpu_44xx_clkdm = { |
a5322c6f | 324 | .name = "mpuss_clkdm", |
3c95b707 BC |
325 | .pwrdm = { .name = "mpu_pwrdm" }, |
326 | .prcm_partition = OMAP4430_CM1_PARTITION, | |
327 | .cm_inst = OMAP4430_CM1_MPU_INST, | |
328 | .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, | |
329 | .wkdep_srcs = mpu_wkup_sleep_deps, | |
330 | .sleepdep_srcs = mpu_wkup_sleep_deps, | |
331 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | |
3c95b707 BC |
332 | }; |
333 | ||
30b8863d AP |
334 | static struct clockdomain l3_2_44xx_clkdm = { |
335 | .name = "l3_2_clkdm", | |
336 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
337 | .prcm_partition = OMAP4430_CM2_PARTITION, |
338 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
339 | .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, | |
514c5948 | 340 | .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT, |
30b8863d | 341 | .flags = CLKDM_CAN_HWSUP, |
30b8863d AP |
342 | }; |
343 | ||
344 | static struct clockdomain l3_1_44xx_clkdm = { | |
345 | .name = "l3_1_clkdm", | |
346 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
347 | .prcm_partition = OMAP4430_CM2_PARTITION, |
348 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
349 | .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, | |
514c5948 | 350 | .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT, |
30b8863d | 351 | .flags = CLKDM_CAN_HWSUP, |
30b8863d AP |
352 | }; |
353 | ||
30b8863d AP |
354 | static struct clockdomain iss_44xx_clkdm = { |
355 | .name = "iss_clkdm", | |
356 | .pwrdm = { .name = "cam_pwrdm" }, | |
bd2122ca PW |
357 | .prcm_partition = OMAP4430_CM2_PARTITION, |
358 | .cm_inst = OMAP4430_CM2_CAM_INST, | |
359 | .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, | |
514c5948 RN |
360 | .wkdep_srcs = iss_wkup_sleep_deps, |
361 | .sleepdep_srcs = iss_wkup_sleep_deps, | |
74549de1 | 362 | .flags = CLKDM_CAN_SWSUP, |
30b8863d AP |
363 | }; |
364 | ||
365 | static struct clockdomain l3_dss_44xx_clkdm = { | |
366 | .name = "l3_dss_clkdm", | |
367 | .pwrdm = { .name = "dss_pwrdm" }, | |
bd2122ca PW |
368 | .prcm_partition = OMAP4430_CM2_PARTITION, |
369 | .cm_inst = OMAP4430_CM2_DSS_INST, | |
370 | .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, | |
514c5948 RN |
371 | .dep_bit = OMAP4430_DSS_STATDEP_SHIFT, |
372 | .wkdep_srcs = l3_dss_wkup_sleep_deps, | |
373 | .sleepdep_srcs = l3_dss_wkup_sleep_deps, | |
30b8863d | 374 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
30b8863d AP |
375 | }; |
376 | ||
377 | static struct clockdomain l4_wkup_44xx_clkdm = { | |
378 | .name = "l4_wkup_clkdm", | |
379 | .pwrdm = { .name = "wkup_pwrdm" }, | |
bd2122ca PW |
380 | .prcm_partition = OMAP4430_PRM_PARTITION, |
381 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, | |
382 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, | |
514c5948 | 383 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, |
006c7f18 | 384 | .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU, |
30b8863d AP |
385 | }; |
386 | ||
387 | static struct clockdomain emu_sys_44xx_clkdm = { | |
388 | .name = "emu_sys_clkdm", | |
389 | .pwrdm = { .name = "emu_pwrdm" }, | |
bd2122ca PW |
390 | .prcm_partition = OMAP4430_PRM_PARTITION, |
391 | .cm_inst = OMAP4430_PRM_EMU_CM_INST, | |
392 | .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, | |
b71c7217 PW |
393 | .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP | |
394 | CLKDM_MISSING_IDLE_REPORTING), | |
30b8863d AP |
395 | }; |
396 | ||
397 | static struct clockdomain l3_dma_44xx_clkdm = { | |
398 | .name = "l3_dma_clkdm", | |
399 | .pwrdm = { .name = "core_pwrdm" }, | |
bd2122ca PW |
400 | .prcm_partition = OMAP4430_CM2_PARTITION, |
401 | .cm_inst = OMAP4430_CM2_CORE_INST, | |
402 | .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, | |
514c5948 RN |
403 | .wkdep_srcs = l3_dma_wkup_sleep_deps, |
404 | .sleepdep_srcs = l3_dma_wkup_sleep_deps, | |
30b8863d | 405 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
30b8863d AP |
406 | }; |
407 | ||
3c95b707 | 408 | /* As clockdomains are added or removed above, this list must also be changed */ |
dc0b3a70 PW |
409 | static struct clockdomain *clockdomains_omap44xx[] __initdata = { |
410 | &l4_cefuse_44xx_clkdm, | |
411 | &l4_cfg_44xx_clkdm, | |
412 | &tesla_44xx_clkdm, | |
413 | &l3_gfx_44xx_clkdm, | |
414 | &ivahd_44xx_clkdm, | |
415 | &l4_secure_44xx_clkdm, | |
416 | &l4_per_44xx_clkdm, | |
417 | &abe_44xx_clkdm, | |
418 | &l3_instr_44xx_clkdm, | |
419 | &l3_init_44xx_clkdm, | |
3c95b707 | 420 | &d2d_44xx_clkdm, |
dc0b3a70 PW |
421 | &mpu0_44xx_clkdm, |
422 | &mpu1_44xx_clkdm, | |
423 | &l3_emif_44xx_clkdm, | |
424 | &l4_ao_44xx_clkdm, | |
425 | &ducati_44xx_clkdm, | |
3c95b707 | 426 | &mpu_44xx_clkdm, |
dc0b3a70 PW |
427 | &l3_2_44xx_clkdm, |
428 | &l3_1_44xx_clkdm, | |
dc0b3a70 PW |
429 | &iss_44xx_clkdm, |
430 | &l3_dss_44xx_clkdm, | |
431 | &l4_wkup_44xx_clkdm, | |
432 | &emu_sys_44xx_clkdm, | |
433 | &l3_dma_44xx_clkdm, | |
3c95b707 | 434 | NULL |
dc0b3a70 | 435 | }; |
30b8863d | 436 | |
08cb9703 | 437 | |
dc0b3a70 PW |
438 | void __init omap44xx_clockdomains_init(void) |
439 | { | |
08cb9703 PW |
440 | clkdm_register_platform_funcs(&omap4_clkdm_operations); |
441 | clkdm_register_clkdms(clockdomains_omap44xx); | |
442 | clkdm_complete_init(); | |
dc0b3a70 | 443 | } |