Commit | Line | Data |
---|---|---|
69d88a00 PW |
1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H |
2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H | |
3 | ||
4 | /* | |
5 | * OMAP24XX Clock Management register bits | |
6 | * | |
7 | * Copyright (C) 2007 Texas Instruments, Inc. | |
8 | * Copyright (C) 2007 Nokia Corporation | |
9 | * | |
10 | * Written by Paul Walmsley | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
69d88a00 | 17 | #define OMAP24XX_EN_CAM_SHIFT 31 |
69d88a00 | 18 | #define OMAP24XX_EN_WDT4_SHIFT 29 |
69d88a00 | 19 | #define OMAP2420_EN_WDT3_SHIFT 28 |
69d88a00 | 20 | #define OMAP24XX_EN_MSPRO_SHIFT 27 |
69d88a00 | 21 | #define OMAP24XX_EN_FAC_SHIFT 25 |
69d88a00 | 22 | #define OMAP2420_EN_EAC_SHIFT 24 |
69d88a00 | 23 | #define OMAP24XX_EN_HDQ_SHIFT 23 |
69d88a00 | 24 | #define OMAP2420_EN_I2C2_SHIFT 20 |
69d88a00 | 25 | #define OMAP2420_EN_I2C1_SHIFT 19 |
69d88a00 | 26 | #define OMAP2430_EN_MCBSP5_SHIFT 5 |
69d88a00 | 27 | #define OMAP2430_EN_MCBSP4_SHIFT 4 |
69d88a00 | 28 | #define OMAP2430_EN_MCBSP3_SHIFT 3 |
69d88a00 | 29 | #define OMAP24XX_EN_SSI_SHIFT 1 |
69d88a00 | 30 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 |
69d88a00 | 31 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 |
6ab9f69e | 32 | #define OMAP24XX_CLKSEL_MPU_WIDTH 5 |
801954d3 | 33 | #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) |
69d88a00 | 34 | #define OMAP24XX_EN_TV_SHIFT 2 |
69d88a00 | 35 | #define OMAP24XX_EN_DSS2_SHIFT 1 |
69d88a00 | 36 | #define OMAP24XX_EN_DSS1_SHIFT 0 |
f38ca10a | 37 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) |
69d88a00 | 38 | #define OMAP2430_EN_I2CHS2_SHIFT 20 |
69d88a00 | 39 | #define OMAP2430_EN_I2CHS1_SHIFT 19 |
69d88a00 | 40 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 |
69d88a00 | 41 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 |
69d88a00 | 42 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 |
69d88a00 | 43 | #define OMAP2430_EN_SDRC_SHIFT 2 |
69d88a00 | 44 | #define OMAP24XX_EN_PKA_SHIFT 4 |
69d88a00 | 45 | #define OMAP24XX_EN_AES_SHIFT 3 |
69d88a00 | 46 | #define OMAP24XX_EN_RNG_SHIFT 2 |
69d88a00 | 47 | #define OMAP24XX_EN_SHA_SHIFT 1 |
69d88a00 | 48 | #define OMAP24XX_EN_DES_SHIFT 0 |
da0747d4 | 49 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
da0747d4 | 50 | #define OMAP24XX_ST_HDQ_SHIFT 23 |
da0747d4 | 51 | #define OMAP2420_ST_I2C2_SHIFT 20 |
2004290f | 52 | #define OMAP2430_ST_I2CHS1_SHIFT 19 |
da0747d4 | 53 | #define OMAP2420_ST_I2C1_SHIFT 19 |
2004290f | 54 | #define OMAP2430_ST_I2CHS2_SHIFT 20 |
da0747d4 | 55 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
da0747d4 | 56 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 |
da0747d4 | 57 | #define OMAP24XX_ST_DSS_SHIFT 0 |
da0747d4 | 58 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
f38ca10a | 59 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
f38ca10a | 60 | #define OMAP2430_ST_MCBSP3_SHIFT 3 |
da0747d4 | 61 | #define OMAP24XX_ST_AES_SHIFT 3 |
da0747d4 | 62 | #define OMAP24XX_ST_RNG_SHIFT 2 |
da0747d4 | 63 | #define OMAP24XX_ST_SHA_SHIFT 1 |
a56d9ea8 | 64 | #define OMAP24XX_AUTO_SDRC_SHIFT 2 |
6ae690da | 65 | #define OMAP24XX_AUTO_GPMC_SHIFT 1 |
6ae690da | 66 | #define OMAP24XX_AUTO_SDMA_SHIFT 0 |
69d88a00 | 67 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) |
69d88a00 | 68 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) |
69d88a00 | 69 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) |
69d88a00 | 70 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) |
69d88a00 PW |
71 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) |
72 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 | |
6ab9f69e | 73 | #define OMAP24XX_CLKSEL_L4_WIDTH 2 |
69d88a00 | 74 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 |
6ab9f69e | 75 | #define OMAP24XX_CLKSEL_L3_WIDTH 5 |
69d88a00 | 76 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) |
69d88a00 | 77 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) |
69d88a00 | 78 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) |
69d88a00 | 79 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) |
69d88a00 | 80 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) |
69d88a00 | 81 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) |
69d88a00 | 82 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) |
69d88a00 | 83 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) |
69d88a00 | 84 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) |
69d88a00 | 85 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) |
69d88a00 | 86 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) |
801954d3 | 87 | #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) |
801954d3 | 88 | #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) |
801954d3 | 89 | #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) |
69d88a00 | 90 | #define OMAP24XX_EN_3D_SHIFT 2 |
69d88a00 | 91 | #define OMAP24XX_EN_2D_SHIFT 1 |
801954d3 | 92 | #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) |
69d88a00 | 93 | #define OMAP2430_EN_ICR_SHIFT 6 |
69d88a00 | 94 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 |
69d88a00 | 95 | #define OMAP24XX_EN_WDT1_SHIFT 4 |
69d88a00 | 96 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 |
da0747d4 | 97 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 |
da0747d4 | 98 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 |
69d88a00 | 99 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) |
69d88a00 | 100 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 |
69d88a00 | 101 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 |
69d88a00 | 102 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) |
b6ffa050 | 103 | #define OMAP24XX_ST_54M_APLL_SHIFT 9 |
b6ffa050 | 104 | #define OMAP24XX_ST_96M_APLL_SHIFT 8 |
69d88a00 | 105 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) |
69d88a00 PW |
106 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) |
107 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | |
108 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | |
69d88a00 PW |
109 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 |
110 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | |
69d88a00 | 111 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) |
69d88a00 PW |
112 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) |
113 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | |
6ab9f69e | 114 | #define OMAP24XX_54M_SOURCE_WIDTH 1 |
69d88a00 | 115 | #define OMAP2430_96M_SOURCE_SHIFT 4 |
6ab9f69e | 116 | #define OMAP2430_96M_SOURCE_WIDTH 1 |
f38ca10a | 117 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) |
69d88a00 | 118 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) |
69d88a00 | 119 | #define OMAP2420_EN_IVA_COP_SHIFT 10 |
69d88a00 | 120 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 |
69d88a00 | 121 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 |
69d88a00 | 122 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 |
69d88a00 | 123 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) |
69d88a00 | 124 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) |
69d88a00 | 125 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) |
801954d3 | 126 | #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) |
801954d3 | 127 | #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) |
69d88a00 | 128 | #define OMAP2430_EN_OSC_SHIFT 1 |
69d88a00 | 129 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 |
69d88a00 | 130 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) |
801954d3 | 131 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) |
55ae3507 PW |
132 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
133 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 | |
69d88a00 | 134 | #endif |