projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c595713d TL |
1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H |
| 2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H | |
| 3 | ||
| 4 | /* | |
| 5 | * OMAP3430 Clock Management register bits | |
| 6 | * | |
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | |
| 9 | * | |
| 10 | * Written by Paul Walmsley | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | */ | |
| 16 | ||
| c595713d TL |
17 | /* Bits shared between registers */ |
| 18 | ||
| 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | |
| 20 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | |
| 21 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | |
| 2bc4ef71 | 22 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) |
| c595713d | 23 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
| 2bc4ef71 | 24 | #define OMAP3430_EN_HDQ_MASK (1 << 22) |
| c595713d | 25 | #define OMAP3430_EN_HDQ_SHIFT 22 |
| 2bc4ef71 | 26 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) |
| c595713d | 27 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
| 2bc4ef71 | 28 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) |
| c595713d | 29 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
| 2bc4ef71 | 30 | #define OMAP3430_EN_SSI_MASK (1 << 0) |
| c595713d TL |
31 | #define OMAP3430_EN_SSI_SHIFT 0 |
| 32 | ||
| 33 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | |
| 34 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | |
| 35 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | |
| 36 | ||
| 37 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | |
| 2bc4ef71 | 38 | #define OMAP3430_EN_WDT2_MASK (1 << 5) |
| c595713d TL |
39 | #define OMAP3430_EN_WDT2_SHIFT 5 |
| 40 | ||
| 41 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | |
| 2bc4ef71 | 42 | #define OMAP3430_EN_CAM_MASK (1 << 0) |
| c595713d TL |
43 | #define OMAP3430_EN_CAM_SHIFT 0 |
| 44 | ||
| 45 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | |
| 2bc4ef71 | 46 | #define OMAP3430_EN_WDT3_MASK (1 << 12) |
| c595713d TL |
47 | #define OMAP3430_EN_WDT3_SHIFT 12 |
| 48 | ||
| 49 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | |
| 2bc4ef71 | 50 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) |
| c595713d TL |
51 | |
| 52 | ||
| 53 | /* Bits specific to each register */ | |
| 54 | ||
| 55 | /* CM_FCLKEN_IVA2 */ | |
| dfa6d6f8 | 56 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
| 31c203d4 | 57 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
| c595713d TL |
58 | |
| 59 | /* CM_CLKEN_PLL_IVA2 */ | |
| 60 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | |
| 61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 62 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | |
| 63 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | |
| 64 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | |
| 65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 66 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | |
| 67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | |
| 68 | ||
| 69 | /* CM_IDLEST_IVA2 */ | |
| 2bc4ef71 | 70 | #define OMAP3430_ST_IVA2_MASK (1 << 0) |
| c595713d TL |
71 | |
| 72 | /* CM_IDLEST_PLL_IVA2 */ | |
| 542313cc PW |
73 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 |
| 74 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | |
| c595713d TL |
75 | |
| 76 | /* CM_AUTOIDLE_PLL_IVA2 */ | |
| 77 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | |
| 78 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | |
| 79 | ||
| 80 | /* CM_CLKSEL1_PLL_IVA2 */ | |
| 81 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | |
| 82 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) | |
| 83 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | |
| 84 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | |
| 85 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | |
| 86 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | |
| 87 | ||
| 88 | /* CM_CLKSEL2_PLL_IVA2 */ | |
| 89 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | |
| 90 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
| 91 | ||
| 92 | /* CM_CLKSTCTRL_IVA2 */ | |
| 93 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | |
| 94 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | |
| 95 | ||
| 96 | /* CM_CLKSTST_IVA2 */ | |
| 801954d3 PW |
97 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 |
| 98 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | |
| c595713d TL |
99 | |
| 100 | /* CM_REVISION specific bits */ | |
| 101 | ||
| 102 | /* CM_SYSCONFIG specific bits */ | |
| 103 | ||
| 104 | /* CM_CLKEN_PLL_MPU */ | |
| 105 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | |
| 106 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 107 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | |
| 108 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | |
| 109 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | |
| 110 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 111 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | |
| 112 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | |
| 113 | ||
| 114 | /* CM_IDLEST_MPU */ | |
| 2bc4ef71 | 115 | #define OMAP3430_ST_MPU_MASK (1 << 0) |
| c595713d TL |
116 | |
| 117 | /* CM_IDLEST_PLL_MPU */ | |
| 542313cc | 118 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 3760d31f | 119 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| c595713d TL |
120 | |
| 121 | /* CM_AUTOIDLE_PLL_MPU */ | |
| 122 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | |
| 123 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | |
| 124 | ||
| 125 | /* CM_CLKSEL1_PLL_MPU */ | |
| 126 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | |
| 127 | #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) | |
| 128 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | |
| 129 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | |
| 130 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | |
| 131 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | |
| 132 | ||
| 133 | /* CM_CLKSEL2_PLL_MPU */ | |
| 134 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | |
| 135 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
| 136 | ||
| 137 | /* CM_CLKSTCTRL_MPU */ | |
| 138 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | |
| 139 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | |
| 140 | ||
| 141 | /* CM_CLKSTST_MPU */ | |
| 801954d3 PW |
142 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 |
| 143 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | |
| c595713d TL |
144 | |
| 145 | /* CM_FCLKEN1_CORE specific bits */ | |
| 2bc4ef71 | 146 | #define OMAP3430_EN_MODEM_MASK (1 << 31) |
| 8111b221 | 147 | #define OMAP3430_EN_MODEM_SHIFT 31 |
| c595713d TL |
148 | |
| 149 | /* CM_ICLKEN1_CORE specific bits */ | |
| 2bc4ef71 | 150 | #define OMAP3430_EN_ICR_MASK (1 << 29) |
| c595713d | 151 | #define OMAP3430_EN_ICR_SHIFT 29 |
| 2bc4ef71 | 152 | #define OMAP3430_EN_AES2_MASK (1 << 28) |
| c595713d | 153 | #define OMAP3430_EN_AES2_SHIFT 28 |
| 2bc4ef71 | 154 | #define OMAP3430_EN_SHA12_MASK (1 << 27) |
| c595713d | 155 | #define OMAP3430_EN_SHA12_SHIFT 27 |
| 2bc4ef71 | 156 | #define OMAP3430_EN_DES2_MASK (1 << 26) |
| c595713d | 157 | #define OMAP3430_EN_DES2_SHIFT 26 |
| 2bc4ef71 | 158 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) |
| c595713d | 159 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
| 2bc4ef71 | 160 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) |
| c595713d | 161 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
| 2bc4ef71 | 162 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) |
| c595713d | 163 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
| 2bc4ef71 | 164 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) |
| 8111b221 | 165 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
| 2bc4ef71 | 166 | #define OMAP3430_EN_SDRC_MASK (1 << 1) |
| c595713d TL |
167 | #define OMAP3430_EN_SDRC_SHIFT 1 |
| 168 | ||
| 3cc4a2fc RL |
169 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
| 170 | #define AM35XX_EN_IPSS_MASK (1 << 4) | |
| 171 | #define AM35XX_EN_IPSS_SHIFT 4 | |
| 2bc4ef71 | 172 | #define AM35XX_EN_UART4_MASK (1 << 23) |
| 3cc4a2fc RL |
173 | #define AM35XX_EN_UART4_SHIFT 23 |
| 174 | ||
| c595713d | 175 | /* CM_ICLKEN2_CORE */ |
| 2bc4ef71 | 176 | #define OMAP3430_EN_PKA_MASK (1 << 4) |
| c595713d | 177 | #define OMAP3430_EN_PKA_SHIFT 4 |
| 2bc4ef71 | 178 | #define OMAP3430_EN_AES1_MASK (1 << 3) |
| c595713d | 179 | #define OMAP3430_EN_AES1_SHIFT 3 |
| 2bc4ef71 | 180 | #define OMAP3430_EN_RNG_MASK (1 << 2) |
| c595713d | 181 | #define OMAP3430_EN_RNG_SHIFT 2 |
| 2bc4ef71 | 182 | #define OMAP3430_EN_SHA11_MASK (1 << 1) |
| c595713d | 183 | #define OMAP3430_EN_SHA11_SHIFT 1 |
| 2bc4ef71 | 184 | #define OMAP3430_EN_DES1_MASK (1 << 0) |
| c595713d TL |
185 | #define OMAP3430_EN_DES1_SHIFT 0 |
| 186 | ||
| 8111b221 KH |
187 | /* CM_ICLKEN3_CORE */ |
| 188 | #define OMAP3430_EN_MAD2D_SHIFT 3 | |
| 2bc4ef71 | 189 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) |
| 8111b221 | 190 | |
| c595713d TL |
191 | /* CM_FCLKEN3_CORE specific bits */ |
| 192 | #define OMAP3430ES2_EN_TS_SHIFT 1 | |
| 193 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | |
| 194 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | |
| 195 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | |
| 196 | ||
| 197 | /* CM_IDLEST1_CORE specific bits */ | |
| da0747d4 PW |
198 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
| 199 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | |
| 200 | #define OMAP3430_ST_ICR_SHIFT 29 | |
| 201 | #define OMAP3430_ST_ICR_MASK (1 << 29) | |
| 202 | #define OMAP3430_ST_AES2_SHIFT 28 | |
| 203 | #define OMAP3430_ST_AES2_MASK (1 << 28) | |
| 204 | #define OMAP3430_ST_SHA12_SHIFT 27 | |
| 205 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | |
| 206 | #define OMAP3430_ST_DES2_SHIFT 26 | |
| 207 | #define OMAP3430_ST_DES2_MASK (1 << 26) | |
| 208 | #define OMAP3430_ST_MSPRO_SHIFT 23 | |
| 209 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | |
| 210 | #define OMAP3430_ST_HDQ_SHIFT 22 | |
| 211 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | |
| 212 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | |
| 213 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | |
| 214 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | |
| 215 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | |
| 216 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | |
| 217 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | |
| 218 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | |
| 219 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | |
| 220 | #define OMAP3430_ST_SDMA_SHIFT 2 | |
| 221 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | |
| 222 | #define OMAP3430_ST_SDRC_SHIFT 1 | |
| 223 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | |
| 224 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | |
| 225 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | |
| c595713d | 226 | |
| 3cc4a2fc RL |
227 | /* AM35xx specific CM_IDLEST1_CORE bits */ |
| 228 | #define AM35XX_ST_IPSS_SHIFT 5 | |
| 229 | #define AM35XX_ST_IPSS_MASK (1 << 5) | |
| 230 | ||
| c595713d | 231 | /* CM_IDLEST2_CORE */ |
| da0747d4 PW |
232 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 233 | #define OMAP3430_ST_PKA_MASK (1 << 4) | |
| 234 | #define OMAP3430_ST_AES1_SHIFT 3 | |
| 235 | #define OMAP3430_ST_AES1_MASK (1 << 3) | |
| 236 | #define OMAP3430_ST_RNG_SHIFT 2 | |
| 237 | #define OMAP3430_ST_RNG_MASK (1 << 2) | |
| 238 | #define OMAP3430_ST_SHA11_SHIFT 1 | |
| 239 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | |
| 240 | #define OMAP3430_ST_DES1_SHIFT 0 | |
| 241 | #define OMAP3430_ST_DES1_MASK (1 << 0) | |
| c595713d TL |
242 | |
| 243 | /* CM_IDLEST3_CORE */ | |
| 244 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | |
| 245 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | |
| da0747d4 PW |
246 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 |
| 247 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | |
| c595713d TL |
248 | |
| 249 | /* CM_AUTOIDLE1_CORE */ | |
| 2bc4ef71 | 250 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) |
| 8111b221 | 251 | #define OMAP3430_AUTO_MODEM_SHIFT 31 |
| 2bc4ef71 | 252 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) |
| 027d8ded | 253 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 |
| 2bc4ef71 | 254 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) |
| 027d8ded | 255 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 |
| 2bc4ef71 | 256 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) |
| c595713d | 257 | #define OMAP3430_AUTO_AES2_SHIFT 28 |
| 2bc4ef71 | 258 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) |
| c595713d | 259 | #define OMAP3430_AUTO_SHA12_SHIFT 27 |
| 2bc4ef71 | 260 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) |
| c595713d | 261 | #define OMAP3430_AUTO_DES2_SHIFT 26 |
| 2bc4ef71 | 262 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) |
| c595713d | 263 | #define OMAP3430_AUTO_MMC2_SHIFT 25 |
| 2bc4ef71 | 264 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) |
| c595713d | 265 | #define OMAP3430_AUTO_MMC1_SHIFT 24 |
| 2bc4ef71 | 266 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) |
| c595713d | 267 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 |
| 2bc4ef71 | 268 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) |
| c595713d | 269 | #define OMAP3430_AUTO_HDQ_SHIFT 22 |
| 2bc4ef71 | 270 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) |
| c595713d | 271 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 |
| 2bc4ef71 | 272 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) |
| c595713d | 273 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 |
| 2bc4ef71 | 274 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) |
| c595713d | 275 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 |
| 2bc4ef71 | 276 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) |
| c595713d | 277 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 |
| 2bc4ef71 | 278 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) |
| c595713d | 279 | #define OMAP3430_AUTO_I2C3_SHIFT 17 |
| 2bc4ef71 | 280 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) |
| c595713d | 281 | #define OMAP3430_AUTO_I2C2_SHIFT 16 |
| 2bc4ef71 | 282 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) |
| c595713d | 283 | #define OMAP3430_AUTO_I2C1_SHIFT 15 |
| 2bc4ef71 | 284 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) |
| c595713d | 285 | #define OMAP3430_AUTO_UART2_SHIFT 14 |
| 2bc4ef71 | 286 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) |
| c595713d | 287 | #define OMAP3430_AUTO_UART1_SHIFT 13 |
| 2bc4ef71 | 288 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) |
| c595713d | 289 | #define OMAP3430_AUTO_GPT11_SHIFT 12 |
| 2bc4ef71 | 290 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) |
| c595713d | 291 | #define OMAP3430_AUTO_GPT10_SHIFT 11 |
| 2bc4ef71 | 292 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) |
| c595713d | 293 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 |
| 2bc4ef71 | 294 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) |
| c595713d | 295 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 |
| 2bc4ef71 | 296 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) |
| c595713d | 297 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 |
| 2bc4ef71 | 298 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) |
| c595713d | 299 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 |
| 2bc4ef71 | 300 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) |
| c595713d | 301 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 |
| 2bc4ef71 | 302 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) |
| c595713d | 303 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 |
| 2bc4ef71 | 304 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) |
| c595713d | 305 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 |
| 2bc4ef71 | 306 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) |
| c595713d | 307 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 |
| 2bc4ef71 | 308 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) |
| 8111b221 | 309 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 |
| 2bc4ef71 | 310 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) |
| c595713d TL |
311 | #define OMAP3430_AUTO_SSI_SHIFT 0 |
| 312 | ||
| 313 | /* CM_AUTOIDLE2_CORE */ | |
| 2bc4ef71 | 314 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) |
| c595713d | 315 | #define OMAP3430_AUTO_PKA_SHIFT 4 |
| 2bc4ef71 | 316 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) |
| c595713d | 317 | #define OMAP3430_AUTO_AES1_SHIFT 3 |
| 2bc4ef71 | 318 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) |
| c595713d | 319 | #define OMAP3430_AUTO_RNG_SHIFT 2 |
| 2bc4ef71 | 320 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) |
| c595713d | 321 | #define OMAP3430_AUTO_SHA11_SHIFT 1 |
| 2bc4ef71 | 322 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) |
| c595713d TL |
323 | #define OMAP3430_AUTO_DES1_SHIFT 0 |
| 324 | ||
| 325 | /* CM_AUTOIDLE3_CORE */ | |
| 027d8ded JH |
326 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) |
| 327 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
| 328 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | |
| c595713d TL |
329 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
| 330 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | |
| 8111b221 | 331 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 |
| 2bc4ef71 | 332 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) |
| c595713d TL |
333 | |
| 334 | /* CM_CLKSEL_CORE */ | |
| 335 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | |
| 336 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | |
| 337 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | |
| 338 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | |
| 339 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | |
| 340 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | |
| 341 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | |
| 342 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | |
| 343 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | |
| 344 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | |
| 345 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | |
| 346 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | |
| 7356f0b2 VB |
347 | #define OMAP3630_CLKSEL_96M_SHIFT 12 |
| 348 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | |
| c595713d TL |
349 | |
| 350 | /* CM_CLKSTCTRL_CORE */ | |
| 351 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | |
| 352 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | |
| 353 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | |
| 354 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | |
| 355 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | |
| 356 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | |
| 357 | ||
| 358 | /* CM_CLKSTST_CORE */ | |
| 801954d3 PW |
359 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 |
| 360 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | |
| 361 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | |
| 362 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | |
| 363 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | |
| 364 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | |
| c595713d TL |
365 | |
| 366 | /* CM_FCLKEN_GFX */ | |
| 2bc4ef71 | 367 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) |
| c595713d | 368 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
| 2bc4ef71 | 369 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) |
| c595713d TL |
370 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
| 371 | ||
| 372 | /* CM_ICLKEN_GFX specific bits */ | |
| 373 | ||
| 374 | /* CM_IDLEST_GFX specific bits */ | |
| 375 | ||
| 376 | /* CM_CLKSEL_GFX specific bits */ | |
| 377 | ||
| 378 | /* CM_SLEEPDEP_GFX specific bits */ | |
| 379 | ||
| 380 | /* CM_CLKSTCTRL_GFX */ | |
| 381 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | |
| 382 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | |
| 383 | ||
| 384 | /* CM_CLKSTST_GFX */ | |
| 801954d3 PW |
385 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 |
| 386 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | |
| c595713d TL |
387 | |
| 388 | /* CM_FCLKEN_SGX */ | |
| 712d7c86 DS |
389 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 390 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | |
| 391 | ||
| b024b542 TK |
392 | /* CM_IDLEST_SGX */ |
| 393 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | |
| 394 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | |
| 395 | ||
| 712d7c86 DS |
396 | /* CM_ICLKEN_SGX */ |
| 397 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | |
| 398 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | |
| c595713d TL |
399 | |
| 400 | /* CM_CLKSEL_SGX */ | |
| 401 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | |
| 402 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | |
| 403 | ||
| 801954d3 PW |
404 | /* CM_CLKSTCTRL_SGX */ |
| 405 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | |
| 406 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | |
| 407 | ||
| 408 | /* CM_CLKSTST_SGX */ | |
| 409 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | |
| 410 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | |
| 411 | ||
| c595713d TL |
412 | /* CM_FCLKEN_WKUP specific bits */ |
| 413 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | |
| da0747d4 | 414 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) |
| c595713d TL |
415 | |
| 416 | /* CM_ICLKEN_WKUP specific bits */ | |
| 2bc4ef71 | 417 | #define OMAP3430_EN_WDT1_MASK (1 << 4) |
| c595713d | 418 | #define OMAP3430_EN_WDT1_SHIFT 4 |
| 2bc4ef71 | 419 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) |
| c595713d TL |
420 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 421 | ||
| 422 | /* CM_IDLEST_WKUP specific bits */ | |
| da0747d4 PW |
423 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
| 424 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | |
| 425 | #define OMAP3430_ST_WDT2_SHIFT 5 | |
| 426 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | |
| 427 | #define OMAP3430_ST_WDT1_SHIFT 4 | |
| 428 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | |
| 429 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | |
| 430 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | |
| c595713d TL |
431 | |
| 432 | /* CM_AUTOIDLE_WKUP */ | |
| 2bc4ef71 | 433 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) |
| da0747d4 | 434 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 |
| 2bc4ef71 | 435 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) |
| c595713d | 436 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
| 2bc4ef71 | 437 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) |
| c595713d | 438 | #define OMAP3430_AUTO_WDT1_SHIFT 4 |
| 2bc4ef71 | 439 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) |
| c595713d | 440 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 |
| 2bc4ef71 | 441 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) |
| c595713d | 442 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 |
| 2bc4ef71 | 443 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) |
| c595713d | 444 | #define OMAP3430_AUTO_GPT12_SHIFT 1 |
| 2bc4ef71 | 445 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) |
| c595713d TL |
446 | #define OMAP3430_AUTO_GPT1_SHIFT 0 |
| 447 | ||
| 448 | /* CM_CLKSEL_WKUP */ | |
| 449 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | |
| 450 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | |
| 451 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | |
| 452 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | |
| 453 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | |
| 454 | ||
| 455 | /* CM_CLKEN_PLL */ | |
| 456 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | |
| 457 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | |
| 458 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | |
| 459 | #define OMAP3430_PWRDN_TV_SHIFT 28 | |
| 460 | #define OMAP3430_PWRDN_96M_SHIFT 27 | |
| 461 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | |
| 462 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | |
| 463 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | |
| 464 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | |
| 465 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | |
| 466 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | |
| 467 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | |
| 468 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | |
| 469 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | |
| 470 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | |
| 471 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 472 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | |
| 473 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | |
| 474 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | |
| 475 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 476 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | |
| 477 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | |
| 478 | ||
| 479 | /* CM_CLKEN2_PLL */ | |
| 2bc4ef71 | 480 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 |
| c595713d TL |
481 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) |
| 482 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | |
| 483 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | |
| 484 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | |
| 485 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | |
| 486 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | |
| 487 | ||
| 488 | /* CM_IDLEST_CKGEN */ | |
| 2bc4ef71 PW |
489 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) |
| 490 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) | |
| 491 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) | |
| 492 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) | |
| 542313cc PW |
493 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 |
| 494 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | |
| 495 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | |
| 496 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | |
| c595713d TL |
497 | |
| 498 | /* CM_IDLEST2_CKGEN */ | |
| da0747d4 PW |
499 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 |
| 500 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | |
| c595713d TL |
501 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| 502 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | |
| 503 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | |
| 504 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | |
| 505 | ||
| 506 | /* CM_AUTOIDLE_PLL */ | |
| 507 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | |
| 508 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | |
| 509 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | |
| 510 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | |
| 511 | ||
| 542313cc PW |
512 | /* CM_AUTOIDLE2_PLL */ |
| 513 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | |
| 514 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | |
| 515 | ||
| c595713d TL |
516 | /* CM_CLKSEL1_PLL */ |
| 517 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | |
| 518 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | |
| 519 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | |
| 520 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | |
| 521 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | |
| 522 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | |
| 523 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | |
| 9cfd985e PW |
524 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 525 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | |
| 526 | #define OMAP3430_SOURCE_54M_SHIFT 5 | |
| 527 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | |
| 528 | #define OMAP3430_SOURCE_48M_SHIFT 3 | |
| 529 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | |
| c595713d TL |
530 | |
| 531 | /* CM_CLKSEL2_PLL */ | |
| 532 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | |
| 533 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | |
| 358965d7 | 534 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) |
| c595713d TL |
535 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 |
| 536 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | |
| 358965d7 RW |
537 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 |
| 538 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | |
| 539 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | |
| 540 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | |
| c595713d TL |
541 | |
| 542 | /* CM_CLKSEL3_PLL */ | |
| 543 | #define OMAP3430_DIV_96M_SHIFT 0 | |
| 544 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | |
| 678bc9a2 | 545 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) |
| c595713d TL |
546 | |
| 547 | /* CM_CLKSEL4_PLL */ | |
| 548 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | |
| 549 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | |
| 550 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | |
| 551 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | |
| 552 | ||
| 553 | /* CM_CLKSEL5_PLL */ | |
| 554 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | |
| 555 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | |
| 556 | ||
| 557 | /* CM_CLKOUT_CTRL */ | |
| 558 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | |
| 2bc4ef71 | 559 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) |
| c595713d TL |
560 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
| 561 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | |
| 562 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | |
| 563 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | |
| 564 | ||
| 565 | /* CM_FCLKEN_DSS */ | |
| 2bc4ef71 | 566 | #define OMAP3430_EN_TV_MASK (1 << 2) |
| c595713d | 567 | #define OMAP3430_EN_TV_SHIFT 2 |
| 2bc4ef71 | 568 | #define OMAP3430_EN_DSS2_MASK (1 << 1) |
| c595713d | 569 | #define OMAP3430_EN_DSS2_SHIFT 1 |
| 2bc4ef71 | 570 | #define OMAP3430_EN_DSS1_MASK (1 << 0) |
| c595713d TL |
571 | #define OMAP3430_EN_DSS1_SHIFT 0 |
| 572 | ||
| 573 | /* CM_ICLKEN_DSS */ | |
| 2bc4ef71 | 574 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) |
| c595713d TL |
575 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 576 | ||
| 577 | /* CM_IDLEST_DSS */ | |
| da0747d4 PW |
578 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 579 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | |
| 580 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | |
| 581 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | |
| 582 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | |
| 583 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | |
| c595713d TL |
584 | |
| 585 | /* CM_AUTOIDLE_DSS */ | |
| 2bc4ef71 | 586 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) |
| c595713d TL |
587 | #define OMAP3430_AUTO_DSS_SHIFT 0 |
| 588 | ||
| 589 | /* CM_CLKSEL_DSS */ | |
| 590 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | |
| 591 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | |
| 678bc9a2 | 592 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) |
| c595713d TL |
593 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
| 594 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | |
| 678bc9a2 | 595 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) |
| c595713d TL |
596 | |
| 597 | /* CM_SLEEPDEP_DSS specific bits */ | |
| 598 | ||
| 599 | /* CM_CLKSTCTRL_DSS */ | |
| 600 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | |
| 601 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | |
| 602 | ||
| 603 | /* CM_CLKSTST_DSS */ | |
| 801954d3 PW |
604 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 |
| 605 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | |
| c595713d TL |
606 | |
| 607 | /* CM_FCLKEN_CAM specific bits */ | |
| 2bc4ef71 | 608 | #define OMAP3430_EN_CSI2_MASK (1 << 1) |
| 6c8fe0b9 | 609 | #define OMAP3430_EN_CSI2_SHIFT 1 |
| c595713d TL |
610 | |
| 611 | /* CM_ICLKEN_CAM specific bits */ | |
| 612 | ||
| 613 | /* CM_IDLEST_CAM */ | |
| 2bc4ef71 | 614 | #define OMAP3430_ST_CAM_MASK (1 << 0) |
| c595713d TL |
615 | |
| 616 | /* CM_AUTOIDLE_CAM */ | |
| 2bc4ef71 | 617 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) |
| c595713d TL |
618 | #define OMAP3430_AUTO_CAM_SHIFT 0 |
| 619 | ||
| 620 | /* CM_CLKSEL_CAM */ | |
| 621 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | |
| 622 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | |
| 678bc9a2 | 623 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) |
| c595713d TL |
624 | |
| 625 | /* CM_SLEEPDEP_CAM specific bits */ | |
| 626 | ||
| 627 | /* CM_CLKSTCTRL_CAM */ | |
| 628 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | |
| 629 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | |
| 630 | ||
| 631 | /* CM_CLKSTST_CAM */ | |
| 801954d3 PW |
632 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 |
| 633 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | |
| c595713d TL |
634 | |
| 635 | /* CM_FCLKEN_PER specific bits */ | |
| 636 | ||
| 637 | /* CM_ICLKEN_PER specific bits */ | |
| 638 | ||
| 639 | /* CM_IDLEST_PER */ | |
| da0747d4 PW |
640 | #define OMAP3430_ST_WDT3_SHIFT 12 |
| 641 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | |
| 642 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | |
| 643 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | |
| 644 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | |
| 645 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | |
| 646 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | |
| 647 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | |
| c595713d TL |
648 | |
| 649 | /* CM_AUTOIDLE_PER */ | |
| e5863689 G |
650 | #define OMAP3630_AUTO_UART4_MASK (1 << 18) |
| 651 | #define OMAP3630_AUTO_UART4_SHIFT 18 | |
| 2bc4ef71 | 652 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) |
| c595713d | 653 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 |
| 2bc4ef71 | 654 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) |
| c595713d | 655 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 |
| 2bc4ef71 | 656 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) |
| c595713d | 657 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 |
| 2bc4ef71 | 658 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) |
| c595713d | 659 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 |
| 2bc4ef71 | 660 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) |
| c595713d | 661 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 |
| 2bc4ef71 | 662 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) |
| c595713d | 663 | #define OMAP3430_AUTO_WDT3_SHIFT 12 |
| 2bc4ef71 | 664 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) |
| c595713d | 665 | #define OMAP3430_AUTO_UART3_SHIFT 11 |
| 2bc4ef71 | 666 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) |
| c595713d | 667 | #define OMAP3430_AUTO_GPT9_SHIFT 10 |
| 2bc4ef71 | 668 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) |
| c595713d | 669 | #define OMAP3430_AUTO_GPT8_SHIFT 9 |
| 2bc4ef71 | 670 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) |
| c595713d | 671 | #define OMAP3430_AUTO_GPT7_SHIFT 8 |
| 2bc4ef71 | 672 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) |
| c595713d | 673 | #define OMAP3430_AUTO_GPT6_SHIFT 7 |
| 2bc4ef71 | 674 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) |
| c595713d | 675 | #define OMAP3430_AUTO_GPT5_SHIFT 6 |
| 2bc4ef71 | 676 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) |
| c595713d | 677 | #define OMAP3430_AUTO_GPT4_SHIFT 5 |
| 2bc4ef71 | 678 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) |
| c595713d | 679 | #define OMAP3430_AUTO_GPT3_SHIFT 4 |
| 2bc4ef71 | 680 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) |
| c595713d | 681 | #define OMAP3430_AUTO_GPT2_SHIFT 3 |
| 2bc4ef71 | 682 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) |
| c595713d | 683 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 |
| 2bc4ef71 | 684 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) |
| c595713d | 685 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 |
| 2bc4ef71 | 686 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) |
| c595713d TL |
687 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 |
| 688 | ||
| 689 | /* CM_CLKSEL_PER */ | |
| 690 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | |
| 691 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | |
| 692 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | |
| 693 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | |
| 694 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | |
| 695 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | |
| 696 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | |
| 697 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | |
| 698 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | |
| 699 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | |
| 700 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | |
| 701 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | |
| 702 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | |
| 703 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | |
| 704 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | |
| 705 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | |
| 706 | ||
| 707 | /* CM_SLEEPDEP_PER specific bits */ | |
| 2bc4ef71 | 708 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) |
| c595713d TL |
709 | |
| 710 | /* CM_CLKSTCTRL_PER */ | |
| 711 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | |
| 712 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | |
| 713 | ||
| 714 | /* CM_CLKSTST_PER */ | |
| 801954d3 PW |
715 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 |
| 716 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | |
| c595713d TL |
717 | |
| 718 | /* CM_CLKSEL1_EMU */ | |
| 719 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | |
| 720 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | |
| 678bc9a2 | 721 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) |
| c595713d TL |
722 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
| 723 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | |
| 724 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | |
| 725 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | |
| 726 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | |
| 727 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | |
| 728 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | |
| 729 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | |
| 730 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | |
| 731 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | |
| 732 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | |
| 733 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | |
| 734 | #define OMAP3430_MUX_CTRL_SHIFT 0 | |
| 735 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | |
| 736 | ||
| 737 | /* CM_CLKSTCTRL_EMU */ | |
| 738 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | |
| 739 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | |
| 740 | ||
| 741 | /* CM_CLKSTST_EMU */ | |
| 801954d3 PW |
742 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 |
| 743 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | |
| c595713d TL |
744 | |
| 745 | /* CM_CLKSEL2_EMU specific bits */ | |
| 746 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | |
| 747 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
| 748 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | |
| 749 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | |
| 750 | ||
| 751 | /* CM_CLKSEL3_EMU specific bits */ | |
| 752 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | |
| 753 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
| 754 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | |
| 755 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | |
| 756 | ||
| 757 | /* CM_POLCTRL */ | |
| 2bc4ef71 | 758 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) |
| c595713d TL |
759 | |
| 760 | /* CM_IDLEST_NEON */ | |
| 2bc4ef71 | 761 | #define OMAP3430_ST_NEON_MASK (1 << 0) |
| c595713d TL |
762 | |
| 763 | /* CM_CLKSTCTRL_NEON */ | |
| 764 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | |
| 765 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | |
| 766 | ||
| 767 | /* CM_FCLKEN_USBHOST */ | |
| 768 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | |
| 769 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | |
| 770 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | |
| 771 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | |
| 772 | ||
| 773 | /* CM_ICLKEN_USBHOST */ | |
| 774 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | |
| 775 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | |
| 776 | ||
| 777 | /* CM_IDLEST_USBHOST */ | |
| da0747d4 PW |
778 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
| 779 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | |
| 780 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | |
| 781 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | |
| c595713d TL |
782 | |
| 783 | /* CM_AUTOIDLE_USBHOST */ | |
| 784 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
| 785 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | |
| 786 | ||
| 787 | /* CM_SLEEPDEP_USBHOST */ | |
| 788 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | |
| 789 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | |
| 790 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | |
| 791 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | |
| 792 | ||
| 793 | /* CM_CLKSTCTRL_USBHOST */ | |
| 794 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | |
| 795 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | |
| 796 | ||
| 801954d3 PW |
797 | /* CM_CLKSTST_USBHOST */ |
| 798 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | |
| 799 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | |
| c595713d | 800 | |
| bd2122ca PW |
801 | /* |
| 802 | * | |
| 803 | */ | |
| 804 | ||
| 805 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | |
| 806 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | |
| 807 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | |
| 808 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | |
| 809 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | |
| 810 | ||
| 811 | ||
| c595713d | 812 | #endif |