projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c595713d TL |
1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H |
| 2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H | |
| 3 | ||
| 4 | /* | |
| 5 | * OMAP3430 Clock Management register bits | |
| 6 | * | |
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | |
| 9 | * | |
| 10 | * Written by Paul Walmsley | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | */ | |
| 16 | ||
| 17 | #include "cm.h" | |
| 18 | ||
| 19 | /* Bits shared between registers */ | |
| 20 | ||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | |
| 22 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | |
| 23 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | |
| 24 | #define OMAP3430_EN_MSPRO (1 << 23) | |
| 25 | #define OMAP3430_EN_MSPRO_SHIFT 23 | |
| 26 | #define OMAP3430_EN_HDQ (1 << 22) | |
| 27 | #define OMAP3430_EN_HDQ_SHIFT 22 | |
| 28 | #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) | |
| 29 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | |
| 30 | #define OMAP3430ES1_EN_D2D (1 << 3) | |
| 31 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | |
| 32 | #define OMAP3430_EN_SSI (1 << 0) | |
| 33 | #define OMAP3430_EN_SSI_SHIFT 0 | |
| 34 | ||
| 35 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | |
| 36 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | |
| 37 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | |
| 38 | ||
| 39 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | |
| 40 | #define OMAP3430_EN_WDT2 (1 << 5) | |
| 41 | #define OMAP3430_EN_WDT2_SHIFT 5 | |
| 42 | ||
| 43 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | |
| 44 | #define OMAP3430_EN_CAM (1 << 0) | |
| 45 | #define OMAP3430_EN_CAM_SHIFT 0 | |
| 46 | ||
| 47 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | |
| 48 | #define OMAP3430_EN_WDT3 (1 << 12) | |
| 49 | #define OMAP3430_EN_WDT3_SHIFT 12 | |
| 50 | ||
| 51 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | |
| 52 | #define OMAP3430_OVERRIDE_ENABLE (1 << 19) | |
| 53 | ||
| 54 | ||
| 55 | /* Bits specific to each register */ | |
| 56 | ||
| 57 | /* CM_FCLKEN_IVA2 */ | |
| dfa6d6f8 | 58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
| 31c203d4 | 59 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
| c595713d TL |
60 | |
| 61 | /* CM_CLKEN_PLL_IVA2 */ | |
| 62 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | |
| 63 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 64 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | |
| 65 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | |
| 66 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | |
| 67 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 68 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | |
| 69 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | |
| 70 | ||
| 71 | /* CM_IDLEST_IVA2 */ | |
| 72 | #define OMAP3430_ST_IVA2 (1 << 0) | |
| 73 | ||
| 74 | /* CM_IDLEST_PLL_IVA2 */ | |
| 542313cc PW |
75 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 |
| 76 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | |
| c595713d TL |
77 | |
| 78 | /* CM_AUTOIDLE_PLL_IVA2 */ | |
| 79 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | |
| 80 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | |
| 81 | ||
| 82 | /* CM_CLKSEL1_PLL_IVA2 */ | |
| 83 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | |
| 84 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) | |
| 85 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | |
| 86 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | |
| 87 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | |
| 88 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | |
| 89 | ||
| 90 | /* CM_CLKSEL2_PLL_IVA2 */ | |
| 91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | |
| 92 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
| 93 | ||
| 94 | /* CM_CLKSTCTRL_IVA2 */ | |
| 95 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | |
| 96 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | |
| 97 | ||
| 98 | /* CM_CLKSTST_IVA2 */ | |
| 801954d3 PW |
99 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 |
| 100 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | |
| c595713d TL |
101 | |
| 102 | /* CM_REVISION specific bits */ | |
| 103 | ||
| 104 | /* CM_SYSCONFIG specific bits */ | |
| 105 | ||
| 106 | /* CM_CLKEN_PLL_MPU */ | |
| 107 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | |
| 108 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 109 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | |
| 110 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | |
| 111 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | |
| 112 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 113 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | |
| 114 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | |
| 115 | ||
| 116 | /* CM_IDLEST_MPU */ | |
| 117 | #define OMAP3430_ST_MPU (1 << 0) | |
| 118 | ||
| 119 | /* CM_IDLEST_PLL_MPU */ | |
| 542313cc | 120 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 3760d31f | 121 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| c595713d TL |
122 | |
| 123 | /* CM_AUTOIDLE_PLL_MPU */ | |
| 124 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | |
| 125 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | |
| 126 | ||
| 127 | /* CM_CLKSEL1_PLL_MPU */ | |
| 128 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | |
| 129 | #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) | |
| 130 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | |
| 131 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | |
| 132 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | |
| 133 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | |
| 134 | ||
| 135 | /* CM_CLKSEL2_PLL_MPU */ | |
| 136 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | |
| 137 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
| 138 | ||
| 139 | /* CM_CLKSTCTRL_MPU */ | |
| 140 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | |
| 141 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | |
| 142 | ||
| 143 | /* CM_CLKSTST_MPU */ | |
| 801954d3 PW |
144 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 |
| 145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | |
| c595713d TL |
146 | |
| 147 | /* CM_FCLKEN1_CORE specific bits */ | |
| 8111b221 KH |
148 | #define OMAP3430_EN_MODEM (1 << 31) |
| 149 | #define OMAP3430_EN_MODEM_SHIFT 31 | |
| c595713d TL |
150 | |
| 151 | /* CM_ICLKEN1_CORE specific bits */ | |
| 152 | #define OMAP3430_EN_ICR (1 << 29) | |
| 153 | #define OMAP3430_EN_ICR_SHIFT 29 | |
| 154 | #define OMAP3430_EN_AES2 (1 << 28) | |
| 155 | #define OMAP3430_EN_AES2_SHIFT 28 | |
| 156 | #define OMAP3430_EN_SHA12 (1 << 27) | |
| 157 | #define OMAP3430_EN_SHA12_SHIFT 27 | |
| 158 | #define OMAP3430_EN_DES2 (1 << 26) | |
| 159 | #define OMAP3430_EN_DES2_SHIFT 26 | |
| 160 | #define OMAP3430ES1_EN_FAC (1 << 8) | |
| 161 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | |
| 162 | #define OMAP3430_EN_MAILBOXES (1 << 7) | |
| 163 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | |
| 164 | #define OMAP3430_EN_OMAPCTRL (1 << 6) | |
| 165 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | |
| 8111b221 KH |
166 | #define OMAP3430_EN_SAD2D (1 << 3) |
| 167 | #define OMAP3430_EN_SAD2D_SHIFT 3 | |
| c595713d TL |
168 | #define OMAP3430_EN_SDRC (1 << 1) |
| 169 | #define OMAP3430_EN_SDRC_SHIFT 1 | |
| 170 | ||
| 3cc4a2fc RL |
171 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
| 172 | #define AM35XX_EN_IPSS_MASK (1 << 4) | |
| 173 | #define AM35XX_EN_IPSS_SHIFT 4 | |
| 174 | #define AM35XX_EN_UART4_MASK (1 << 23) | |
| 175 | #define AM35XX_EN_UART4_SHIFT 23 | |
| 176 | ||
| c595713d TL |
177 | /* CM_ICLKEN2_CORE */ |
| 178 | #define OMAP3430_EN_PKA (1 << 4) | |
| 179 | #define OMAP3430_EN_PKA_SHIFT 4 | |
| 180 | #define OMAP3430_EN_AES1 (1 << 3) | |
| 181 | #define OMAP3430_EN_AES1_SHIFT 3 | |
| 182 | #define OMAP3430_EN_RNG (1 << 2) | |
| 183 | #define OMAP3430_EN_RNG_SHIFT 2 | |
| 184 | #define OMAP3430_EN_SHA11 (1 << 1) | |
| 185 | #define OMAP3430_EN_SHA11_SHIFT 1 | |
| 186 | #define OMAP3430_EN_DES1 (1 << 0) | |
| 187 | #define OMAP3430_EN_DES1_SHIFT 0 | |
| 188 | ||
| 8111b221 KH |
189 | /* CM_ICLKEN3_CORE */ |
| 190 | #define OMAP3430_EN_MAD2D_SHIFT 3 | |
| 191 | #define OMAP3430_EN_MAD2D (1 << 3) | |
| 192 | ||
| c595713d TL |
193 | /* CM_FCLKEN3_CORE specific bits */ |
| 194 | #define OMAP3430ES2_EN_TS_SHIFT 1 | |
| 195 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | |
| 196 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | |
| 197 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | |
| 198 | ||
| 199 | /* CM_IDLEST1_CORE specific bits */ | |
| da0747d4 PW |
200 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
| 201 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | |
| 202 | #define OMAP3430_ST_ICR_SHIFT 29 | |
| 203 | #define OMAP3430_ST_ICR_MASK (1 << 29) | |
| 204 | #define OMAP3430_ST_AES2_SHIFT 28 | |
| 205 | #define OMAP3430_ST_AES2_MASK (1 << 28) | |
| 206 | #define OMAP3430_ST_SHA12_SHIFT 27 | |
| 207 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | |
| 208 | #define OMAP3430_ST_DES2_SHIFT 26 | |
| 209 | #define OMAP3430_ST_DES2_MASK (1 << 26) | |
| 210 | #define OMAP3430_ST_MSPRO_SHIFT 23 | |
| 211 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | |
| 212 | #define OMAP3430_ST_HDQ_SHIFT 22 | |
| 213 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | |
| 214 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | |
| 215 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | |
| 216 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | |
| 217 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | |
| 218 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | |
| 219 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | |
| 220 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | |
| 221 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | |
| 222 | #define OMAP3430_ST_SDMA_SHIFT 2 | |
| 223 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | |
| 224 | #define OMAP3430_ST_SDRC_SHIFT 1 | |
| 225 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | |
| 226 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | |
| 227 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | |
| c595713d | 228 | |
| 3cc4a2fc RL |
229 | /* AM35xx specific CM_IDLEST1_CORE bits */ |
| 230 | #define AM35XX_ST_IPSS_SHIFT 5 | |
| 231 | #define AM35XX_ST_IPSS_MASK (1 << 5) | |
| 232 | ||
| c595713d | 233 | /* CM_IDLEST2_CORE */ |
| da0747d4 PW |
234 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 235 | #define OMAP3430_ST_PKA_MASK (1 << 4) | |
| 236 | #define OMAP3430_ST_AES1_SHIFT 3 | |
| 237 | #define OMAP3430_ST_AES1_MASK (1 << 3) | |
| 238 | #define OMAP3430_ST_RNG_SHIFT 2 | |
| 239 | #define OMAP3430_ST_RNG_MASK (1 << 2) | |
| 240 | #define OMAP3430_ST_SHA11_SHIFT 1 | |
| 241 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | |
| 242 | #define OMAP3430_ST_DES1_SHIFT 0 | |
| 243 | #define OMAP3430_ST_DES1_MASK (1 << 0) | |
| c595713d TL |
244 | |
| 245 | /* CM_IDLEST3_CORE */ | |
| 246 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | |
| 247 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | |
| da0747d4 PW |
248 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 |
| 249 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | |
| c595713d TL |
250 | |
| 251 | /* CM_AUTOIDLE1_CORE */ | |
| 8111b221 KH |
252 | #define OMAP3430_AUTO_MODEM (1 << 31) |
| 253 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | |
| 027d8ded JH |
254 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) |
| 255 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | |
| 256 | #define OMAP3430ES2_AUTO_ICR (1 << 29) | |
| 257 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | |
| c595713d TL |
258 | #define OMAP3430_AUTO_AES2 (1 << 28) |
| 259 | #define OMAP3430_AUTO_AES2_SHIFT 28 | |
| 260 | #define OMAP3430_AUTO_SHA12 (1 << 27) | |
| 261 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | |
| 262 | #define OMAP3430_AUTO_DES2 (1 << 26) | |
| 263 | #define OMAP3430_AUTO_DES2_SHIFT 26 | |
| 264 | #define OMAP3430_AUTO_MMC2 (1 << 25) | |
| 265 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | |
| 266 | #define OMAP3430_AUTO_MMC1 (1 << 24) | |
| 267 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | |
| 268 | #define OMAP3430_AUTO_MSPRO (1 << 23) | |
| 269 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | |
| 270 | #define OMAP3430_AUTO_HDQ (1 << 22) | |
| 271 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | |
| 272 | #define OMAP3430_AUTO_MCSPI4 (1 << 21) | |
| 273 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | |
| 274 | #define OMAP3430_AUTO_MCSPI3 (1 << 20) | |
| 275 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | |
| 276 | #define OMAP3430_AUTO_MCSPI2 (1 << 19) | |
| 277 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | |
| 278 | #define OMAP3430_AUTO_MCSPI1 (1 << 18) | |
| 279 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | |
| 280 | #define OMAP3430_AUTO_I2C3 (1 << 17) | |
| 281 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | |
| 282 | #define OMAP3430_AUTO_I2C2 (1 << 16) | |
| 283 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | |
| 284 | #define OMAP3430_AUTO_I2C1 (1 << 15) | |
| 285 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | |
| 286 | #define OMAP3430_AUTO_UART2 (1 << 14) | |
| 287 | #define OMAP3430_AUTO_UART2_SHIFT 14 | |
| 288 | #define OMAP3430_AUTO_UART1 (1 << 13) | |
| 289 | #define OMAP3430_AUTO_UART1_SHIFT 13 | |
| 290 | #define OMAP3430_AUTO_GPT11 (1 << 12) | |
| 291 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | |
| 292 | #define OMAP3430_AUTO_GPT10 (1 << 11) | |
| 293 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | |
| 294 | #define OMAP3430_AUTO_MCBSP5 (1 << 10) | |
| 295 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | |
| 296 | #define OMAP3430_AUTO_MCBSP1 (1 << 9) | |
| 297 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | |
| 298 | #define OMAP3430ES1_AUTO_FAC (1 << 8) | |
| 299 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | |
| 300 | #define OMAP3430_AUTO_MAILBOXES (1 << 7) | |
| 301 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | |
| 302 | #define OMAP3430_AUTO_OMAPCTRL (1 << 6) | |
| 303 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | |
| 304 | #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) | |
| 305 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | |
| 306 | #define OMAP3430_AUTO_HSOTGUSB (1 << 4) | |
| 307 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | |
| 308 | #define OMAP3430ES1_AUTO_D2D (1 << 3) | |
| 309 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | |
| 8111b221 KH |
310 | #define OMAP3430_AUTO_SAD2D (1 << 3) |
| 311 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | |
| c595713d TL |
312 | #define OMAP3430_AUTO_SSI (1 << 0) |
| 313 | #define OMAP3430_AUTO_SSI_SHIFT 0 | |
| 314 | ||
| 315 | /* CM_AUTOIDLE2_CORE */ | |
| 316 | #define OMAP3430_AUTO_PKA (1 << 4) | |
| 317 | #define OMAP3430_AUTO_PKA_SHIFT 4 | |
| 318 | #define OMAP3430_AUTO_AES1 (1 << 3) | |
| 319 | #define OMAP3430_AUTO_AES1_SHIFT 3 | |
| 320 | #define OMAP3430_AUTO_RNG (1 << 2) | |
| 321 | #define OMAP3430_AUTO_RNG_SHIFT 2 | |
| 322 | #define OMAP3430_AUTO_SHA11 (1 << 1) | |
| 323 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | |
| 324 | #define OMAP3430_AUTO_DES1 (1 << 0) | |
| 325 | #define OMAP3430_AUTO_DES1_SHIFT 0 | |
| 326 | ||
| 327 | /* CM_AUTOIDLE3_CORE */ | |
| 027d8ded JH |
328 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) |
| 329 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
| 330 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | |
| c595713d TL |
331 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
| 332 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | |
| 8111b221 KH |
333 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 |
| 334 | #define OMAP3430_AUTO_MAD2D (1 << 3) | |
| c595713d TL |
335 | |
| 336 | /* CM_CLKSEL_CORE */ | |
| 337 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | |
| 338 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | |
| 339 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | |
| 340 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | |
| 341 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | |
| 342 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | |
| 343 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | |
| 344 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | |
| 345 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | |
| 346 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | |
| 347 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | |
| 348 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | |
| 349 | ||
| 350 | /* CM_CLKSTCTRL_CORE */ | |
| 351 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | |
| 352 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | |
| 353 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | |
| 354 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | |
| 355 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | |
| 356 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | |
| 357 | ||
| 358 | /* CM_CLKSTST_CORE */ | |
| 801954d3 PW |
359 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 |
| 360 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | |
| 361 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | |
| 362 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | |
| 363 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | |
| 364 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | |
| c595713d TL |
365 | |
| 366 | /* CM_FCLKEN_GFX */ | |
| 367 | #define OMAP3430ES1_EN_3D (1 << 2) | |
| 368 | #define OMAP3430ES1_EN_3D_SHIFT 2 | |
| 369 | #define OMAP3430ES1_EN_2D (1 << 1) | |
| 370 | #define OMAP3430ES1_EN_2D_SHIFT 1 | |
| 371 | ||
| 372 | /* CM_ICLKEN_GFX specific bits */ | |
| 373 | ||
| 374 | /* CM_IDLEST_GFX specific bits */ | |
| 375 | ||
| 376 | /* CM_CLKSEL_GFX specific bits */ | |
| 377 | ||
| 378 | /* CM_SLEEPDEP_GFX specific bits */ | |
| 379 | ||
| 380 | /* CM_CLKSTCTRL_GFX */ | |
| 381 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | |
| 382 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | |
| 383 | ||
| 384 | /* CM_CLKSTST_GFX */ | |
| 801954d3 PW |
385 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 |
| 386 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | |
| c595713d TL |
387 | |
| 388 | /* CM_FCLKEN_SGX */ | |
| 712d7c86 DS |
389 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 390 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | |
| 391 | ||
| b024b542 TK |
392 | /* CM_IDLEST_SGX */ |
| 393 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | |
| 394 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | |
| 395 | ||
| 712d7c86 DS |
396 | /* CM_ICLKEN_SGX */ |
| 397 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | |
| 398 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | |
| c595713d TL |
399 | |
| 400 | /* CM_CLKSEL_SGX */ | |
| 401 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | |
| 402 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | |
| 403 | ||
| 801954d3 PW |
404 | /* CM_CLKSTCTRL_SGX */ |
| 405 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | |
| 406 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | |
| 407 | ||
| 408 | /* CM_CLKSTST_SGX */ | |
| 409 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | |
| 410 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | |
| 411 | ||
| c595713d TL |
412 | /* CM_FCLKEN_WKUP specific bits */ |
| 413 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | |
| da0747d4 | 414 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) |
| c595713d TL |
415 | |
| 416 | /* CM_ICLKEN_WKUP specific bits */ | |
| 417 | #define OMAP3430_EN_WDT1 (1 << 4) | |
| 418 | #define OMAP3430_EN_WDT1_SHIFT 4 | |
| 419 | #define OMAP3430_EN_32KSYNC (1 << 2) | |
| 420 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | |
| 421 | ||
| 422 | /* CM_IDLEST_WKUP specific bits */ | |
| da0747d4 PW |
423 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
| 424 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | |
| 425 | #define OMAP3430_ST_WDT2_SHIFT 5 | |
| 426 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | |
| 427 | #define OMAP3430_ST_WDT1_SHIFT 4 | |
| 428 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | |
| 429 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | |
| 430 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | |
| c595713d TL |
431 | |
| 432 | /* CM_AUTOIDLE_WKUP */ | |
| da0747d4 PW |
433 | #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) |
| 434 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | |
| c595713d TL |
435 | #define OMAP3430_AUTO_WDT2 (1 << 5) |
| 436 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | |
| 437 | #define OMAP3430_AUTO_WDT1 (1 << 4) | |
| 438 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | |
| 439 | #define OMAP3430_AUTO_GPIO1 (1 << 3) | |
| 440 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | |
| 441 | #define OMAP3430_AUTO_32KSYNC (1 << 2) | |
| 442 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | |
| 443 | #define OMAP3430_AUTO_GPT12 (1 << 1) | |
| 444 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | |
| 445 | #define OMAP3430_AUTO_GPT1 (1 << 0) | |
| 446 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | |
| 447 | ||
| 448 | /* CM_CLKSEL_WKUP */ | |
| 449 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | |
| 450 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | |
| 451 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | |
| 452 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | |
| 453 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | |
| 454 | ||
| 455 | /* CM_CLKEN_PLL */ | |
| 456 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | |
| 457 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | |
| 458 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | |
| 459 | #define OMAP3430_PWRDN_TV_SHIFT 28 | |
| 460 | #define OMAP3430_PWRDN_96M_SHIFT 27 | |
| 461 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | |
| 462 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | |
| 463 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | |
| 464 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | |
| 465 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | |
| 466 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | |
| 467 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | |
| 468 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | |
| 469 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | |
| 470 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | |
| 471 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 472 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | |
| 473 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | |
| 474 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | |
| 475 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | |
| 476 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | |
| 477 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | |
| 478 | ||
| 479 | /* CM_CLKEN2_PLL */ | |
| 480 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | |
| 481 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | |
| 482 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | |
| 483 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | |
| 484 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | |
| 485 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | |
| 486 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | |
| 487 | ||
| 488 | /* CM_IDLEST_CKGEN */ | |
| 489 | #define OMAP3430_ST_54M_CLK (1 << 5) | |
| 490 | #define OMAP3430_ST_12M_CLK (1 << 4) | |
| 491 | #define OMAP3430_ST_48M_CLK (1 << 3) | |
| 492 | #define OMAP3430_ST_96M_CLK (1 << 2) | |
| 542313cc PW |
493 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 |
| 494 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | |
| 495 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | |
| 496 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | |
| c595713d TL |
497 | |
| 498 | /* CM_IDLEST2_CKGEN */ | |
| da0747d4 PW |
499 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 |
| 500 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | |
| c595713d TL |
501 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| 502 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | |
| 503 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | |
| 504 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | |
| 505 | ||
| 506 | /* CM_AUTOIDLE_PLL */ | |
| 507 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | |
| 508 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | |
| 509 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | |
| 510 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | |
| 511 | ||
| 542313cc PW |
512 | /* CM_AUTOIDLE2_PLL */ |
| 513 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | |
| 514 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | |
| 515 | ||
| c595713d TL |
516 | /* CM_CLKSEL1_PLL */ |
| 517 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | |
| 518 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | |
| 519 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | |
| 520 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | |
| 521 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | |
| 522 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | |
| 523 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | |
| 9cfd985e PW |
524 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 525 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | |
| 526 | #define OMAP3430_SOURCE_54M_SHIFT 5 | |
| 527 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | |
| 528 | #define OMAP3430_SOURCE_48M_SHIFT 3 | |
| 529 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | |
| c595713d TL |
530 | |
| 531 | /* CM_CLKSEL2_PLL */ | |
| 532 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | |
| 533 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | |
| 534 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | |
| 535 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | |
| 536 | ||
| 537 | /* CM_CLKSEL3_PLL */ | |
| 538 | #define OMAP3430_DIV_96M_SHIFT 0 | |
| 539 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | |
| 540 | ||
| 541 | /* CM_CLKSEL4_PLL */ | |
| 542 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | |
| 543 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | |
| 544 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | |
| 545 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | |
| 546 | ||
| 547 | /* CM_CLKSEL5_PLL */ | |
| 548 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | |
| 549 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | |
| 550 | ||
| 551 | /* CM_CLKOUT_CTRL */ | |
| 552 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | |
| 553 | #define OMAP3430_CLKOUT2_EN (1 << 7) | |
| 554 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | |
| 555 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | |
| 556 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | |
| 557 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | |
| 558 | ||
| 559 | /* CM_FCLKEN_DSS */ | |
| 560 | #define OMAP3430_EN_TV (1 << 2) | |
| 561 | #define OMAP3430_EN_TV_SHIFT 2 | |
| 562 | #define OMAP3430_EN_DSS2 (1 << 1) | |
| 563 | #define OMAP3430_EN_DSS2_SHIFT 1 | |
| 564 | #define OMAP3430_EN_DSS1 (1 << 0) | |
| 565 | #define OMAP3430_EN_DSS1_SHIFT 0 | |
| 566 | ||
| 567 | /* CM_ICLKEN_DSS */ | |
| 568 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) | |
| 569 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | |
| 570 | ||
| 571 | /* CM_IDLEST_DSS */ | |
| da0747d4 PW |
572 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 573 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | |
| 574 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | |
| 575 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | |
| 576 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | |
| 577 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | |
| c595713d TL |
578 | |
| 579 | /* CM_AUTOIDLE_DSS */ | |
| 580 | #define OMAP3430_AUTO_DSS (1 << 0) | |
| 581 | #define OMAP3430_AUTO_DSS_SHIFT 0 | |
| 582 | ||
| 583 | /* CM_CLKSEL_DSS */ | |
| 584 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | |
| 585 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | |
| 586 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | |
| 587 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | |
| 588 | ||
| 589 | /* CM_SLEEPDEP_DSS specific bits */ | |
| 590 | ||
| 591 | /* CM_CLKSTCTRL_DSS */ | |
| 592 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | |
| 593 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | |
| 594 | ||
| 595 | /* CM_CLKSTST_DSS */ | |
| 801954d3 PW |
596 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 |
| 597 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | |
| c595713d TL |
598 | |
| 599 | /* CM_FCLKEN_CAM specific bits */ | |
| 6c8fe0b9 SA |
600 | #define OMAP3430_EN_CSI2 (1 << 1) |
| 601 | #define OMAP3430_EN_CSI2_SHIFT 1 | |
| c595713d TL |
602 | |
| 603 | /* CM_ICLKEN_CAM specific bits */ | |
| 604 | ||
| 605 | /* CM_IDLEST_CAM */ | |
| 606 | #define OMAP3430_ST_CAM (1 << 0) | |
| 607 | ||
| 608 | /* CM_AUTOIDLE_CAM */ | |
| 609 | #define OMAP3430_AUTO_CAM (1 << 0) | |
| 610 | #define OMAP3430_AUTO_CAM_SHIFT 0 | |
| 611 | ||
| 612 | /* CM_CLKSEL_CAM */ | |
| 613 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | |
| 614 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | |
| 615 | ||
| 616 | /* CM_SLEEPDEP_CAM specific bits */ | |
| 617 | ||
| 618 | /* CM_CLKSTCTRL_CAM */ | |
| 619 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | |
| 620 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | |
| 621 | ||
| 622 | /* CM_CLKSTST_CAM */ | |
| 801954d3 PW |
623 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 |
| 624 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | |
| c595713d TL |
625 | |
| 626 | /* CM_FCLKEN_PER specific bits */ | |
| 627 | ||
| 628 | /* CM_ICLKEN_PER specific bits */ | |
| 629 | ||
| 630 | /* CM_IDLEST_PER */ | |
| da0747d4 PW |
631 | #define OMAP3430_ST_WDT3_SHIFT 12 |
| 632 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | |
| 633 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | |
| 634 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | |
| 635 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | |
| 636 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | |
| 637 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | |
| 638 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | |
| c595713d TL |
639 | |
| 640 | /* CM_AUTOIDLE_PER */ | |
| 641 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | |
| 642 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | |
| 643 | #define OMAP3430_AUTO_GPIO5 (1 << 16) | |
| 644 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | |
| 645 | #define OMAP3430_AUTO_GPIO4 (1 << 15) | |
| 646 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | |
| 647 | #define OMAP3430_AUTO_GPIO3 (1 << 14) | |
| 648 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | |
| 649 | #define OMAP3430_AUTO_GPIO2 (1 << 13) | |
| 650 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | |
| 651 | #define OMAP3430_AUTO_WDT3 (1 << 12) | |
| 652 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | |
| 653 | #define OMAP3430_AUTO_UART3 (1 << 11) | |
| 654 | #define OMAP3430_AUTO_UART3_SHIFT 11 | |
| 655 | #define OMAP3430_AUTO_GPT9 (1 << 10) | |
| 656 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | |
| 657 | #define OMAP3430_AUTO_GPT8 (1 << 9) | |
| 658 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | |
| 659 | #define OMAP3430_AUTO_GPT7 (1 << 8) | |
| 660 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | |
| 661 | #define OMAP3430_AUTO_GPT6 (1 << 7) | |
| 662 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | |
| 663 | #define OMAP3430_AUTO_GPT5 (1 << 6) | |
| 664 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | |
| 665 | #define OMAP3430_AUTO_GPT4 (1 << 5) | |
| 666 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | |
| 667 | #define OMAP3430_AUTO_GPT3 (1 << 4) | |
| 668 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | |
| 669 | #define OMAP3430_AUTO_GPT2 (1 << 3) | |
| 670 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | |
| 671 | #define OMAP3430_AUTO_MCBSP4 (1 << 2) | |
| 672 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | |
| 673 | #define OMAP3430_AUTO_MCBSP3 (1 << 1) | |
| 674 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | |
| 675 | #define OMAP3430_AUTO_MCBSP2 (1 << 0) | |
| 676 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | |
| 677 | ||
| 678 | /* CM_CLKSEL_PER */ | |
| 679 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | |
| 680 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | |
| 681 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | |
| 682 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | |
| 683 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | |
| 684 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | |
| 685 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | |
| 686 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | |
| 687 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | |
| 688 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | |
| 689 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | |
| 690 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | |
| 691 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | |
| 692 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | |
| 693 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | |
| 694 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | |
| 695 | ||
| 696 | /* CM_SLEEPDEP_PER specific bits */ | |
| 697 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) | |
| 698 | ||
| 699 | /* CM_CLKSTCTRL_PER */ | |
| 700 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | |
| 701 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | |
| 702 | ||
| 703 | /* CM_CLKSTST_PER */ | |
| 801954d3 PW |
704 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 |
| 705 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | |
| c595713d TL |
706 | |
| 707 | /* CM_CLKSEL1_EMU */ | |
| 708 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | |
| 709 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | |
| 710 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | |
| 711 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | |
| 712 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | |
| 713 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | |
| 714 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | |
| 715 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | |
| 716 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | |
| 717 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | |
| 718 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | |
| 719 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | |
| 720 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | |
| 721 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | |
| 722 | #define OMAP3430_MUX_CTRL_SHIFT 0 | |
| 723 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | |
| 724 | ||
| 725 | /* CM_CLKSTCTRL_EMU */ | |
| 726 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | |
| 727 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | |
| 728 | ||
| 729 | /* CM_CLKSTST_EMU */ | |
| 801954d3 PW |
730 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 |
| 731 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | |
| c595713d TL |
732 | |
| 733 | /* CM_CLKSEL2_EMU specific bits */ | |
| 734 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | |
| 735 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
| 736 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | |
| 737 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | |
| 738 | ||
| 739 | /* CM_CLKSEL3_EMU specific bits */ | |
| 740 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | |
| 741 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
| 742 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | |
| 743 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | |
| 744 | ||
| 745 | /* CM_POLCTRL */ | |
| 746 | #define OMAP3430_CLKOUT2_POL (1 << 0) | |
| 747 | ||
| 748 | /* CM_IDLEST_NEON */ | |
| 749 | #define OMAP3430_ST_NEON (1 << 0) | |
| 750 | ||
| 751 | /* CM_CLKSTCTRL_NEON */ | |
| 752 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | |
| 753 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | |
| 754 | ||
| 755 | /* CM_FCLKEN_USBHOST */ | |
| 756 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | |
| 757 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | |
| 758 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | |
| 759 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | |
| 760 | ||
| 761 | /* CM_ICLKEN_USBHOST */ | |
| 762 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | |
| 763 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | |
| 764 | ||
| 765 | /* CM_IDLEST_USBHOST */ | |
| da0747d4 PW |
766 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
| 767 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | |
| 768 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | |
| 769 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | |
| c595713d TL |
770 | |
| 771 | /* CM_AUTOIDLE_USBHOST */ | |
| 772 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
| 773 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | |
| 774 | ||
| 775 | /* CM_SLEEPDEP_USBHOST */ | |
| 776 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | |
| 777 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | |
| 778 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | |
| 779 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | |
| 780 | ||
| 781 | /* CM_CLKSTCTRL_USBHOST */ | |
| 782 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | |
| 783 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | |
| 784 | ||
| 801954d3 PW |
785 | /* CM_CLKSTST_USBHOST */ |
| 786 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | |
| 787 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | |
| c595713d TL |
788 | |
| 789 | #endif |