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c595713d TL |
1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H |
2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H | |
3 | ||
4 | /* | |
5 | * OMAP3430 Clock Management register bits | |
6 | * | |
7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
8 | * Copyright (C) 2007-2008 Nokia Corporation | |
9 | * | |
10 | * Written by Paul Walmsley | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
c595713d TL |
17 | /* Bits shared between registers */ |
18 | ||
19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | |
20 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | |
21 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | |
2bc4ef71 | 22 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) |
c595713d | 23 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
2bc4ef71 | 24 | #define OMAP3430_EN_HDQ_MASK (1 << 22) |
c595713d | 25 | #define OMAP3430_EN_HDQ_SHIFT 22 |
2bc4ef71 | 26 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) |
c595713d | 27 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
2bc4ef71 | 28 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) |
c595713d | 29 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
2bc4ef71 | 30 | #define OMAP3430_EN_SSI_MASK (1 << 0) |
c595713d TL |
31 | #define OMAP3430_EN_SSI_SHIFT 0 |
32 | ||
33 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | |
34 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | |
35 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | |
36 | ||
37 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | |
2bc4ef71 | 38 | #define OMAP3430_EN_WDT2_MASK (1 << 5) |
c595713d TL |
39 | #define OMAP3430_EN_WDT2_SHIFT 5 |
40 | ||
41 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | |
2bc4ef71 | 42 | #define OMAP3430_EN_CAM_MASK (1 << 0) |
c595713d TL |
43 | #define OMAP3430_EN_CAM_SHIFT 0 |
44 | ||
45 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | |
2bc4ef71 | 46 | #define OMAP3430_EN_WDT3_MASK (1 << 12) |
c595713d TL |
47 | #define OMAP3430_EN_WDT3_SHIFT 12 |
48 | ||
49 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | |
2bc4ef71 | 50 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) |
c595713d TL |
51 | |
52 | ||
53 | /* Bits specific to each register */ | |
54 | ||
55 | /* CM_FCLKEN_IVA2 */ | |
dfa6d6f8 | 56 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
31c203d4 | 57 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
c595713d TL |
58 | |
59 | /* CM_CLKEN_PLL_IVA2 */ | |
60 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | |
61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | |
62 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | |
63 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | |
64 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | |
65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | |
66 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | |
67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | |
68 | ||
69 | /* CM_IDLEST_IVA2 */ | |
ed733619 | 70 | #define OMAP3430_ST_IVA2_SHIFT 0 |
2bc4ef71 | 71 | #define OMAP3430_ST_IVA2_MASK (1 << 0) |
c595713d TL |
72 | |
73 | /* CM_IDLEST_PLL_IVA2 */ | |
542313cc PW |
74 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 |
75 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | |
c595713d TL |
76 | |
77 | /* CM_AUTOIDLE_PLL_IVA2 */ | |
78 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | |
79 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | |
80 | ||
81 | /* CM_CLKSEL1_PLL_IVA2 */ | |
82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | |
4e68f5a7 | 83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) |
c595713d TL |
84 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 |
85 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | |
86 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | |
87 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | |
88 | ||
89 | /* CM_CLKSEL2_PLL_IVA2 */ | |
90 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | |
91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
92 | ||
93 | /* CM_CLKSTCTRL_IVA2 */ | |
94 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | |
95 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | |
96 | ||
97 | /* CM_CLKSTST_IVA2 */ | |
801954d3 PW |
98 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 |
99 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | |
c595713d TL |
100 | |
101 | /* CM_REVISION specific bits */ | |
102 | ||
103 | /* CM_SYSCONFIG specific bits */ | |
104 | ||
105 | /* CM_CLKEN_PLL_MPU */ | |
106 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | |
107 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | |
108 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | |
109 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | |
110 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | |
111 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | |
112 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | |
113 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | |
114 | ||
115 | /* CM_IDLEST_MPU */ | |
2bc4ef71 | 116 | #define OMAP3430_ST_MPU_MASK (1 << 0) |
c595713d TL |
117 | |
118 | /* CM_IDLEST_PLL_MPU */ | |
542313cc | 119 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
3760d31f | 120 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
c595713d TL |
121 | |
122 | /* CM_AUTOIDLE_PLL_MPU */ | |
123 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | |
124 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | |
125 | ||
126 | /* CM_CLKSEL1_PLL_MPU */ | |
127 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | |
4e68f5a7 | 128 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) |
c595713d TL |
129 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 |
130 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | |
131 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | |
132 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | |
133 | ||
134 | /* CM_CLKSEL2_PLL_MPU */ | |
135 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | |
136 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | |
137 | ||
138 | /* CM_CLKSTCTRL_MPU */ | |
139 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | |
140 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | |
141 | ||
142 | /* CM_CLKSTST_MPU */ | |
801954d3 PW |
143 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 |
144 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | |
c595713d TL |
145 | |
146 | /* CM_FCLKEN1_CORE specific bits */ | |
2bc4ef71 | 147 | #define OMAP3430_EN_MODEM_MASK (1 << 31) |
8111b221 | 148 | #define OMAP3430_EN_MODEM_SHIFT 31 |
c595713d TL |
149 | |
150 | /* CM_ICLKEN1_CORE specific bits */ | |
2bc4ef71 | 151 | #define OMAP3430_EN_ICR_MASK (1 << 29) |
c595713d | 152 | #define OMAP3430_EN_ICR_SHIFT 29 |
2bc4ef71 | 153 | #define OMAP3430_EN_AES2_MASK (1 << 28) |
c595713d | 154 | #define OMAP3430_EN_AES2_SHIFT 28 |
2bc4ef71 | 155 | #define OMAP3430_EN_SHA12_MASK (1 << 27) |
c595713d | 156 | #define OMAP3430_EN_SHA12_SHIFT 27 |
2bc4ef71 | 157 | #define OMAP3430_EN_DES2_MASK (1 << 26) |
c595713d | 158 | #define OMAP3430_EN_DES2_SHIFT 26 |
2bc4ef71 | 159 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) |
c595713d | 160 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
2bc4ef71 | 161 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) |
c595713d | 162 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
2bc4ef71 | 163 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) |
c595713d | 164 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
2bc4ef71 | 165 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) |
8111b221 | 166 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
2bc4ef71 | 167 | #define OMAP3430_EN_SDRC_MASK (1 << 1) |
c595713d TL |
168 | #define OMAP3430_EN_SDRC_SHIFT 1 |
169 | ||
3cc4a2fc RL |
170 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
171 | #define AM35XX_EN_IPSS_MASK (1 << 4) | |
172 | #define AM35XX_EN_IPSS_SHIFT 4 | |
3cc4a2fc | 173 | |
c595713d | 174 | /* CM_ICLKEN2_CORE */ |
2bc4ef71 | 175 | #define OMAP3430_EN_PKA_MASK (1 << 4) |
c595713d | 176 | #define OMAP3430_EN_PKA_SHIFT 4 |
2bc4ef71 | 177 | #define OMAP3430_EN_AES1_MASK (1 << 3) |
c595713d | 178 | #define OMAP3430_EN_AES1_SHIFT 3 |
2bc4ef71 | 179 | #define OMAP3430_EN_RNG_MASK (1 << 2) |
c595713d | 180 | #define OMAP3430_EN_RNG_SHIFT 2 |
2bc4ef71 | 181 | #define OMAP3430_EN_SHA11_MASK (1 << 1) |
c595713d | 182 | #define OMAP3430_EN_SHA11_SHIFT 1 |
2bc4ef71 | 183 | #define OMAP3430_EN_DES1_MASK (1 << 0) |
c595713d TL |
184 | #define OMAP3430_EN_DES1_SHIFT 0 |
185 | ||
8111b221 KH |
186 | /* CM_ICLKEN3_CORE */ |
187 | #define OMAP3430_EN_MAD2D_SHIFT 3 | |
2bc4ef71 | 188 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) |
8111b221 | 189 | |
c595713d TL |
190 | /* CM_FCLKEN3_CORE specific bits */ |
191 | #define OMAP3430ES2_EN_TS_SHIFT 1 | |
192 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | |
193 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | |
194 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | |
195 | ||
196 | /* CM_IDLEST1_CORE specific bits */ | |
da0747d4 PW |
197 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
198 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | |
199 | #define OMAP3430_ST_ICR_SHIFT 29 | |
200 | #define OMAP3430_ST_ICR_MASK (1 << 29) | |
201 | #define OMAP3430_ST_AES2_SHIFT 28 | |
202 | #define OMAP3430_ST_AES2_MASK (1 << 28) | |
203 | #define OMAP3430_ST_SHA12_SHIFT 27 | |
204 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | |
205 | #define OMAP3430_ST_DES2_SHIFT 26 | |
206 | #define OMAP3430_ST_DES2_MASK (1 << 26) | |
207 | #define OMAP3430_ST_MSPRO_SHIFT 23 | |
208 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | |
bf765237 PW |
209 | #define AM35XX_ST_UART4_SHIFT 23 |
210 | #define AM35XX_ST_UART4_MASK (1 << 23) | |
da0747d4 PW |
211 | #define OMAP3430_ST_HDQ_SHIFT 22 |
212 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | |
213 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | |
214 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | |
215 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | |
216 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | |
217 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | |
218 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | |
219 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | |
220 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | |
8f993a01 TK |
221 | #define OMAP3430_ST_SAD2D_SHIFT 3 |
222 | #define OMAP3430_ST_SAD2D_MASK (1 << 3) | |
da0747d4 PW |
223 | #define OMAP3430_ST_SDMA_SHIFT 2 |
224 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | |
225 | #define OMAP3430_ST_SDRC_SHIFT 1 | |
226 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | |
227 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | |
228 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | |
c595713d | 229 | |
3cc4a2fc RL |
230 | /* AM35xx specific CM_IDLEST1_CORE bits */ |
231 | #define AM35XX_ST_IPSS_SHIFT 5 | |
232 | #define AM35XX_ST_IPSS_MASK (1 << 5) | |
233 | ||
c595713d | 234 | /* CM_IDLEST2_CORE */ |
da0747d4 PW |
235 | #define OMAP3430_ST_PKA_SHIFT 4 |
236 | #define OMAP3430_ST_PKA_MASK (1 << 4) | |
237 | #define OMAP3430_ST_AES1_SHIFT 3 | |
238 | #define OMAP3430_ST_AES1_MASK (1 << 3) | |
239 | #define OMAP3430_ST_RNG_SHIFT 2 | |
240 | #define OMAP3430_ST_RNG_MASK (1 << 2) | |
241 | #define OMAP3430_ST_SHA11_SHIFT 1 | |
242 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | |
243 | #define OMAP3430_ST_DES1_SHIFT 0 | |
244 | #define OMAP3430_ST_DES1_MASK (1 << 0) | |
c595713d TL |
245 | |
246 | /* CM_IDLEST3_CORE */ | |
247 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | |
248 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | |
da0747d4 PW |
249 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 |
250 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | |
c595713d TL |
251 | |
252 | /* CM_AUTOIDLE1_CORE */ | |
2bc4ef71 | 253 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) |
8111b221 | 254 | #define OMAP3430_AUTO_MODEM_SHIFT 31 |
2bc4ef71 | 255 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) |
027d8ded | 256 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 |
2bc4ef71 | 257 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) |
027d8ded | 258 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 |
2bc4ef71 | 259 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) |
c595713d | 260 | #define OMAP3430_AUTO_AES2_SHIFT 28 |
2bc4ef71 | 261 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) |
c595713d | 262 | #define OMAP3430_AUTO_SHA12_SHIFT 27 |
2bc4ef71 | 263 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) |
c595713d | 264 | #define OMAP3430_AUTO_DES2_SHIFT 26 |
2bc4ef71 | 265 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) |
c595713d | 266 | #define OMAP3430_AUTO_MMC2_SHIFT 25 |
2bc4ef71 | 267 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) |
c595713d | 268 | #define OMAP3430_AUTO_MMC1_SHIFT 24 |
2bc4ef71 | 269 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) |
c595713d | 270 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 |
2bc4ef71 | 271 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) |
c595713d | 272 | #define OMAP3430_AUTO_HDQ_SHIFT 22 |
2bc4ef71 | 273 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) |
c595713d | 274 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 |
2bc4ef71 | 275 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) |
c595713d | 276 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 |
2bc4ef71 | 277 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) |
c595713d | 278 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 |
2bc4ef71 | 279 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) |
c595713d | 280 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 |
2bc4ef71 | 281 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) |
c595713d | 282 | #define OMAP3430_AUTO_I2C3_SHIFT 17 |
2bc4ef71 | 283 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) |
c595713d | 284 | #define OMAP3430_AUTO_I2C2_SHIFT 16 |
2bc4ef71 | 285 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) |
c595713d | 286 | #define OMAP3430_AUTO_I2C1_SHIFT 15 |
2bc4ef71 | 287 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) |
c595713d | 288 | #define OMAP3430_AUTO_UART2_SHIFT 14 |
2bc4ef71 | 289 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) |
c595713d | 290 | #define OMAP3430_AUTO_UART1_SHIFT 13 |
2bc4ef71 | 291 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) |
c595713d | 292 | #define OMAP3430_AUTO_GPT11_SHIFT 12 |
2bc4ef71 | 293 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) |
c595713d | 294 | #define OMAP3430_AUTO_GPT10_SHIFT 11 |
2bc4ef71 | 295 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) |
c595713d | 296 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 |
2bc4ef71 | 297 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) |
c595713d | 298 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 |
2bc4ef71 | 299 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) |
c595713d | 300 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 |
2bc4ef71 | 301 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) |
c595713d | 302 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 |
2bc4ef71 | 303 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) |
c595713d | 304 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 |
2bc4ef71 | 305 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) |
c595713d | 306 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 |
2bc4ef71 | 307 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) |
c595713d | 308 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 |
2bc4ef71 | 309 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) |
c595713d | 310 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 |
2bc4ef71 | 311 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) |
8111b221 | 312 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 |
2bc4ef71 | 313 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) |
c595713d TL |
314 | #define OMAP3430_AUTO_SSI_SHIFT 0 |
315 | ||
316 | /* CM_AUTOIDLE2_CORE */ | |
2bc4ef71 | 317 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) |
c595713d | 318 | #define OMAP3430_AUTO_PKA_SHIFT 4 |
2bc4ef71 | 319 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) |
c595713d | 320 | #define OMAP3430_AUTO_AES1_SHIFT 3 |
2bc4ef71 | 321 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) |
c595713d | 322 | #define OMAP3430_AUTO_RNG_SHIFT 2 |
2bc4ef71 | 323 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) |
c595713d | 324 | #define OMAP3430_AUTO_SHA11_SHIFT 1 |
2bc4ef71 | 325 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) |
c595713d TL |
326 | #define OMAP3430_AUTO_DES1_SHIFT 0 |
327 | ||
328 | /* CM_AUTOIDLE3_CORE */ | |
027d8ded JH |
329 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) |
330 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
331 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | |
c595713d TL |
332 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
333 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | |
8111b221 | 334 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 |
2bc4ef71 | 335 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) |
c595713d TL |
336 | |
337 | /* CM_CLKSEL_CORE */ | |
338 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | |
339 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | |
340 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | |
341 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | |
342 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | |
343 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | |
344 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | |
345 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | |
346 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | |
347 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | |
348 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | |
349 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | |
7356f0b2 VB |
350 | #define OMAP3630_CLKSEL_96M_SHIFT 12 |
351 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | |
c595713d TL |
352 | |
353 | /* CM_CLKSTCTRL_CORE */ | |
354 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | |
355 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | |
356 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | |
357 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | |
358 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | |
359 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | |
360 | ||
361 | /* CM_CLKSTST_CORE */ | |
801954d3 PW |
362 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 |
363 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | |
364 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | |
365 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | |
366 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | |
367 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | |
c595713d TL |
368 | |
369 | /* CM_FCLKEN_GFX */ | |
2bc4ef71 | 370 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) |
c595713d | 371 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
2bc4ef71 | 372 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) |
c595713d TL |
373 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
374 | ||
375 | /* CM_ICLKEN_GFX specific bits */ | |
376 | ||
377 | /* CM_IDLEST_GFX specific bits */ | |
378 | ||
379 | /* CM_CLKSEL_GFX specific bits */ | |
380 | ||
381 | /* CM_SLEEPDEP_GFX specific bits */ | |
382 | ||
383 | /* CM_CLKSTCTRL_GFX */ | |
384 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | |
385 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | |
386 | ||
387 | /* CM_CLKSTST_GFX */ | |
801954d3 PW |
388 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 |
389 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | |
c595713d TL |
390 | |
391 | /* CM_FCLKEN_SGX */ | |
712d7c86 DS |
392 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
393 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | |
394 | ||
b024b542 TK |
395 | /* CM_IDLEST_SGX */ |
396 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | |
397 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | |
398 | ||
712d7c86 DS |
399 | /* CM_ICLKEN_SGX */ |
400 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | |
401 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | |
c595713d TL |
402 | |
403 | /* CM_CLKSEL_SGX */ | |
404 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | |
405 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | |
406 | ||
801954d3 PW |
407 | /* CM_CLKSTCTRL_SGX */ |
408 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | |
409 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | |
410 | ||
411 | /* CM_CLKSTST_SGX */ | |
412 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | |
413 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | |
414 | ||
c595713d TL |
415 | /* CM_FCLKEN_WKUP specific bits */ |
416 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | |
da0747d4 | 417 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) |
c595713d TL |
418 | |
419 | /* CM_ICLKEN_WKUP specific bits */ | |
2bc4ef71 | 420 | #define OMAP3430_EN_WDT1_MASK (1 << 4) |
c595713d | 421 | #define OMAP3430_EN_WDT1_SHIFT 4 |
2bc4ef71 | 422 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) |
c595713d TL |
423 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
424 | ||
425 | /* CM_IDLEST_WKUP specific bits */ | |
da0747d4 PW |
426 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
427 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | |
428 | #define OMAP3430_ST_WDT2_SHIFT 5 | |
429 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | |
430 | #define OMAP3430_ST_WDT1_SHIFT 4 | |
431 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | |
432 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | |
433 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | |
c595713d TL |
434 | |
435 | /* CM_AUTOIDLE_WKUP */ | |
2bc4ef71 | 436 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) |
da0747d4 | 437 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 |
2bc4ef71 | 438 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) |
c595713d | 439 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
2bc4ef71 | 440 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) |
c595713d | 441 | #define OMAP3430_AUTO_WDT1_SHIFT 4 |
2bc4ef71 | 442 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) |
c595713d | 443 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 |
2bc4ef71 | 444 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) |
c595713d | 445 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 |
2bc4ef71 | 446 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) |
c595713d | 447 | #define OMAP3430_AUTO_GPT12_SHIFT 1 |
2bc4ef71 | 448 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) |
c595713d TL |
449 | #define OMAP3430_AUTO_GPT1_SHIFT 0 |
450 | ||
451 | /* CM_CLKSEL_WKUP */ | |
452 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | |
453 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | |
454 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | |
455 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | |
456 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | |
457 | ||
458 | /* CM_CLKEN_PLL */ | |
459 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | |
460 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | |
461 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | |
462 | #define OMAP3430_PWRDN_TV_SHIFT 28 | |
463 | #define OMAP3430_PWRDN_96M_SHIFT 27 | |
464 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | |
465 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | |
466 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | |
467 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | |
468 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | |
469 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | |
470 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | |
471 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | |
472 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | |
473 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | |
474 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | |
475 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | |
476 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | |
477 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | |
478 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | |
479 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | |
480 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | |
481 | ||
482 | /* CM_CLKEN2_PLL */ | |
2bc4ef71 | 483 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 |
c595713d TL |
484 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) |
485 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | |
486 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | |
487 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | |
488 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | |
489 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | |
490 | ||
491 | /* CM_IDLEST_CKGEN */ | |
2bc4ef71 PW |
492 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) |
493 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) | |
494 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) | |
495 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) | |
542313cc PW |
496 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 |
497 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | |
498 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | |
499 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | |
c595713d TL |
500 | |
501 | /* CM_IDLEST2_CKGEN */ | |
da0747d4 PW |
502 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 |
503 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | |
c595713d TL |
504 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
505 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | |
506 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | |
507 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | |
508 | ||
509 | /* CM_AUTOIDLE_PLL */ | |
510 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | |
511 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | |
512 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | |
513 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | |
514 | ||
542313cc PW |
515 | /* CM_AUTOIDLE2_PLL */ |
516 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | |
517 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | |
518 | ||
c595713d TL |
519 | /* CM_CLKSEL1_PLL */ |
520 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | |
521 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | |
522 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | |
523 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | |
524 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | |
525 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | |
526 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | |
9cfd985e PW |
527 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
528 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | |
529 | #define OMAP3430_SOURCE_54M_SHIFT 5 | |
530 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | |
531 | #define OMAP3430_SOURCE_48M_SHIFT 3 | |
532 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | |
c595713d TL |
533 | |
534 | /* CM_CLKSEL2_PLL */ | |
535 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | |
536 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | |
358965d7 | 537 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) |
c595713d TL |
538 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 |
539 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | |
358965d7 RW |
540 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 |
541 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | |
542 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | |
543 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | |
c595713d TL |
544 | |
545 | /* CM_CLKSEL3_PLL */ | |
546 | #define OMAP3430_DIV_96M_SHIFT 0 | |
547 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | |
678bc9a2 | 548 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) |
c595713d TL |
549 | |
550 | /* CM_CLKSEL4_PLL */ | |
551 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | |
552 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | |
553 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | |
554 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | |
555 | ||
556 | /* CM_CLKSEL5_PLL */ | |
557 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | |
558 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | |
559 | ||
560 | /* CM_CLKOUT_CTRL */ | |
561 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | |
2bc4ef71 | 562 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) |
c595713d TL |
563 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
564 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | |
565 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | |
566 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | |
567 | ||
568 | /* CM_FCLKEN_DSS */ | |
2bc4ef71 | 569 | #define OMAP3430_EN_TV_MASK (1 << 2) |
c595713d | 570 | #define OMAP3430_EN_TV_SHIFT 2 |
2bc4ef71 | 571 | #define OMAP3430_EN_DSS2_MASK (1 << 1) |
c595713d | 572 | #define OMAP3430_EN_DSS2_SHIFT 1 |
2bc4ef71 | 573 | #define OMAP3430_EN_DSS1_MASK (1 << 0) |
c595713d TL |
574 | #define OMAP3430_EN_DSS1_SHIFT 0 |
575 | ||
576 | /* CM_ICLKEN_DSS */ | |
2bc4ef71 | 577 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) |
c595713d TL |
578 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
579 | ||
580 | /* CM_IDLEST_DSS */ | |
da0747d4 PW |
581 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
582 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | |
583 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | |
584 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | |
585 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | |
586 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | |
c595713d TL |
587 | |
588 | /* CM_AUTOIDLE_DSS */ | |
2bc4ef71 | 589 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) |
c595713d TL |
590 | #define OMAP3430_AUTO_DSS_SHIFT 0 |
591 | ||
592 | /* CM_CLKSEL_DSS */ | |
593 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | |
594 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | |
678bc9a2 | 595 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) |
c595713d TL |
596 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
597 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | |
678bc9a2 | 598 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) |
c595713d TL |
599 | |
600 | /* CM_SLEEPDEP_DSS specific bits */ | |
601 | ||
602 | /* CM_CLKSTCTRL_DSS */ | |
603 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | |
604 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | |
605 | ||
606 | /* CM_CLKSTST_DSS */ | |
801954d3 PW |
607 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 |
608 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | |
c595713d TL |
609 | |
610 | /* CM_FCLKEN_CAM specific bits */ | |
2bc4ef71 | 611 | #define OMAP3430_EN_CSI2_MASK (1 << 1) |
6c8fe0b9 | 612 | #define OMAP3430_EN_CSI2_SHIFT 1 |
c595713d TL |
613 | |
614 | /* CM_ICLKEN_CAM specific bits */ | |
615 | ||
616 | /* CM_IDLEST_CAM */ | |
2bc4ef71 | 617 | #define OMAP3430_ST_CAM_MASK (1 << 0) |
c595713d TL |
618 | |
619 | /* CM_AUTOIDLE_CAM */ | |
2bc4ef71 | 620 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) |
c595713d TL |
621 | #define OMAP3430_AUTO_CAM_SHIFT 0 |
622 | ||
623 | /* CM_CLKSEL_CAM */ | |
624 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | |
625 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | |
678bc9a2 | 626 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) |
c595713d TL |
627 | |
628 | /* CM_SLEEPDEP_CAM specific bits */ | |
629 | ||
630 | /* CM_CLKSTCTRL_CAM */ | |
631 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | |
632 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | |
633 | ||
634 | /* CM_CLKSTST_CAM */ | |
801954d3 PW |
635 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 |
636 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | |
c595713d TL |
637 | |
638 | /* CM_FCLKEN_PER specific bits */ | |
639 | ||
640 | /* CM_ICLKEN_PER specific bits */ | |
641 | ||
642 | /* CM_IDLEST_PER */ | |
da0747d4 PW |
643 | #define OMAP3430_ST_WDT3_SHIFT 12 |
644 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | |
645 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | |
646 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | |
647 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | |
648 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | |
649 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | |
650 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | |
c595713d TL |
651 | |
652 | /* CM_AUTOIDLE_PER */ | |
e5863689 G |
653 | #define OMAP3630_AUTO_UART4_MASK (1 << 18) |
654 | #define OMAP3630_AUTO_UART4_SHIFT 18 | |
2bc4ef71 | 655 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) |
c595713d | 656 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 |
2bc4ef71 | 657 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) |
c595713d | 658 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 |
2bc4ef71 | 659 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) |
c595713d | 660 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 |
2bc4ef71 | 661 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) |
c595713d | 662 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 |
2bc4ef71 | 663 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) |
c595713d | 664 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 |
2bc4ef71 | 665 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) |
c595713d | 666 | #define OMAP3430_AUTO_WDT3_SHIFT 12 |
2bc4ef71 | 667 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) |
c595713d | 668 | #define OMAP3430_AUTO_UART3_SHIFT 11 |
2bc4ef71 | 669 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) |
c595713d | 670 | #define OMAP3430_AUTO_GPT9_SHIFT 10 |
2bc4ef71 | 671 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) |
c595713d | 672 | #define OMAP3430_AUTO_GPT8_SHIFT 9 |
2bc4ef71 | 673 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) |
c595713d | 674 | #define OMAP3430_AUTO_GPT7_SHIFT 8 |
2bc4ef71 | 675 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) |
c595713d | 676 | #define OMAP3430_AUTO_GPT6_SHIFT 7 |
2bc4ef71 | 677 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) |
c595713d | 678 | #define OMAP3430_AUTO_GPT5_SHIFT 6 |
2bc4ef71 | 679 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) |
c595713d | 680 | #define OMAP3430_AUTO_GPT4_SHIFT 5 |
2bc4ef71 | 681 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) |
c595713d | 682 | #define OMAP3430_AUTO_GPT3_SHIFT 4 |
2bc4ef71 | 683 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) |
c595713d | 684 | #define OMAP3430_AUTO_GPT2_SHIFT 3 |
2bc4ef71 | 685 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) |
c595713d | 686 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 |
2bc4ef71 | 687 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) |
c595713d | 688 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 |
2bc4ef71 | 689 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) |
c595713d TL |
690 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 |
691 | ||
692 | /* CM_CLKSEL_PER */ | |
693 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | |
694 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | |
695 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | |
696 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | |
697 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | |
698 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | |
699 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | |
700 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | |
701 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | |
702 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | |
703 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | |
704 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | |
705 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | |
706 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | |
707 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | |
708 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | |
709 | ||
710 | /* CM_SLEEPDEP_PER specific bits */ | |
2bc4ef71 | 711 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) |
c595713d TL |
712 | |
713 | /* CM_CLKSTCTRL_PER */ | |
714 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | |
715 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | |
716 | ||
717 | /* CM_CLKSTST_PER */ | |
801954d3 PW |
718 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 |
719 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | |
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720 | |
721 | /* CM_CLKSEL1_EMU */ | |
722 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | |
723 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | |
678bc9a2 | 724 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) |
c595713d TL |
725 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
726 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | |
727 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | |
728 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | |
729 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | |
730 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | |
731 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | |
732 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | |
733 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | |
734 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | |
735 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | |
736 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | |
737 | #define OMAP3430_MUX_CTRL_SHIFT 0 | |
738 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | |
739 | ||
740 | /* CM_CLKSTCTRL_EMU */ | |
741 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | |
742 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | |
743 | ||
744 | /* CM_CLKSTST_EMU */ | |
801954d3 PW |
745 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 |
746 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | |
c595713d TL |
747 | |
748 | /* CM_CLKSEL2_EMU specific bits */ | |
749 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | |
750 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
751 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | |
752 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | |
753 | ||
754 | /* CM_CLKSEL3_EMU specific bits */ | |
755 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | |
756 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | |
757 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | |
758 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | |
759 | ||
760 | /* CM_POLCTRL */ | |
2bc4ef71 | 761 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) |
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762 | |
763 | /* CM_IDLEST_NEON */ | |
2bc4ef71 | 764 | #define OMAP3430_ST_NEON_MASK (1 << 0) |
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765 | |
766 | /* CM_CLKSTCTRL_NEON */ | |
767 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | |
768 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | |
769 | ||
770 | /* CM_FCLKEN_USBHOST */ | |
771 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | |
772 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | |
773 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | |
774 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | |
775 | ||
776 | /* CM_ICLKEN_USBHOST */ | |
777 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | |
778 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | |
779 | ||
780 | /* CM_IDLEST_USBHOST */ | |
da0747d4 PW |
781 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
782 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | |
783 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | |
784 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | |
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785 | |
786 | /* CM_AUTOIDLE_USBHOST */ | |
787 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | |
788 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | |
789 | ||
790 | /* CM_SLEEPDEP_USBHOST */ | |
791 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | |
792 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | |
793 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | |
794 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | |
795 | ||
796 | /* CM_CLKSTCTRL_USBHOST */ | |
797 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | |
798 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | |
799 | ||
801954d3 PW |
800 | /* CM_CLKSTST_USBHOST */ |
801 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | |
802 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | |
c595713d | 803 | |
bd2122ca PW |
804 | /* |
805 | * | |
806 | */ | |
807 | ||
808 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | |
809 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | |
810 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | |
811 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | |
812 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | |
813 | ||
814 | ||
c595713d | 815 | #endif |