Commit | Line | Data |
---|---|---|
dd708413 RN |
1 | /* |
2 | * OMAP44xx Clock Management register bits | |
3 | * | |
f19a3022 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
568997cf | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
dd708413 RN |
6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | |
23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | |
24 | ||
7b342a8d | 25 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
56ef28ac | 26 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 |
f19a3022 | 27 | #define OMAP4430_ABE_DYNDEP_WIDTH 0x1 |
568997cf | 28 | #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) |
dd708413 RN |
29 | |
30 | /* | |
7b342a8d BC |
31 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
32 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | |
dd708413 | 33 | */ |
56ef28ac | 34 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
f19a3022 | 35 | #define OMAP4430_ABE_STATDEP_WIDTH 0x1 |
568997cf | 36 | #define OMAP4430_ABE_STATDEP_MASK (1 << 3) |
dd708413 | 37 | |
7b342a8d | 38 | /* Used by CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 39 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 |
f19a3022 | 40 | #define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 |
568997cf | 41 | #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) |
dd708413 RN |
42 | |
43 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | |
56ef28ac | 44 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 |
f19a3022 | 45 | #define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 |
568997cf | 46 | #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) |
dd708413 RN |
47 | |
48 | /* | |
568997cf | 49 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, |
7b342a8d BC |
50 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, |
51 | * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB | |
dd708413 | 52 | */ |
56ef28ac | 53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 |
f19a3022 | 54 | #define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 |
568997cf | 55 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
dd708413 | 56 | |
7b342a8d | 57 | /* Used by CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 58 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 |
f19a3022 | 59 | #define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 |
568997cf | 60 | #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) |
dd708413 RN |
61 | |
62 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | |
56ef28ac | 63 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 |
f19a3022 | 64 | #define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 |
568997cf | 65 | #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) |
dd708413 RN |
66 | |
67 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 68 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 |
f19a3022 | 69 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 |
568997cf | 70 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) |
dd708413 RN |
71 | |
72 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 73 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 |
f19a3022 | 74 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 |
568997cf | 75 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) |
dd708413 RN |
76 | |
77 | /* Used by CM_WKUP_CLKSTCTRL */ | |
56ef28ac | 78 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 |
f19a3022 | 79 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 |
568997cf | 80 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) |
dd708413 RN |
81 | |
82 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 83 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 |
f19a3022 | 84 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 |
568997cf | 85 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) |
dd708413 RN |
86 | |
87 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 88 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 |
f19a3022 | 89 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 |
568997cf | 90 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) |
dd708413 | 91 | |
7b342a8d | 92 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 93 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 |
f19a3022 | 94 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 |
568997cf | 95 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) |
dd708413 | 96 | |
7b342a8d | 97 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 98 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 |
f19a3022 | 99 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 |
568997cf | 100 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) |
dd708413 | 101 | |
7b342a8d | 102 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 103 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 |
f19a3022 | 104 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 |
568997cf | 105 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) |
dd708413 RN |
106 | |
107 | /* Used by CM_CAM_CLKSTCTRL */ | |
56ef28ac | 108 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 |
f19a3022 | 109 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 |
568997cf RN |
110 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) |
111 | ||
112 | /* Used by CM_ALWON_CLKSTCTRL */ | |
113 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 | |
f19a3022 | 114 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 |
568997cf | 115 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) |
dd708413 RN |
116 | |
117 | /* Used by CM_EMU_CLKSTCTRL */ | |
56ef28ac | 118 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 |
f19a3022 | 119 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 |
568997cf | 120 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) |
dd708413 | 121 | |
6b54b499 RN |
122 | /* Used by CM_L4CFG_CLKSTCTRL */ |
123 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 | |
f19a3022 | 124 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 |
6b54b499 RN |
125 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) |
126 | ||
dd708413 | 127 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
56ef28ac | 128 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 |
f19a3022 | 129 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 |
568997cf | 130 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) |
dd708413 | 131 | |
7b342a8d | 132 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 133 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 |
f19a3022 | 134 | #define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 |
568997cf | 135 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) |
dd708413 | 136 | |
7b342a8d | 137 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 138 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 |
f19a3022 | 139 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 |
568997cf | 140 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) |
dd708413 | 141 | |
7b342a8d | 142 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 143 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 |
f19a3022 | 144 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 |
568997cf | 145 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) |
dd708413 | 146 | |
7b342a8d | 147 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 148 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 |
f19a3022 | 149 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 |
568997cf | 150 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) |
dd708413 | 151 | |
7b342a8d | 152 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 153 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 |
f19a3022 | 154 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 |
568997cf | 155 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) |
dd708413 | 156 | |
7b342a8d | 157 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 158 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 |
f19a3022 | 159 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 |
568997cf | 160 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) |
dd708413 | 161 | |
7b342a8d | 162 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 163 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 |
f19a3022 | 164 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 |
568997cf | 165 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) |
dd708413 RN |
166 | |
167 | /* Used by CM_DSS_CLKSTCTRL */ | |
56ef28ac | 168 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 |
f19a3022 | 169 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 |
568997cf | 170 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) |
dd708413 RN |
171 | |
172 | /* Used by CM_DSS_CLKSTCTRL */ | |
56ef28ac | 173 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 |
f19a3022 | 174 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 |
568997cf | 175 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) |
dd708413 RN |
176 | |
177 | /* Used by CM_DUCATI_CLKSTCTRL */ | |
56ef28ac | 178 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 |
f19a3022 | 179 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 |
568997cf | 180 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) |
dd708413 RN |
181 | |
182 | /* Used by CM_EMU_CLKSTCTRL */ | |
56ef28ac | 183 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 |
f19a3022 | 184 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 |
568997cf | 185 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) |
dd708413 RN |
186 | |
187 | /* Used by CM_CAM_CLKSTCTRL */ | |
56ef28ac | 188 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 |
f19a3022 | 189 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 |
568997cf | 190 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) |
dd708413 | 191 | |
7b342a8d | 192 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 193 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 |
f19a3022 | 194 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 |
568997cf | 195 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) |
dd708413 RN |
196 | |
197 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 198 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 |
f19a3022 | 199 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 |
568997cf | 200 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) |
dd708413 RN |
201 | |
202 | /* Used by CM_DSS_CLKSTCTRL */ | |
56ef28ac | 203 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 |
f19a3022 | 204 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 |
568997cf | 205 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) |
dd708413 | 206 | |
7b342a8d | 207 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 208 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 |
f19a3022 | 209 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 |
568997cf | 210 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) |
dd708413 | 211 | |
7b342a8d | 212 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 213 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 |
f19a3022 | 214 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 |
568997cf | 215 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) |
dd708413 | 216 | |
7b342a8d | 217 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 218 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 |
f19a3022 | 219 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 |
568997cf | 220 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) |
dd708413 | 221 | |
7b342a8d | 222 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 223 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 |
f19a3022 | 224 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 |
568997cf | 225 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) |
dd708413 | 226 | |
7b342a8d | 227 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 228 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 |
f19a3022 | 229 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 |
568997cf | 230 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) |
dd708413 | 231 | |
7b342a8d | 232 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 233 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 |
f19a3022 | 234 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 |
568997cf | 235 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) |
dd708413 | 236 | |
7b342a8d | 237 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 238 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 |
f19a3022 | 239 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 |
568997cf | 240 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) |
dd708413 | 241 | |
7b342a8d | 242 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 243 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 |
f19a3022 | 244 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 |
568997cf | 245 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) |
dd708413 | 246 | |
7b342a8d | 247 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 248 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 |
f19a3022 | 249 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 |
568997cf | 250 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) |
dd708413 | 251 | |
7b342a8d | 252 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 253 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 |
f19a3022 | 254 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 |
568997cf | 255 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) |
dd708413 | 256 | |
7b342a8d | 257 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 258 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 |
f19a3022 | 259 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 |
568997cf | 260 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) |
dd708413 | 261 | |
7b342a8d | 262 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 263 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 |
f19a3022 | 264 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 |
568997cf | 265 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) |
dd708413 | 266 | |
7b342a8d | 267 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 268 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 |
f19a3022 | 269 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 |
568997cf | 270 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) |
dd708413 RN |
271 | |
272 | /* Used by CM_CAM_CLKSTCTRL */ | |
56ef28ac | 273 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 |
f19a3022 | 274 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 |
568997cf | 275 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) |
dd708413 RN |
276 | |
277 | /* Used by CM_IVAHD_CLKSTCTRL */ | |
56ef28ac | 278 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 |
f19a3022 | 279 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 |
568997cf | 280 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) |
dd708413 | 281 | |
568997cf RN |
282 | /* Used by CM_D2D_CLKSTCTRL */ |
283 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 | |
f19a3022 | 284 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 |
568997cf | 285 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) |
dd708413 | 286 | |
7b342a8d | 287 | /* Used by CM_L3_1_CLKSTCTRL */ |
56ef28ac | 288 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 |
f19a3022 | 289 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 |
568997cf | 290 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) |
dd708413 | 291 | |
7b342a8d | 292 | /* Used by CM_L3_2_CLKSTCTRL */ |
56ef28ac | 293 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 |
f19a3022 | 294 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 |
568997cf | 295 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) |
dd708413 RN |
296 | |
297 | /* Used by CM_D2D_CLKSTCTRL */ | |
56ef28ac | 298 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 |
f19a3022 | 299 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 |
568997cf | 300 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) |
dd708413 RN |
301 | |
302 | /* Used by CM_SDMA_CLKSTCTRL */ | |
56ef28ac | 303 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 |
f19a3022 | 304 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 |
568997cf | 305 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) |
dd708413 RN |
306 | |
307 | /* Used by CM_DSS_CLKSTCTRL */ | |
56ef28ac | 308 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 |
f19a3022 | 309 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 |
568997cf | 310 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) |
dd708413 | 311 | |
7b342a8d | 312 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 313 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 |
f19a3022 | 314 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 |
568997cf | 315 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) |
dd708413 RN |
316 | |
317 | /* Used by CM_GFX_CLKSTCTRL */ | |
56ef28ac | 318 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 |
f19a3022 | 319 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 |
568997cf | 320 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) |
dd708413 | 321 | |
7b342a8d | 322 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 323 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 |
f19a3022 | 324 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 |
568997cf | 325 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) |
dd708413 RN |
326 | |
327 | /* Used by CM_L3INSTR_CLKSTCTRL */ | |
56ef28ac | 328 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 |
f19a3022 | 329 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 |
568997cf | 330 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) |
dd708413 RN |
331 | |
332 | /* Used by CM_L4SEC_CLKSTCTRL */ | |
56ef28ac | 333 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 |
f19a3022 | 334 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 |
568997cf | 335 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) |
dd708413 RN |
336 | |
337 | /* Used by CM_ALWON_CLKSTCTRL */ | |
56ef28ac | 338 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 |
f19a3022 | 339 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 |
568997cf | 340 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) |
dd708413 RN |
341 | |
342 | /* Used by CM_CEFUSE_CLKSTCTRL */ | |
56ef28ac | 343 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 |
f19a3022 | 344 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 |
568997cf | 345 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) |
dd708413 | 346 | |
7b342a8d | 347 | /* Used by CM_L4CFG_CLKSTCTRL */ |
56ef28ac | 348 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 |
f19a3022 | 349 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 |
568997cf | 350 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) |
dd708413 RN |
351 | |
352 | /* Used by CM_D2D_CLKSTCTRL */ | |
56ef28ac | 353 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 |
f19a3022 | 354 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 |
568997cf | 355 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) |
dd708413 | 356 | |
7b342a8d | 357 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 358 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 |
f19a3022 | 359 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 |
568997cf | 360 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) |
dd708413 | 361 | |
7b342a8d | 362 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 363 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 |
f19a3022 | 364 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 |
568997cf | 365 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) |
dd708413 RN |
366 | |
367 | /* Used by CM_L4SEC_CLKSTCTRL */ | |
56ef28ac | 368 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 |
f19a3022 | 369 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 |
568997cf | 370 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) |
dd708413 RN |
371 | |
372 | /* Used by CM_WKUP_CLKSTCTRL */ | |
56ef28ac | 373 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 |
f19a3022 | 374 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 |
568997cf | 375 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) |
dd708413 | 376 | |
7b342a8d | 377 | /* Used by CM_MPU_CLKSTCTRL */ |
56ef28ac | 378 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 |
f19a3022 | 379 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 |
568997cf | 380 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) |
dd708413 RN |
381 | |
382 | /* Used by CM1_ABE_CLKSTCTRL */ | |
56ef28ac | 383 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 |
f19a3022 | 384 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 |
568997cf | 385 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) |
dd708413 | 386 | |
7b342a8d | 387 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 388 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 |
f19a3022 | 389 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 |
568997cf | 390 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) |
dd708413 | 391 | |
7b342a8d | 392 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 393 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 |
f19a3022 | 394 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 |
568997cf | 395 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) |
dd708413 | 396 | |
7b342a8d | 397 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 398 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 |
f19a3022 | 399 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 |
568997cf | 400 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) |
dd708413 | 401 | |
7b342a8d | 402 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 403 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 |
f19a3022 | 404 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 |
568997cf | 405 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) |
dd708413 | 406 | |
7b342a8d | 407 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 408 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 |
f19a3022 | 409 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 |
568997cf | 410 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) |
dd708413 | 411 | |
7b342a8d | 412 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 413 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 |
f19a3022 | 414 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 |
568997cf | 415 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) |
dd708413 | 416 | |
7b342a8d | 417 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 418 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 |
568997cf | 419 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) |
dd708413 | 420 | |
7b342a8d | 421 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 422 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 |
f19a3022 | 423 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 |
568997cf | 424 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) |
dd708413 | 425 | |
7b342a8d | 426 | /* Used by CM_L4PER_CLKSTCTRL */ |
56ef28ac | 427 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 |
f19a3022 | 428 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 |
568997cf | 429 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) |
dd708413 | 430 | |
7b342a8d | 431 | /* Used by CM_MEMIF_CLKSTCTRL */ |
56ef28ac | 432 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 |
f19a3022 | 433 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 |
568997cf | 434 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) |
dd708413 RN |
435 | |
436 | /* Used by CM_GFX_CLKSTCTRL */ | |
56ef28ac | 437 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 |
f19a3022 | 438 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 |
568997cf | 439 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) |
dd708413 RN |
440 | |
441 | /* Used by CM_ALWON_CLKSTCTRL */ | |
56ef28ac | 442 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 |
f19a3022 | 443 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 |
568997cf | 444 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) |
dd708413 RN |
445 | |
446 | /* Used by CM_ALWON_CLKSTCTRL */ | |
56ef28ac | 447 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 |
f19a3022 | 448 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 |
568997cf | 449 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) |
dd708413 RN |
450 | |
451 | /* Used by CM_ALWON_CLKSTCTRL */ | |
56ef28ac | 452 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 |
f19a3022 | 453 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 |
568997cf | 454 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) |
dd708413 RN |
455 | |
456 | /* Used by CM_WKUP_CLKSTCTRL */ | |
56ef28ac | 457 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 |
f19a3022 | 458 | #define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 |
568997cf | 459 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) |
dd708413 RN |
460 | |
461 | /* Used by CM_TESLA_CLKSTCTRL */ | |
56ef28ac | 462 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 |
f19a3022 | 463 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 |
568997cf | 464 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) |
dd708413 | 465 | |
7b342a8d | 466 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 467 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 |
f19a3022 | 468 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 |
568997cf | 469 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) |
dd708413 | 470 | |
7b342a8d | 471 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 472 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 |
f19a3022 | 473 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 |
568997cf | 474 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) |
dd708413 | 475 | |
7b342a8d | 476 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 477 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 |
f19a3022 | 478 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 |
568997cf RN |
479 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) |
480 | ||
7b342a8d | 481 | /* Used by CM_L3INIT_CLKSTCTRL */ |
568997cf | 482 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 |
f19a3022 | 483 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 |
568997cf RN |
484 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) |
485 | ||
7b342a8d | 486 | /* Used by CM_L3INIT_CLKSTCTRL */ |
568997cf | 487 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 |
f19a3022 | 488 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 |
568997cf | 489 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) |
dd708413 | 490 | |
7b342a8d | 491 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 492 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 |
f19a3022 | 493 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 |
568997cf | 494 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) |
dd708413 RN |
495 | |
496 | /* Used by CM_WKUP_CLKSTCTRL */ | |
56ef28ac | 497 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 |
f19a3022 | 498 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 |
568997cf | 499 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) |
dd708413 | 500 | |
7b342a8d | 501 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 502 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 |
f19a3022 | 503 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 |
568997cf | 504 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) |
dd708413 | 505 | |
7b342a8d | 506 | /* Used by CM_L3INIT_CLKSTCTRL */ |
56ef28ac | 507 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 |
f19a3022 | 508 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 |
568997cf | 509 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) |
dd708413 RN |
510 | |
511 | /* Used by CM_WKUP_CLKSTCTRL */ | |
56ef28ac | 512 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 |
f19a3022 | 513 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 |
568997cf | 514 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) |
dd708413 | 515 | |
6b54b499 RN |
516 | /* Used by CM_WKUP_CLKSTCTRL */ |
517 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 | |
f19a3022 | 518 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 |
6b54b499 RN |
519 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) |
520 | ||
dd708413 | 521 | /* |
568997cf RN |
522 | * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, |
523 | * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | |
f19a3022 | 524 | * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, |
dd708413 RN |
525 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, |
526 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | |
f19a3022 | 527 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL |
dd708413 | 528 | */ |
56ef28ac | 529 | #define OMAP4430_CLKSEL_SHIFT 24 |
f19a3022 | 530 | #define OMAP4430_CLKSEL_WIDTH 0x1 |
568997cf | 531 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
dd708413 RN |
532 | |
533 | /* | |
534 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, | |
7b342a8d | 535 | * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL |
dd708413 | 536 | */ |
56ef28ac | 537 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
f19a3022 | 538 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 |
568997cf | 539 | #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) |
dd708413 RN |
540 | |
541 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | |
56ef28ac | 542 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
f19a3022 | 543 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 |
568997cf | 544 | #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) |
dd708413 RN |
545 | |
546 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ | |
56ef28ac | 547 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
f19a3022 | 548 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 |
568997cf | 549 | #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) |
dd708413 RN |
550 | |
551 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | |
56ef28ac | 552 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
f19a3022 | 553 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 |
568997cf | 554 | #define OMAP4430_CLKSEL_60M_MASK (1 << 24) |
dd708413 | 555 | |
6b54b499 RN |
556 | /* Used by CM_MPU_MPU_CLKCTRL */ |
557 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 | |
f19a3022 | 558 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 |
6b54b499 RN |
559 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) |
560 | ||
dd708413 | 561 | /* Used by CM1_ABE_AESS_CLKCTRL */ |
56ef28ac | 562 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
f19a3022 | 563 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 |
568997cf | 564 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) |
dd708413 | 565 | |
7b342a8d | 566 | /* Used by CM_CLKSEL_CORE */ |
56ef28ac | 567 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
f19a3022 | 568 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 |
568997cf | 569 | #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) |
dd708413 | 570 | |
7b342a8d | 571 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ |
56ef28ac | 572 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 |
f19a3022 | 573 | #define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 |
568997cf | 574 | #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) |
dd708413 RN |
575 | |
576 | /* Used by CM_WKUP_USIM_CLKCTRL */ | |
56ef28ac | 577 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
f19a3022 | 578 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 |
568997cf | 579 | #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) |
dd708413 | 580 | |
6b54b499 RN |
581 | /* Used by CM_MPU_MPU_CLKCTRL */ |
582 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 | |
f19a3022 | 583 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 |
6b54b499 RN |
584 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) |
585 | ||
dd708413 | 586 | /* Used by CM_CAM_FDIF_CLKCTRL */ |
56ef28ac | 587 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
f19a3022 | 588 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 |
568997cf | 589 | #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) |
dd708413 RN |
590 | |
591 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ | |
56ef28ac | 592 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
f19a3022 | 593 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 |
568997cf | 594 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) |
dd708413 RN |
595 | |
596 | /* | |
597 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, | |
598 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | |
599 | * CM1_ABE_MCBSP3_CLKCTRL | |
600 | */ | |
56ef28ac | 601 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 |
f19a3022 | 602 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 |
568997cf | 603 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) |
dd708413 | 604 | |
7b342a8d | 605 | /* Used by CM_CLKSEL_CORE */ |
56ef28ac | 606 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
f19a3022 | 607 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 |
568997cf | 608 | #define OMAP4430_CLKSEL_L3_MASK (1 << 4) |
dd708413 | 609 | |
7b342a8d | 610 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ |
56ef28ac | 611 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 |
f19a3022 | 612 | #define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 |
568997cf | 613 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) |
dd708413 | 614 | |
7b342a8d | 615 | /* Used by CM_CLKSEL_CORE */ |
56ef28ac | 616 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
f19a3022 | 617 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 |
568997cf | 618 | #define OMAP4430_CLKSEL_L4_MASK (1 << 8) |
dd708413 RN |
619 | |
620 | /* Used by CM_CLKSEL_ABE */ | |
56ef28ac | 621 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
f19a3022 | 622 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 |
568997cf | 623 | #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) |
dd708413 RN |
624 | |
625 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | |
56ef28ac | 626 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
f19a3022 | 627 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 |
568997cf | 628 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) |
dd708413 RN |
629 | |
630 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | |
56ef28ac | 631 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 |
f19a3022 | 632 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 |
568997cf | 633 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
dd708413 RN |
634 | |
635 | /* Used by CM_GFX_GFX_CLKCTRL */ | |
56ef28ac | 636 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 |
f19a3022 | 637 | #define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 |
568997cf | 638 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
dd708413 RN |
639 | |
640 | /* | |
641 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, | |
642 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL | |
643 | */ | |
56ef28ac | 644 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 |
f19a3022 | 645 | #define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 |
568997cf | 646 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
dd708413 RN |
647 | |
648 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ | |
56ef28ac | 649 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 |
f19a3022 | 650 | #define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 |
568997cf | 651 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
dd708413 | 652 | |
7b342a8d | 653 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 654 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
f19a3022 | 655 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 |
568997cf | 656 | #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) |
dd708413 | 657 | |
7b342a8d | 658 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 659 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
f19a3022 | 660 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 |
568997cf | 661 | #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) |
dd708413 RN |
662 | |
663 | /* | |
568997cf RN |
664 | * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, |
665 | * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, | |
666 | * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, | |
7b342a8d BC |
667 | * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, |
668 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, | |
669 | * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, | |
670 | * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL | |
dd708413 | 671 | */ |
56ef28ac | 672 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
f19a3022 | 673 | #define OMAP4430_CLKTRCTRL_WIDTH 0x2 |
568997cf | 674 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
dd708413 RN |
675 | |
676 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | |
56ef28ac | 677 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 |
f19a3022 | 678 | #define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 |
568997cf | 679 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) |
dd708413 RN |
680 | |
681 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | |
56ef28ac | 682 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 |
f19a3022 | 683 | #define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb |
568997cf RN |
684 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) |
685 | ||
686 | /* Used by REVISION_CM1, REVISION_CM2 */ | |
687 | #define OMAP4430_CUSTOM_SHIFT 6 | |
f19a3022 | 688 | #define OMAP4430_CUSTOM_WIDTH 0x2 |
568997cf | 689 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) |
dd708413 | 690 | |
7b342a8d | 691 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 692 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 |
f19a3022 | 693 | #define OMAP4430_D2D_DYNDEP_WIDTH 0x1 |
568997cf | 694 | #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) |
dd708413 RN |
695 | |
696 | /* Used by CM_MPU_STATICDEP */ | |
56ef28ac | 697 | #define OMAP4430_D2D_STATDEP_SHIFT 18 |
f19a3022 | 698 | #define OMAP4430_D2D_STATDEP_WIDTH 0x1 |
568997cf | 699 | #define OMAP4430_D2D_STATDEP_MASK (1 << 18) |
dd708413 | 700 | |
6b54b499 RN |
701 | /* Used by CM_CLKSEL_DPLL_MPU */ |
702 | #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 | |
f19a3022 | 703 | #define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 |
6b54b499 RN |
704 | #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) |
705 | ||
706 | /* Used by CM_CLKSEL_DPLL_MPU */ | |
707 | #define OMAP4460_DCC_EN_SHIFT 22 | |
708 | #define OMAP4460_DCC_EN_MASK (1 << 22) | |
709 | ||
dd708413 | 710 | /* |
568997cf | 711 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, |
7b342a8d BC |
712 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, |
713 | * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, | |
714 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB | |
dd708413 | 715 | */ |
56ef28ac | 716 | #define OMAP4430_DELTAMSTEP_SHIFT 0 |
f19a3022 | 717 | #define OMAP4430_DELTAMSTEP_WIDTH 0x14 |
568997cf | 718 | #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) |
dd708413 | 719 | |
6b54b499 RN |
720 | /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ |
721 | #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 | |
f19a3022 | 722 | #define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 |
6b54b499 RN |
723 | #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) |
724 | ||
7b342a8d BC |
725 | /* Used by CM_DLL_CTRL */ |
726 | #define OMAP4430_DLL_OVERRIDE_SHIFT 0 | |
f19a3022 | 727 | #define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 |
7b342a8d | 728 | #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) |
dd708413 | 729 | |
7b342a8d BC |
730 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ |
731 | #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 | |
f19a3022 | 732 | #define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 |
7b342a8d | 733 | #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) |
dd708413 | 734 | |
7b342a8d | 735 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
56ef28ac | 736 | #define OMAP4430_DLL_RESET_SHIFT 3 |
f19a3022 | 737 | #define OMAP4430_DLL_RESET_WIDTH 0x1 |
568997cf | 738 | #define OMAP4430_DLL_RESET_MASK (1 << 3) |
dd708413 RN |
739 | |
740 | /* | |
7b342a8d BC |
741 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
742 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | |
743 | * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB | |
dd708413 | 744 | */ |
56ef28ac | 745 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
f19a3022 | 746 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 |
568997cf | 747 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) |
dd708413 RN |
748 | |
749 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | |
56ef28ac | 750 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 |
f19a3022 | 751 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 |
568997cf | 752 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) |
dd708413 | 753 | |
7b342a8d | 754 | /* Used by CM_CLKSEL_DPLL_CORE */ |
56ef28ac | 755 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 |
f19a3022 | 756 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 |
568997cf | 757 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) |
dd708413 | 758 | |
7b342a8d | 759 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
56ef28ac | 760 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 |
f19a3022 | 761 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 |
568997cf | 762 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
dd708413 | 763 | |
7b342a8d | 764 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
56ef28ac | 765 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 |
f19a3022 | 766 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 |
568997cf | 767 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) |
dd708413 | 768 | |
7b342a8d | 769 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
56ef28ac | 770 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
f19a3022 | 771 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 |
568997cf | 772 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) |
dd708413 | 773 | |
568997cf | 774 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
56ef28ac | 775 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 |
f19a3022 | 776 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 |
568997cf | 777 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
dd708413 RN |
778 | |
779 | /* | |
7b342a8d BC |
780 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
781 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | |
dd708413 | 782 | */ |
56ef28ac | 783 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
f19a3022 | 784 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 |
568997cf | 785 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
dd708413 RN |
786 | |
787 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ | |
56ef28ac | 788 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 |
f19a3022 | 789 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 |
568997cf | 790 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
dd708413 RN |
791 | |
792 | /* | |
7b342a8d BC |
793 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
794 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | |
dd708413 | 795 | */ |
56ef28ac | 796 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 |
f19a3022 | 797 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 |
568997cf | 798 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) |
dd708413 RN |
799 | |
800 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ | |
56ef28ac | 801 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 |
f19a3022 | 802 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 |
568997cf | 803 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) |
dd708413 RN |
804 | |
805 | /* | |
7b342a8d BC |
806 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
807 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | |
dd708413 | 808 | */ |
56ef28ac | 809 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 |
f19a3022 | 810 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 |
568997cf | 811 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
dd708413 | 812 | |
7b342a8d | 813 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
56ef28ac | 814 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 |
f19a3022 | 815 | #define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 |
568997cf | 816 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) |
dd708413 | 817 | |
7b342a8d | 818 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
56ef28ac | 819 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 |
f19a3022 | 820 | #define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 |
568997cf | 821 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) |
dd708413 | 822 | |
7b342a8d | 823 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
56ef28ac | 824 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 |
f19a3022 | 825 | #define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 |
568997cf | 826 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) |
dd708413 RN |
827 | |
828 | /* | |
7b342a8d BC |
829 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
830 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | |
831 | * CM_CLKSEL_DPLL_UNIPRO | |
dd708413 | 832 | */ |
56ef28ac | 833 | #define OMAP4430_DPLL_DIV_SHIFT 0 |
f19a3022 | 834 | #define OMAP4430_DPLL_DIV_WIDTH 0x7 |
568997cf | 835 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
dd708413 RN |
836 | |
837 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ | |
56ef28ac | 838 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 |
f19a3022 | 839 | #define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 |
568997cf | 840 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
dd708413 RN |
841 | |
842 | /* | |
7b342a8d BC |
843 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
844 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | |
dd708413 | 845 | */ |
56ef28ac | 846 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 |
f19a3022 | 847 | #define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 |
568997cf | 848 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
dd708413 RN |
849 | |
850 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ | |
56ef28ac | 851 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 |
f19a3022 | 852 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 |
568997cf | 853 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) |
dd708413 RN |
854 | |
855 | /* | |
7b342a8d BC |
856 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
857 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
858 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | |
dd708413 | 859 | */ |
56ef28ac | 860 | #define OMAP4430_DPLL_EN_SHIFT 0 |
f19a3022 | 861 | #define OMAP4430_DPLL_EN_WIDTH 0x3 |
568997cf | 862 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
dd708413 RN |
863 | |
864 | /* | |
7b342a8d BC |
865 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
866 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
867 | * CM_CLKMODE_DPLL_UNIPRO | |
dd708413 | 868 | */ |
56ef28ac | 869 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 |
f19a3022 | 870 | #define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 |
568997cf | 871 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
dd708413 RN |
872 | |
873 | /* | |
7b342a8d BC |
874 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
875 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | |
876 | * CM_CLKSEL_DPLL_UNIPRO | |
dd708413 | 877 | */ |
56ef28ac | 878 | #define OMAP4430_DPLL_MULT_SHIFT 8 |
f19a3022 | 879 | #define OMAP4430_DPLL_MULT_WIDTH 0xb |
568997cf | 880 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
dd708413 RN |
881 | |
882 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ | |
56ef28ac | 883 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 |
f19a3022 | 884 | #define OMAP4430_DPLL_MULT_USB_WIDTH 0xc |
568997cf | 885 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
dd708413 RN |
886 | |
887 | /* | |
7b342a8d BC |
888 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
889 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
890 | * CM_CLKMODE_DPLL_UNIPRO | |
dd708413 | 891 | */ |
56ef28ac | 892 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 |
f19a3022 | 893 | #define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 |
568997cf | 894 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
dd708413 RN |
895 | |
896 | /* Used by CM_CLKSEL_DPLL_USB */ | |
56ef28ac | 897 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 |
f19a3022 | 898 | #define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 |
568997cf | 899 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
dd708413 RN |
900 | |
901 | /* | |
7b342a8d BC |
902 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
903 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
904 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | |
dd708413 | 905 | */ |
56ef28ac | 906 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 |
f19a3022 | 907 | #define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 |
568997cf | 908 | #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) |
dd708413 RN |
909 | |
910 | /* | |
7b342a8d BC |
911 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
912 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
913 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | |
dd708413 | 914 | */ |
56ef28ac | 915 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 |
f19a3022 | 916 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 |
568997cf | 917 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) |
dd708413 RN |
918 | |
919 | /* | |
7b342a8d BC |
920 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
921 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | |
922 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | |
dd708413 | 923 | */ |
56ef28ac | 924 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 |
f19a3022 | 925 | #define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 |
568997cf | 926 | #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) |
dd708413 | 927 | |
7b342a8d | 928 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
56ef28ac | 929 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 |
f19a3022 | 930 | #define OMAP4430_DSS_DYNDEP_WIDTH 0x1 |
568997cf | 931 | #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) |
dd708413 | 932 | |
7b342a8d | 933 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
56ef28ac | 934 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
f19a3022 | 935 | #define OMAP4430_DSS_STATDEP_WIDTH 0x1 |
568997cf | 936 | #define OMAP4430_DSS_STATDEP_MASK (1 << 8) |
dd708413 | 937 | |
7b342a8d | 938 | /* Used by CM_L3_2_DYNAMICDEP */ |
56ef28ac | 939 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 |
f19a3022 | 940 | #define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 |
568997cf | 941 | #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) |
dd708413 | 942 | |
7b342a8d | 943 | /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
56ef28ac | 944 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
f19a3022 | 945 | #define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 |
568997cf | 946 | #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) |
dd708413 | 947 | |
7b342a8d | 948 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
56ef28ac | 949 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 |
f19a3022 | 950 | #define OMAP4430_FREQ_UPDATE_WIDTH 0x1 |
568997cf RN |
951 | #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) |
952 | ||
953 | /* Used by REVISION_CM1, REVISION_CM2 */ | |
954 | #define OMAP4430_FUNC_SHIFT 16 | |
f19a3022 | 955 | #define OMAP4430_FUNC_WIDTH 0xc |
568997cf | 956 | #define OMAP4430_FUNC_MASK (0xfff << 16) |
dd708413 | 957 | |
7b342a8d | 958 | /* Used by CM_L3_2_DYNAMICDEP */ |
56ef28ac | 959 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 |
f19a3022 | 960 | #define OMAP4430_GFX_DYNDEP_WIDTH 0x1 |
568997cf | 961 | #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) |
dd708413 RN |
962 | |
963 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | |
56ef28ac | 964 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
f19a3022 | 965 | #define OMAP4430_GFX_STATDEP_WIDTH 0x1 |
568997cf | 966 | #define OMAP4430_GFX_STATDEP_MASK (1 << 10) |
dd708413 | 967 | |
7b342a8d | 968 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
56ef28ac | 969 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 |
f19a3022 | 970 | #define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 |
568997cf | 971 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) |
dd708413 RN |
972 | |
973 | /* | |
7b342a8d BC |
974 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
975 | * CM_DIV_M4_DPLL_PER | |
dd708413 | 976 | */ |
56ef28ac | 977 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
f19a3022 | 978 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 |
568997cf | 979 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
dd708413 RN |
980 | |
981 | /* | |
7b342a8d BC |
982 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
983 | * CM_DIV_M4_DPLL_PER | |
dd708413 | 984 | */ |
56ef28ac | 985 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 |
f19a3022 | 986 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 |
568997cf | 987 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) |
dd708413 RN |
988 | |
989 | /* | |
7b342a8d BC |
990 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
991 | * CM_DIV_M4_DPLL_PER | |
dd708413 | 992 | */ |
56ef28ac | 993 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 |
f19a3022 | 994 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 |
568997cf | 995 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) |
dd708413 RN |
996 | |
997 | /* | |
7b342a8d BC |
998 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
999 | * CM_DIV_M4_DPLL_PER | |
dd708413 | 1000 | */ |
56ef28ac | 1001 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 |
f19a3022 | 1002 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 |
568997cf | 1003 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) |
dd708413 RN |
1004 | |
1005 | /* | |
7b342a8d BC |
1006 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
1007 | * CM_DIV_M5_DPLL_PER | |
dd708413 | 1008 | */ |
56ef28ac | 1009 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
f19a3022 | 1010 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 |
568997cf | 1011 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
dd708413 RN |
1012 | |
1013 | /* | |
7b342a8d BC |
1014 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
1015 | * CM_DIV_M5_DPLL_PER | |
dd708413 | 1016 | */ |
56ef28ac | 1017 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 |
f19a3022 | 1018 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 |
568997cf | 1019 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) |
dd708413 RN |
1020 | |
1021 | /* | |
7b342a8d BC |
1022 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
1023 | * CM_DIV_M5_DPLL_PER | |
dd708413 | 1024 | */ |
56ef28ac | 1025 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 |
f19a3022 | 1026 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 |
568997cf | 1027 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) |
dd708413 RN |
1028 | |
1029 | /* | |
7b342a8d BC |
1030 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
1031 | * CM_DIV_M5_DPLL_PER | |
dd708413 | 1032 | */ |
56ef28ac | 1033 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 |
f19a3022 | 1034 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 |
568997cf | 1035 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) |
dd708413 | 1036 | |
7b342a8d | 1037 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
56ef28ac | 1038 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
f19a3022 | 1039 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 |
568997cf | 1040 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
dd708413 | 1041 | |
7b342a8d | 1042 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
56ef28ac | 1043 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 |
f19a3022 | 1044 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 |
568997cf | 1045 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) |
dd708413 | 1046 | |
7b342a8d | 1047 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
56ef28ac | 1048 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 |
f19a3022 | 1049 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 |
568997cf | 1050 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) |
dd708413 | 1051 | |
7b342a8d | 1052 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
56ef28ac | 1053 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 |
f19a3022 | 1054 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 |
568997cf | 1055 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) |
dd708413 | 1056 | |
7b342a8d | 1057 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
56ef28ac | 1058 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 |
f19a3022 | 1059 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 |
568997cf | 1060 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
dd708413 | 1061 | |
7b342a8d | 1062 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
56ef28ac | 1063 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 |
f19a3022 | 1064 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 |
568997cf | 1065 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) |
dd708413 | 1066 | |
7b342a8d | 1067 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
56ef28ac | 1068 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 |
f19a3022 | 1069 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 |
568997cf | 1070 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) |
dd708413 | 1071 | |
7b342a8d | 1072 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
56ef28ac | 1073 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 |
f19a3022 | 1074 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 |
568997cf RN |
1075 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) |
1076 | ||
1077 | /* | |
1078 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | |
1079 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | |
1080 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | |
1081 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | |
f19a3022 MT |
1082 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, |
1083 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | |
1084 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | |
1085 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | |
1086 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | |
568997cf | 1087 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
f19a3022 MT |
1088 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
1089 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
1090 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | |
1091 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | |
1092 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | |
1093 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | |
1094 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | |
1095 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | |
568997cf RN |
1096 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
1097 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | |
1098 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | |
7b342a8d BC |
1099 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
1100 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | |
f19a3022 MT |
1101 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, |
1102 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | |
1103 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | |
1104 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | |
1105 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | |
1106 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | |
1107 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | |
1108 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | |
568997cf RN |
1109 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
1110 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | |
f19a3022 | 1111 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
568997cf | 1112 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
f19a3022 MT |
1113 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, |
1114 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | |
1115 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | |
dd708413 | 1116 | */ |
56ef28ac | 1117 | #define OMAP4430_IDLEST_SHIFT 16 |
f19a3022 | 1118 | #define OMAP4430_IDLEST_WIDTH 0x2 |
568997cf | 1119 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
dd708413 | 1120 | |
7b342a8d | 1121 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 1122 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 |
f19a3022 | 1123 | #define OMAP4430_ISS_DYNDEP_WIDTH 0x1 |
568997cf | 1124 | #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) |
dd708413 RN |
1125 | |
1126 | /* | |
568997cf | 1127 | * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, |
7b342a8d | 1128 | * CM_TESLA_STATICDEP |
dd708413 | 1129 | */ |
56ef28ac | 1130 | #define OMAP4430_ISS_STATDEP_SHIFT 9 |
f19a3022 | 1131 | #define OMAP4430_ISS_STATDEP_WIDTH 0x1 |
568997cf | 1132 | #define OMAP4430_ISS_STATDEP_MASK (1 << 9) |
dd708413 | 1133 | |
7b342a8d | 1134 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
56ef28ac | 1135 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 |
f19a3022 | 1136 | #define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 |
568997cf | 1137 | #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) |
dd708413 RN |
1138 | |
1139 | /* | |
7b342a8d BC |
1140 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
1141 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, | |
1142 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | |
dd708413 | 1143 | */ |
56ef28ac | 1144 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
f19a3022 | 1145 | #define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 |
568997cf | 1146 | #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) |
dd708413 | 1147 | |
7b342a8d | 1148 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
56ef28ac | 1149 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 |
f19a3022 | 1150 | #define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 |
568997cf | 1151 | #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) |
dd708413 RN |
1152 | |
1153 | /* | |
7b342a8d BC |
1154 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, |
1155 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | |
dd708413 | 1156 | */ |
56ef28ac | 1157 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
f19a3022 | 1158 | #define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 |
568997cf | 1159 | #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) |
dd708413 RN |
1160 | |
1161 | /* | |
568997cf | 1162 | * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, |
7b342a8d | 1163 | * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
dd708413 | 1164 | */ |
56ef28ac | 1165 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 |
f19a3022 | 1166 | #define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 |
568997cf | 1167 | #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) |
dd708413 RN |
1168 | |
1169 | /* | |
7b342a8d BC |
1170 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
1171 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | |
568997cf | 1172 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
7b342a8d | 1173 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
dd708413 | 1174 | */ |
56ef28ac | 1175 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
f19a3022 | 1176 | #define OMAP4430_L3_1_STATDEP_WIDTH 0x1 |
568997cf | 1177 | #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) |
dd708413 RN |
1178 | |
1179 | /* | |
7b342a8d BC |
1180 | * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, |
1181 | * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, | |
1182 | * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | |
1183 | * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP | |
dd708413 | 1184 | */ |
56ef28ac | 1185 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 |
f19a3022 | 1186 | #define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 |
568997cf | 1187 | #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) |
dd708413 RN |
1188 | |
1189 | /* | |
7b342a8d BC |
1190 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
1191 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | |
568997cf | 1192 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
7b342a8d | 1193 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
dd708413 | 1194 | */ |
56ef28ac | 1195 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
f19a3022 | 1196 | #define OMAP4430_L3_2_STATDEP_WIDTH 0x1 |
568997cf | 1197 | #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) |
dd708413 | 1198 | |
7b342a8d | 1199 | /* Used by CM_L3_1_DYNAMICDEP */ |
56ef28ac | 1200 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 |
f19a3022 | 1201 | #define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 |
568997cf | 1202 | #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) |
dd708413 RN |
1203 | |
1204 | /* | |
7b342a8d BC |
1205 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
1206 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | |
dd708413 | 1207 | */ |
56ef28ac | 1208 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
f19a3022 | 1209 | #define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 |
568997cf | 1210 | #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) |
dd708413 | 1211 | |
7b342a8d | 1212 | /* Used by CM_L3_2_DYNAMICDEP */ |
56ef28ac | 1213 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 |
f19a3022 | 1214 | #define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 |
568997cf | 1215 | #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) |
dd708413 RN |
1216 | |
1217 | /* | |
7b342a8d BC |
1218 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
1219 | * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | |
dd708413 | 1220 | */ |
56ef28ac | 1221 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
f19a3022 | 1222 | #define OMAP4430_L4PER_STATDEP_WIDTH 0x1 |
568997cf | 1223 | #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) |
dd708413 | 1224 | |
7b342a8d | 1225 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
56ef28ac | 1226 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 |
f19a3022 | 1227 | #define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 |
568997cf | 1228 | #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) |
dd708413 RN |
1229 | |
1230 | /* | |
568997cf | 1231 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
7b342a8d | 1232 | * CM_SDMA_STATICDEP |
dd708413 | 1233 | */ |
56ef28ac | 1234 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
f19a3022 | 1235 | #define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 |
568997cf | 1236 | #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) |
dd708413 | 1237 | |
7b342a8d | 1238 | /* Used by CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 1239 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 |
f19a3022 | 1240 | #define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 |
568997cf | 1241 | #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) |
dd708413 RN |
1242 | |
1243 | /* | |
568997cf | 1244 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
7b342a8d | 1245 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
dd708413 | 1246 | */ |
56ef28ac | 1247 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
f19a3022 | 1248 | #define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 |
568997cf | 1249 | #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) |
dd708413 RN |
1250 | |
1251 | /* | |
7b342a8d BC |
1252 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
1253 | * CM_MPU_DYNAMICDEP | |
dd708413 | 1254 | */ |
56ef28ac | 1255 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 |
f19a3022 | 1256 | #define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 |
568997cf | 1257 | #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) |
dd708413 RN |
1258 | |
1259 | /* | |
7b342a8d BC |
1260 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
1261 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | |
568997cf | 1262 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
7b342a8d | 1263 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
dd708413 | 1264 | */ |
56ef28ac | 1265 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
f19a3022 | 1266 | #define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 |
568997cf | 1267 | #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) |
dd708413 RN |
1268 | |
1269 | /* | |
568997cf | 1270 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
7b342a8d BC |
1271 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
1272 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | |
1273 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | |
dd708413 | 1274 | */ |
56ef28ac | 1275 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 |
f19a3022 | 1276 | #define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 |
568997cf | 1277 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) |
dd708413 RN |
1278 | |
1279 | /* | |
568997cf | 1280 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
7b342a8d BC |
1281 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
1282 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | |
1283 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | |
dd708413 | 1284 | */ |
56ef28ac | 1285 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 |
f19a3022 | 1286 | #define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 |
568997cf RN |
1287 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) |
1288 | ||
1289 | /* | |
1290 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | |
1291 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | |
1292 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | |
1293 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | |
f19a3022 MT |
1294 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, |
1295 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | |
1296 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | |
1297 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | |
1298 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | |
568997cf | 1299 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
f19a3022 MT |
1300 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
1301 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
1302 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | |
1303 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | |
1304 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | |
1305 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | |
1306 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | |
1307 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | |
568997cf RN |
1308 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
1309 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | |
1310 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | |
7b342a8d BC |
1311 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
1312 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | |
f19a3022 MT |
1313 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, |
1314 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | |
1315 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | |
1316 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | |
1317 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | |
1318 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | |
1319 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | |
1320 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | |
568997cf RN |
1321 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
1322 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | |
f19a3022 | 1323 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
568997cf | 1324 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
f19a3022 MT |
1325 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, |
1326 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | |
1327 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | |
dd708413 | 1328 | */ |
56ef28ac | 1329 | #define OMAP4430_MODULEMODE_SHIFT 0 |
f19a3022 | 1330 | #define OMAP4430_MODULEMODE_WIDTH 0x2 |
568997cf | 1331 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
dd708413 | 1332 | |
6b54b499 RN |
1333 | /* Used by CM_L4CFG_DYNAMICDEP */ |
1334 | #define OMAP4460_MPU_DYNDEP_SHIFT 19 | |
f19a3022 | 1335 | #define OMAP4460_MPU_DYNDEP_WIDTH 0x1 |
6b54b499 RN |
1336 | #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) |
1337 | ||
dd708413 | 1338 | /* Used by CM_DSS_DSS_CLKCTRL */ |
56ef28ac | 1339 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
f19a3022 | 1340 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 |
568997cf | 1341 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) |
dd708413 RN |
1342 | |
1343 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | |
56ef28ac | 1344 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
f19a3022 | 1345 | #define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 |
568997cf | 1346 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) |
dd708413 | 1347 | |
568997cf RN |
1348 | /* Used by CM_ALWON_USBPHY_CLKCTRL */ |
1349 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 | |
f19a3022 | 1350 | #define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 |
568997cf | 1351 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) |
dd708413 RN |
1352 | |
1353 | /* Used by CM_CAM_ISS_CLKCTRL */ | |
56ef28ac | 1354 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
f19a3022 | 1355 | #define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 |
568997cf | 1356 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) |
dd708413 RN |
1357 | |
1358 | /* | |
7b342a8d BC |
1359 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, |
1360 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, | |
1361 | * CM_WKUP_GPIO1_CLKCTRL | |
dd708413 | 1362 | */ |
56ef28ac | 1363 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
f19a3022 | 1364 | #define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 |
568997cf | 1365 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) |
dd708413 RN |
1366 | |
1367 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ | |
56ef28ac | 1368 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 |
f19a3022 | 1369 | #define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 |
568997cf | 1370 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) |
dd708413 RN |
1371 | |
1372 | /* Used by CM_DSS_DSS_CLKCTRL */ | |
56ef28ac | 1373 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
f19a3022 | 1374 | #define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 |
568997cf RN |
1375 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) |
1376 | ||
1377 | /* Used by CM_WKUP_USIM_CLKCTRL */ | |
1378 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 | |
f19a3022 | 1379 | #define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 |
568997cf | 1380 | #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) |
dd708413 RN |
1381 | |
1382 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | |
56ef28ac | 1383 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
f19a3022 | 1384 | #define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 |
568997cf | 1385 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) |
dd708413 RN |
1386 | |
1387 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | |
56ef28ac | 1388 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
f19a3022 | 1389 | #define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 |
568997cf | 1390 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) |
dd708413 RN |
1391 | |
1392 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | |
56ef28ac | 1393 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
f19a3022 | 1394 | #define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 |
568997cf | 1395 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) |
dd708413 | 1396 | |
7b342a8d | 1397 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1398 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
f19a3022 | 1399 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 |
568997cf | 1400 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) |
dd708413 | 1401 | |
7b342a8d | 1402 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1403 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
f19a3022 | 1404 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 |
568997cf | 1405 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) |
dd708413 | 1406 | |
7b342a8d | 1407 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1408 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
f19a3022 | 1409 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 |
568997cf | 1410 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) |
dd708413 | 1411 | |
7b342a8d | 1412 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1413 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
f19a3022 | 1414 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 |
568997cf | 1415 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) |
dd708413 | 1416 | |
7b342a8d | 1417 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1418 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
f19a3022 | 1419 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 |
568997cf | 1420 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) |
dd708413 RN |
1421 | |
1422 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | |
56ef28ac | 1423 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
f19a3022 | 1424 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 |
568997cf | 1425 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) |
dd708413 RN |
1426 | |
1427 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | |
56ef28ac | 1428 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
f19a3022 | 1429 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 |
568997cf | 1430 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) |
dd708413 RN |
1431 | |
1432 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | |
56ef28ac | 1433 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
f19a3022 | 1434 | #define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 |
568997cf | 1435 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) |
dd708413 RN |
1436 | |
1437 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | |
56ef28ac | 1438 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
f19a3022 | 1439 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 |
568997cf | 1440 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) |
dd708413 RN |
1441 | |
1442 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ | |
56ef28ac | 1443 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
f19a3022 | 1444 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 |
568997cf | 1445 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) |
dd708413 RN |
1446 | |
1447 | /* Used by CM_DSS_DSS_CLKCTRL */ | |
56ef28ac | 1448 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
f19a3022 | 1449 | #define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 |
568997cf | 1450 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) |
dd708413 | 1451 | |
6b54b499 RN |
1452 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
1453 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 | |
f19a3022 | 1454 | #define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 |
6b54b499 RN |
1455 | #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) |
1456 | ||
dd708413 | 1457 | /* Used by CM_DSS_DSS_CLKCTRL */ |
56ef28ac | 1458 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
f19a3022 | 1459 | #define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 |
568997cf | 1460 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) |
dd708413 RN |
1461 | |
1462 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ | |
56ef28ac | 1463 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 |
f19a3022 | 1464 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 |
568997cf | 1465 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) |
dd708413 | 1466 | |
7b342a8d | 1467 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
56ef28ac | 1468 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
f19a3022 | 1469 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 |
568997cf | 1470 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) |
dd708413 | 1471 | |
7b342a8d | 1472 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
56ef28ac | 1473 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
f19a3022 | 1474 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 |
568997cf | 1475 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) |
dd708413 | 1476 | |
7b342a8d | 1477 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
56ef28ac | 1478 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
f19a3022 | 1479 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 |
568997cf | 1480 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) |
dd708413 | 1481 | |
7b342a8d | 1482 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1483 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
f19a3022 | 1484 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 |
568997cf | 1485 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) |
dd708413 | 1486 | |
7b342a8d | 1487 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1488 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
f19a3022 | 1489 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 |
568997cf | 1490 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) |
dd708413 | 1491 | |
7b342a8d | 1492 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
56ef28ac | 1493 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
f19a3022 | 1494 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 |
568997cf | 1495 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) |
dd708413 RN |
1496 | |
1497 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | |
56ef28ac | 1498 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
f19a3022 | 1499 | #define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 |
568997cf | 1500 | #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) |
dd708413 | 1501 | |
568997cf | 1502 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
56ef28ac | 1503 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 |
f19a3022 | 1504 | #define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 |
568997cf | 1505 | #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) |
dd708413 RN |
1506 | |
1507 | /* Used by CM_CLKSEL_ABE */ | |
56ef28ac | 1508 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
f19a3022 | 1509 | #define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 |
568997cf | 1510 | #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) |
dd708413 RN |
1511 | |
1512 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ | |
56ef28ac | 1513 | #define OMAP4430_PERF_CURRENT_SHIFT 0 |
f19a3022 | 1514 | #define OMAP4430_PERF_CURRENT_WIDTH 0x8 |
568997cf | 1515 | #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) |
dd708413 RN |
1516 | |
1517 | /* | |
1518 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, | |
1519 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, | |
1520 | * CM_IVA_DVFS_PERF_TESLA | |
1521 | */ | |
56ef28ac | 1522 | #define OMAP4430_PERF_REQ_SHIFT 0 |
f19a3022 | 1523 | #define OMAP4430_PERF_REQ_WIDTH 0x8 |
568997cf | 1524 | #define OMAP4430_PERF_REQ_MASK (0xff << 0) |
dd708413 RN |
1525 | |
1526 | /* Used by CM_RESTORE_ST */ | |
56ef28ac | 1527 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 |
f19a3022 | 1528 | #define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 |
568997cf | 1529 | #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) |
dd708413 RN |
1530 | |
1531 | /* Used by CM_RESTORE_ST */ | |
56ef28ac | 1532 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 |
f19a3022 | 1533 | #define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 |
568997cf | 1534 | #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) |
dd708413 RN |
1535 | |
1536 | /* Used by CM_RESTORE_ST */ | |
56ef28ac | 1537 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 |
f19a3022 | 1538 | #define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 |
568997cf | 1539 | #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) |
dd708413 RN |
1540 | |
1541 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | |
56ef28ac | 1542 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
f19a3022 | 1543 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 |
568997cf | 1544 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) |
dd708413 RN |
1545 | |
1546 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | |
56ef28ac | 1547 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
f19a3022 | 1548 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 |
568997cf | 1549 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) |
dd708413 | 1550 | |
7b342a8d | 1551 | /* Used by CM_DYN_DEP_PRESCAL */ |
56ef28ac | 1552 | #define OMAP4430_PRESCAL_SHIFT 0 |
f19a3022 | 1553 | #define OMAP4430_PRESCAL_WIDTH 0x6 |
568997cf | 1554 | #define OMAP4430_PRESCAL_MASK (0x3f << 0) |
dd708413 | 1555 | |
568997cf RN |
1556 | /* Used by REVISION_CM1, REVISION_CM2 */ |
1557 | #define OMAP4430_R_RTL_SHIFT 11 | |
f19a3022 | 1558 | #define OMAP4430_R_RTL_WIDTH 0x5 |
568997cf | 1559 | #define OMAP4430_R_RTL_MASK (0x1f << 11) |
dd708413 | 1560 | |
7b342a8d | 1561 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ |
56ef28ac | 1562 | #define OMAP4430_SAR_MODE_SHIFT 4 |
f19a3022 | 1563 | #define OMAP4430_SAR_MODE_WIDTH 0x1 |
568997cf | 1564 | #define OMAP4430_SAR_MODE_MASK (1 << 4) |
dd708413 RN |
1565 | |
1566 | /* Used by CM_SCALE_FCLK */ | |
56ef28ac | 1567 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
f19a3022 | 1568 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 |
568997cf RN |
1569 | #define OMAP4430_SCALE_FCLK_MASK (1 << 0) |
1570 | ||
1571 | /* Used by REVISION_CM1, REVISION_CM2 */ | |
1572 | #define OMAP4430_SCHEME_SHIFT 30 | |
f19a3022 | 1573 | #define OMAP4430_SCHEME_WIDTH 0x2 |
568997cf | 1574 | #define OMAP4430_SCHEME_MASK (0x3 << 30) |
dd708413 | 1575 | |
7b342a8d | 1576 | /* Used by CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 1577 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 |
f19a3022 | 1578 | #define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 |
568997cf | 1579 | #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) |
dd708413 RN |
1580 | |
1581 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | |
56ef28ac | 1582 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 |
f19a3022 | 1583 | #define OMAP4430_SDMA_STATDEP_WIDTH 0x1 |
568997cf | 1584 | #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) |
dd708413 RN |
1585 | |
1586 | /* Used by CM_CLKSEL_ABE */ | |
56ef28ac | 1587 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
f19a3022 | 1588 | #define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 |
568997cf | 1589 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) |
dd708413 RN |
1590 | |
1591 | /* | |
568997cf | 1592 | * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, |
f19a3022 MT |
1593 | * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
1594 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | |
dd708413 | 1595 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, |
7b342a8d | 1596 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, |
f19a3022 MT |
1597 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, |
1598 | * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL | |
dd708413 | 1599 | */ |
56ef28ac | 1600 | #define OMAP4430_STBYST_SHIFT 18 |
f19a3022 | 1601 | #define OMAP4430_STBYST_WIDTH 0x1 |
568997cf | 1602 | #define OMAP4430_STBYST_MASK (1 << 18) |
dd708413 RN |
1603 | |
1604 | /* | |
568997cf RN |
1605 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
1606 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | |
1607 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | |
dd708413 | 1608 | */ |
56ef28ac | 1609 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 |
f19a3022 | 1610 | #define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 |
568997cf | 1611 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
dd708413 RN |
1612 | |
1613 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | |
56ef28ac | 1614 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 |
f19a3022 | 1615 | #define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 |
568997cf | 1616 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) |
dd708413 RN |
1617 | |
1618 | /* | |
7b342a8d BC |
1619 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
1620 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | |
dd708413 | 1621 | */ |
56ef28ac | 1622 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 |
f19a3022 | 1623 | #define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 |
568997cf | 1624 | #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) |
dd708413 | 1625 | |
7b342a8d | 1626 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
56ef28ac | 1627 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 |
f19a3022 | 1628 | #define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 |
568997cf | 1629 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) |
dd708413 | 1630 | |
568997cf | 1631 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
56ef28ac | 1632 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 |
f19a3022 | 1633 | #define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 |
568997cf | 1634 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) |
dd708413 RN |
1635 | |
1636 | /* | |
7b342a8d BC |
1637 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
1638 | * CM_DIV_M4_DPLL_PER | |
dd708413 | 1639 | */ |
56ef28ac | 1640 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 |
f19a3022 | 1641 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 |
568997cf | 1642 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) |
dd708413 RN |
1643 | |
1644 | /* | |
7b342a8d BC |
1645 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
1646 | * CM_DIV_M5_DPLL_PER | |
dd708413 | 1647 | */ |
56ef28ac | 1648 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 |
f19a3022 | 1649 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 |
568997cf | 1650 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) |
dd708413 | 1651 | |
7b342a8d | 1652 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
56ef28ac | 1653 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 |
f19a3022 | 1654 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 |
568997cf | 1655 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) |
dd708413 | 1656 | |
7b342a8d | 1657 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
56ef28ac | 1658 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 |
f19a3022 | 1659 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 |
568997cf RN |
1660 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) |
1661 | ||
1662 | /* | |
1663 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | |
1664 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | |
1665 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | |
1666 | */ | |
1667 | #define OMAP4430_ST_MN_BYPASS_SHIFT 8 | |
f19a3022 | 1668 | #define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 |
568997cf | 1669 | #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) |
dd708413 RN |
1670 | |
1671 | /* Used by CM_SYS_CLKSEL */ | |
56ef28ac | 1672 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
f19a3022 | 1673 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 |
568997cf | 1674 | #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) |
dd708413 | 1675 | |
7b342a8d | 1676 | /* Used by CM_L4CFG_DYNAMICDEP */ |
56ef28ac | 1677 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 |
f19a3022 | 1678 | #define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 |
568997cf | 1679 | #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) |
dd708413 RN |
1680 | |
1681 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | |
56ef28ac | 1682 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
f19a3022 | 1683 | #define OMAP4430_TESLA_STATDEP_WIDTH 0x1 |
568997cf | 1684 | #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) |
dd708413 RN |
1685 | |
1686 | /* | |
7b342a8d BC |
1687 | * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, |
1688 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | |
1689 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | |
dd708413 | 1690 | */ |
56ef28ac | 1691 | #define OMAP4430_WINDOWSIZE_SHIFT 24 |
f19a3022 | 1692 | #define OMAP4430_WINDOWSIZE_WIDTH 0x4 |
568997cf RN |
1693 | #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) |
1694 | ||
1695 | /* Used by REVISION_CM1, REVISION_CM2 */ | |
1696 | #define OMAP4430_X_MAJOR_SHIFT 8 | |
f19a3022 | 1697 | #define OMAP4430_X_MAJOR_WIDTH 0x3 |
568997cf RN |
1698 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) |
1699 | ||
1700 | /* Used by REVISION_CM1, REVISION_CM2 */ | |
1701 | #define OMAP4430_Y_MINOR_SHIFT 0 | |
f19a3022 | 1702 | #define OMAP4430_Y_MINOR_WIDTH 0x6 |
568997cf | 1703 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) |
dd708413 | 1704 | #endif |