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dd708413 RN |
1 | /* |
2 | * OMAP44xx Clock Management register bits | |
3 | * | |
f19a3022 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
568997cf | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
dd708413 RN |
6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | |
23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | |
24 | ||
56ef28ac | 25 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
568997cf | 26 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
56ef28ac | 27 | #define OMAP4430_CLKSEL_SHIFT 24 |
f19a3022 | 28 | #define OMAP4430_CLKSEL_WIDTH 0x1 |
568997cf | 29 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
56ef28ac | 30 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
f19a3022 | 31 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 |
56ef28ac | 32 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
f19a3022 | 33 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 |
56ef28ac | 34 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
f19a3022 | 35 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 |
56ef28ac | 36 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
f19a3022 | 37 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 |
56ef28ac | 38 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
f19a3022 | 39 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 |
56ef28ac | 40 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
f19a3022 | 41 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 |
56ef28ac | 42 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
f19a3022 | 43 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 |
56ef28ac | 44 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
f19a3022 | 45 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 |
56ef28ac | 46 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
f19a3022 | 47 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 |
56ef28ac | 48 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
f19a3022 | 49 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 |
56ef28ac | 50 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
f19a3022 | 51 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 |
56ef28ac | 52 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
f19a3022 | 53 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 |
56ef28ac | 54 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
f19a3022 | 55 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 |
568997cf | 56 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
568997cf | 57 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
568997cf | 58 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
568997cf | 59 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
56ef28ac | 60 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
f19a3022 | 61 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 |
56ef28ac | 62 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
f19a3022 | 63 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 |
56ef28ac | 64 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
568997cf | 65 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
56ef28ac | 66 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
f19a3022 | 67 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 |
568997cf | 68 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
56ef28ac | 69 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
568997cf | 70 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
56ef28ac | 71 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
f19a3022 | 72 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 |
568997cf | 73 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
568997cf | 74 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
568997cf | 75 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
568997cf | 76 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
568997cf | 77 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
568997cf | 78 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
568997cf | 79 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
568997cf | 80 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
568997cf | 81 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
568997cf | 82 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
568997cf | 83 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
56ef28ac | 84 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
56ef28ac | 85 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
56ef28ac | 86 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
568997cf | 87 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
568997cf | 88 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
568997cf | 89 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
568997cf | 90 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
56ef28ac | 91 | #define OMAP4430_IDLEST_SHIFT 16 |
568997cf | 92 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
56ef28ac | 93 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
56ef28ac | 94 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
56ef28ac | 95 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
56ef28ac | 96 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
56ef28ac | 97 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
56ef28ac | 98 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
56ef28ac | 99 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
56ef28ac | 100 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
56ef28ac | 101 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
56ef28ac | 102 | #define OMAP4430_MODULEMODE_SHIFT 0 |
568997cf | 103 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
56ef28ac | 104 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
56ef28ac | 105 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
568997cf | 106 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 |
56ef28ac | 107 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
56ef28ac | 108 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
56ef28ac | 109 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
568997cf | 110 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 |
56ef28ac | 111 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
56ef28ac | 112 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
56ef28ac | 113 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
56ef28ac | 114 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
56ef28ac | 115 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
56ef28ac | 116 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
56ef28ac | 117 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
56ef28ac | 118 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
56ef28ac | 119 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
56ef28ac | 120 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
56ef28ac | 121 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
56ef28ac | 122 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
56ef28ac | 123 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
56ef28ac | 124 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
6b54b499 | 125 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 |
56ef28ac | 126 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
56ef28ac | 127 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
56ef28ac | 128 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
56ef28ac | 129 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
56ef28ac | 130 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
56ef28ac | 131 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
56ef28ac | 132 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
56ef28ac | 133 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
56ef28ac | 134 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
56ef28ac | 135 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
f19a3022 | 136 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 |
56ef28ac | 137 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
f19a3022 | 138 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 |
56ef28ac | 139 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
f19a3022 | 140 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 |
56ef28ac | 141 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
568997cf | 142 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
56ef28ac | 143 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
f19a3022 | 144 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 |
56ef28ac | 145 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
dd708413 | 146 | #endif |