[deliverable/linux.git] / arch / arm / mach-omap2 / cm1_44xx.h

/*
 * OMAP44xx CM1 instance offset macros
 *
 * Copyright (C) 2009-2010 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
 *     or "OMAP4430".
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H

/* CM1 base address */
#define OMAP4430_CM1_BASE		0x4a004000

#define OMAP44XX_CM1_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))

/* CM1 instances */
#define OMAP4430_CM1_OCP_SOCKET_INST	0x0000
#define OMAP4430_CM1_CKGEN_INST		0x0100
#define OMAP4430_CM1_MPU_INST		0x0300
#define OMAP4430_CM1_TESLA_INST		0x0400
#define OMAP4430_CM1_ABE_INST		0x0500
#define OMAP4430_CM1_RESTORE_INST	0x0e00
#define OMAP4430_CM1_INSTR_INST		0x0f00

/* CM1 */

/* CM1.OCP_SOCKET_CM1 register offsets */
#define OMAP4_REVISION_CM1_OFFSET			0x0000
#define OMAP4430_REVISION_CM1				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET		0x0040
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)

/* CM1.CKGEN_CM1 register offsets */
#define OMAP4_CM_CLKSEL_CORE_OFFSET			0x0000
#define OMAP4430_CM_CLKSEL_CORE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
#define OMAP4_CM_CLKSEL_ABE_OFFSET			0x0008
#define OMAP4430_CM_CLKSEL_ABE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
#define OMAP4_CM_DLL_CTRL_OFFSET			0x0010
#define OMAP4430_CM_DLL_CTRL				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
#define OMAP4430_CM_CLKMODE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
#define OMAP4430_CM_IDLEST_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c
#define OMAP4430_CM_CLKSEL_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030
#define OMAP4430_CM_DIV_M2_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034
#define OMAP4430_CM_DIV_M3_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET		0x0038
#define OMAP4430_CM_DIV_M4_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET		0x003c
#define OMAP4430_CM_DIV_M5_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET		0x0040
#define OMAP4430_CM_DIV_M6_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET		0x0044
#define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET	0x004c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
#define OMAP4430_CM_CLKMODE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET			0x0064
#define OMAP4430_CM_IDLEST_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068
#define OMAP4430_CM_AUTOIDLE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET			0x006c
#define OMAP4430_CM_CLKSEL_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070
#define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET		0x008c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c
#define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
#define OMAP4430_CM_CLKMODE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET			0x00a4
#define OMAP4430_CM_IDLEST_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8
#define OMAP4430_CM_AUTOIDLE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET			0x00ac
#define OMAP4430_CM_CLKSEL_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET			0x00b8
#define OMAP4430_CM_DIV_M4_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET			0x00bc
#define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET		0x00cc
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc
#define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
#define OMAP4430_CM_CLKMODE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET			0x00e4
#define OMAP4430_CM_IDLEST_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8
#define OMAP4430_CM_AUTOIDLE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET			0x00ec
#define OMAP4430_CM_CLKSEL_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET			0x00f0
#define OMAP4430_CM_DIV_M2_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET			0x00f4
#define OMAP4430_CM_DIV_M3_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET		0x010c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET		0x0120
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET		0x0124
#define OMAP4430_CM_IDLEST_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET		0x0128
#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET		0x012c
#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET		0x0130
#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET		0x0138
#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET		0x013c
#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET		0x0140
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET	0x0148
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET	0x014c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET			0x0170
#define OMAP4430_CM_DYN_DEP_PRESCAL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
#define OMAP4_CM_RESTORE_ST_OFFSET			0x0180
#define OMAP4430_CM_RESTORE_ST				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)

/* CM1.MPU_CM1 register offsets */
#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET			0x0000
#define OMAP4430_CM_MPU_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
#define OMAP4_CM_MPU_STATICDEP_OFFSET			0x0004
#define OMAP4430_CM_MPU_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET			0x0008
#define OMAP4430_CM_MPU_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET			0x0020
#define OMAP4430_CM_MPU_MPU_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)

/* CM1.TESLA_CM1 register offsets */
#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET			0x0000
#define OMAP4430_CM_TESLA_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
#define OMAP4_CM_TESLA_STATICDEP_OFFSET			0x0004
#define OMAP4430_CM_TESLA_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET		0x0008
#define OMAP4430_CM_TESLA_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET		0x0020
#define OMAP4430_CM_TESLA_TESLA_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)

/* CM1.ABE_CM1 register offsets */
#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET			0x0000
#define OMAP4430_CM1_ABE_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET		0x0020
#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET		0x0028
#define OMAP4430_CM1_ABE_AESS_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET		0x0030
#define OMAP4430_CM1_ABE_PDM_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET		0x0038
#define OMAP4430_CM1_ABE_DMIC_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET		0x0040
#define OMAP4430_CM1_ABE_MCASP_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET		0x0048
#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET		0x0050
#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET		0x0058
#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET		0x0060
#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET		0x0068
#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET		0x0070
#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET		0x0078
#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET		0x0080
#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET		0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)

/* CM1.RESTORE_CM1 register offsets */
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET		0x0000
#define OMAP4430_CM_CLKSEL_CORE_RESTORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET	0x0004
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET	0x0008
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET	0x000c
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET	0x0010
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET	0x0014
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET	0x0018
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET	0x001c
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET	0x0020
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET	0x0024
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET	0x0028
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET	0x002c
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET	0x0030
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET	0x0034
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET		0x0038
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET	0x003c
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE	OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET		0x0040
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)

#endif
Commit	Line	Data
d198b514 PW	1	/*
	2	* OMAP44xx CM1 instance offset macros
	3	*
	4	* Copyright (C) 2009-2010 Texas Instruments, Inc.
	5	* Copyright (C) 2009-2010 Nokia Corporation
	6	*
	7	* Paul Walmsley (paul@pwsan.com)
	8	* Rajendra Nayak (rnayak@ti.com)
	9	* Benoit Cousson (b-cousson@ti.com)
	10	*
	11	* This file is automatically generated from the OMAP hardware databases.
	12	* We respectfully ask that any modifications to this file be coordinated
	13	* with the public linux-omap@vger.kernel.org mailing list and the
	14	* authors above to ensure that the autogeneration scripts are kept
	15	* up-to-date with the file contents.
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License version 2 as
	19	* published by the Free Software Foundation.
	20	*
	21	* XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
	22	* or "OMAP4430".
	23	*/
	24
	25	#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
	26	#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
	27
	28	/* CM1 base address */
	29	#define OMAP4430_CM1_BASE 0x4a004000
	30
cdb54c44 PW	31	#define OMAP44XX_CM1_REGADDR(inst, reg) \
cdb54c44 PW	32	OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
d198b514 PW	33
d198b514 PW	34	/* CM1 instances */
cdb54c44 PW	35	#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
	36	#define OMAP4430_CM1_CKGEN_INST 0x0100
	37	#define OMAP4430_CM1_MPU_INST 0x0300
	38	#define OMAP4430_CM1_TESLA_INST 0x0400
	39	#define OMAP4430_CM1_ABE_INST 0x0500
	40	#define OMAP4430_CM1_RESTORE_INST 0x0e00
	41	#define OMAP4430_CM1_INSTR_INST 0x0f00
d198b514 PW	42
	43	/* CM1 */
	44
	45	/* CM1.OCP_SOCKET_CM1 register offsets */
	46	#define OMAP4_REVISION_CM1_OFFSET 0x0000
cdb54c44	47	#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
d198b514	48	#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
cdb54c44	49	#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
d198b514 PW	50
	51	/* CM1.CKGEN_CM1 register offsets */
	52	#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
cdb54c44	53	#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
d198b514	54	#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
cdb54c44	55	#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
d198b514	56	#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
cdb54c44	57	#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
d198b514	58	#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
cdb54c44	59	#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
d198b514	60	#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
cdb54c44	61	#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
d198b514	62	#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
cdb54c44	63	#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
d198b514	64	#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
cdb54c44	65	#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
d198b514	66	#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
cdb54c44	67	#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
d198b514	68	#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
cdb54c44	69	#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
d198b514	70	#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
cdb54c44	71	#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
d198b514	72	#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
cdb54c44	73	#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
d198b514	74	#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
cdb54c44	75	#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
d198b514	76	#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
cdb54c44	77	#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
d198b514	78	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
cdb54c44 PW	79	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
	80	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
	81	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
d198b514	82	#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
cdb54c44	83	#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
d198b514	84	#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
cdb54c44	85	#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
d198b514	86	#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
cdb54c44	87	#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
d198b514	88	#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
cdb54c44	89	#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
d198b514	90	#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
cdb54c44	91	#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
d198b514	92	#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
cdb54c44	93	#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
d198b514	94	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
cdb54c44 PW	95	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
	96	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
	97	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
d198b514	98	#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
cdb54c44	99	#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
d198b514	100	#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
cdb54c44	101	#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
d198b514	102	#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
cdb54c44	103	#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
d198b514	104	#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
cdb54c44	105	#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
d198b514	106	#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
cdb54c44	107	#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
d198b514	108	#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
cdb54c44	109	#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
d198b514	110	#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
cdb54c44	111	#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
d198b514	112	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
cdb54c44 PW	113	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
	114	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
	115	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
d198b514	116	#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
cdb54c44	117	#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
d198b514	118	#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
cdb54c44	119	#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
d198b514	120	#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
cdb54c44	121	#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
d198b514	122	#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
cdb54c44	123	#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
d198b514	124	#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
cdb54c44	125	#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
d198b514	126	#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
cdb54c44	127	#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
d198b514	128	#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
cdb54c44	129	#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
d198b514	130	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
cdb54c44 PW	131	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
	132	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
	133	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
d198b514	134	#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
cdb54c44	135	#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
d198b514	136	#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
cdb54c44	137	#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
d198b514	138	#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
cdb54c44	139	#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
d198b514	140	#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
cdb54c44	141	#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
d198b514	142	#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
cdb54c44	143	#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
d198b514	144	#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
cdb54c44	145	#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
d198b514	146	#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
cdb54c44	147	#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
d198b514	148	#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
cdb54c44	149	#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
d198b514	150	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
cdb54c44 PW	151	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
	152	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
	153	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
d198b514	154	#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
cdb54c44	155	#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
d198b514	156	#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
cdb54c44	157	#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
d198b514	158	#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
cdb54c44	159	#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
d198b514	160	#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
cdb54c44	161	#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
d198b514 PW	162
	163	/* CM1.MPU_CM1 register offsets */
	164	#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
cdb54c44	165	#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
d198b514	166	#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
cdb54c44	167	#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
d198b514	168	#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
cdb54c44	169	#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
d198b514	170	#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
cdb54c44	171	#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
d198b514 PW	172
	173	/* CM1.TESLA_CM1 register offsets */
	174	#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
cdb54c44	175	#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
d198b514	176	#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
cdb54c44	177	#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
d198b514	178	#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
cdb54c44	179	#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
d198b514	180	#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
cdb54c44	181	#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
d198b514 PW	182
	183	/* CM1.ABE_CM1 register offsets */
	184	#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
cdb54c44	185	#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
d198b514	186	#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
cdb54c44	187	#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
d198b514	188	#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
cdb54c44	189	#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
d198b514	190	#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
cdb54c44	191	#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
d198b514	192	#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
cdb54c44	193	#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
d198b514	194	#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
cdb54c44	195	#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
d198b514	196	#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
cdb54c44	197	#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
d198b514	198	#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
cdb54c44	199	#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
d198b514	200	#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
cdb54c44	201	#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
d198b514	202	#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
cdb54c44	203	#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
d198b514	204	#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
cdb54c44	205	#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
d198b514	206	#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
cdb54c44	207	#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
d198b514	208	#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
cdb54c44	209	#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
d198b514	210	#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
cdb54c44	211	#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
d198b514	212	#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
cdb54c44	213	#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
d198b514 PW	214
	215	/* CM1.RESTORE_CM1 register offsets */
	216	#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
cdb54c44	217	#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
d198b514	218	#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
cdb54c44	219	#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
d198b514	220	#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
cdb54c44	221	#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
d198b514	222	#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
cdb54c44	223	#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
d198b514	224	#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
cdb54c44	225	#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
d198b514	226	#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
cdb54c44	227	#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
d198b514	228	#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
cdb54c44	229	#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
d198b514	230	#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
cdb54c44	231	#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
d198b514	232	#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
cdb54c44 PW	233	#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
	234	#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
	235	#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
d198b514	236	#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
cdb54c44	237	#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
d198b514	238	#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
cdb54c44	239	#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
d198b514	240	#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
cdb54c44	241	#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
d198b514	242	#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
cdb54c44	243	#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
d198b514	244	#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
cdb54c44	245	#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
d198b514	246	#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
cdb54c44	247	#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
d198b514	248	#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
cdb54c44	249	#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
d198b514 PW	250
d198b514 PW	251	#endif